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feat(tb): add Vivado XSIM Verilog testbenches for all 10 sync modules

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Add file-based vector testbenches ( + ) for:
- mod_add_sync, rng_sync, poly_arith_sync, comp_decomp_sync
- s_bram/sd_bram, sha3_chain_top
- ntt_core, poly_mul_sync
- sample_cbd_sync, sample_ntt_sync

Each module includes:
- tb_<module>_xsim.v: Vivado XSIM testbench
- gen_vectors.py: Python vector generator (stdlib only)
- vectors/<module>_input.hex: test input vectors
- xsim_run.tcl: compile + elaborate + simulate script
This commit is contained in:
FallenSigh
2026-06-25 20:48:38 +08:00
parent ae5f0ca048
commit d4c3fc86fc
42 changed files with 7745 additions and 0 deletions
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28
sync_rtl/storage/TB/vectors/storage_input.hex Normal file
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0000000000000000
0100000011111111
0200000022222222
0A000000AAAAAAAA
14000000CCCCCCCC
3F000000FFFFFFFF
1E000000DEADBEEF
4000000000000000
4100000011111111
4200000022222222
4A000000AAAAAAAA
54000000CCCCCCCC
7F000000FFFFFFFF
5E000000DEADBEEF
8000000000000000
8100000033333333
8200000044444444
8A00000055555555
BF000000FFFFFFFF
8F000000CAFEBABE
94000000BEEFCAFE
C000000000000000
C100000033333333
C200000044444444
CA00000055555555
FF000000FFFFFFFF
CF000000CAFEBABE
D4000000BEEFCAFE