feat(tb): add Vivado XSIM Verilog testbenches for all 10 sync modules

Add file-based vector testbenches ( + ) for:
- mod_add_sync, rng_sync, poly_arith_sync, comp_decomp_sync
- s_bram/sd_bram, sha3_chain_top
- ntt_core, poly_mul_sync
- sample_cbd_sync, sample_ntt_sync

Each module includes:
- tb_<module>_xsim.v: Vivado XSIM testbench
- gen_vectors.py: Python vector generator (stdlib only)
- vectors/<module>_input.hex: test input vectors
- xsim_run.tcl: compile + elaborate + simulate script

sync_rtl/sample_ntt/TB/xsim_run.tcl

@@ -0,0 +1,56 @@
+# xsim_run.tcl - Vivado xsim compilation and simulation for sample_ntt_sync
+#
+# Compiles sample_ntt_sync RTL + SHA3 dependencies + testbench and runs simulation.
+# Run from the project root: ~/Dev/mlkem/
+#
+# Prerequisites:
+#   source /opt/Xilinx/Vivado/2019.2/settings64.sh
+#
+# Usage:
+#   xsim -runall sync_rtl/sample_ntt/TB/xsim_run.tcl
+#
+#   # Or step-by-step:
+#   vivado -mode batch -source sync_rtl/sample_ntt/TB/xsim_run.tcl
+
+# ================================================================
+# Configuration
+# ================================================================
+set SRC_DIR      sync_rtl/sample_ntt
+set SHA3_DIR     sync_rtl/sha3
+set COMMON_DIR   sync_rtl/common
+set TB_DIR       sync_rtl/sample_ntt/TB
+
+# ================================================================
+# Step 1: Compile all source files (xvlog)
+# ================================================================
+puts "=== Compiling RTL sources ==="
+
+# Keccak round (combinational, used by keccak_core)
+xvlog -sv -include_dirs . ${SHA3_DIR}/keccak_round.v
+
+# Keccak core (24-round sequential core, used by sample_ntt_sync)
+xvlog -sv -include_dirs . ${SHA3_DIR}/keccak_core.v
+
+# sample_ntt_sync (DUT) — uses `include "sync_rtl/common/defines.vh"
+xvlog -sv -include_dirs . ${SRC_DIR}/sample_ntt_sync.v
+
+# ================================================================
+# Step 2: Compile testbench
+# ================================================================
+puts "=== Compiling testbench ==="
+xvlog -sv ${TB_DIR}/tb_sample_ntt_xsim.v
+
+# ================================================================
+# Step 3: Elaborate snapshot (xelab)
+# ================================================================
+puts "=== Elaborating snapshot ==="
+xelab tb_sample_ntt_xsim -s tb_sample_ntt_xsim
+
+# ================================================================
+# Step 4: Run simulation
+# ================================================================
+puts "=== Running simulation ==="
+xsim tb_sample_ntt_xsim -R
+
+puts ""
+puts "=== sample_ntt simulation complete ==="