feat(tb): add Vivado XSIM Verilog testbenches for all 10 sync modules

Add file-based vector testbenches ( + ) for:
- mod_add_sync, rng_sync, poly_arith_sync, comp_decomp_sync
- s_bram/sd_bram, sha3_chain_top
- ntt_core, poly_mul_sync
- sample_cbd_sync, sample_ntt_sync

Each module includes:
- tb_<module>_xsim.v: Vivado XSIM testbench
- gen_vectors.py: Python vector generator (stdlib only)
- vectors/<module>_input.hex: test input vectors
- xsim_run.tcl: compile + elaborate + simulate script

sync_rtl/sample_ntt/TB/vectors/sample_ntt_input.hex

@@ -0,0 +1,4 @@
+0BF6E5D64607BA30905E9F3976195E2B9A0C82BE0DB27480902BA8CA44BAAF0F50
+14EF02248243A8FDAC343C3B298DEA5CEAA2F520D79153B4D3F7009ED90D0E63FA
+24A606EFDC962E55F0BC95332332D82BCC5ACB04497FA99EF06A1D71BF11AF8297
+426F23F87730D6FE0FE18F27180ECA3DE60D0CA77846F40F8D5FB024030E0CEC0F