feat(tb): add Vivado XSIM Verilog testbenches for all 10 sync modules
Add file-based vector testbenches ( + ) for: - mod_add_sync, rng_sync, poly_arith_sync, comp_decomp_sync - s_bram/sd_bram, sha3_chain_top - ntt_core, poly_mul_sync - sample_cbd_sync, sample_ntt_sync Each module includes: - tb_<module>_xsim.v: Vivado XSIM testbench - gen_vectors.py: Python vector generator (stdlib only) - vectors/<module>_input.hex: test input vectors - xsim_run.tcl: compile + elaborate + simulate script
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265
sync_rtl/sample_ntt/TB/tb_sample_ntt_xsim.v
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265
sync_rtl/sample_ntt/TB/tb_sample_ntt_xsim.v
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// tb_sample_ntt_xsim.v - Vivado xsim testbench for sample_ntt_sync
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//
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// Reads test vectors from a hex file using $readmemh.
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// Each line is a packed hex word: {j_idx[1:0], i_idx[1:0], k_i[2:0], rho_i[255:0]}
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// - rho_i[255:0] : 64 hex chars (LSB = rho_i[0])
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// - k_i[2:0] : bits [258:256]
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// - i_idx[1:0] : bits [260:259]
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// - j_idx[1:0] : bits [262:261]
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// - Total: 264 bits = 66 hex chars
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//
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// Drives sample_ntt_sync, waits for valid_o, collects 256 coefficients,
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// and writes results to an output file.
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//
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// Usage:
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// xvlog -sv sample_ntt_sync.v TB/tb_sample_ntt_xsim.v
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// xelab tb_sample_ntt_xsim -s tb_sample_ntt_xsim
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// xsim tb_sample_ntt_xsim -R
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//
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// Prerequisites:
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// - Generate vectors: python3 TB/gen_vectors.py
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// - Output file: vectors/sample_ntt_input.hex
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`timescale 1ns / 1ps
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module tb_sample_ntt_xsim;
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// ================================================================
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// Parameters
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// ================================================================
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parameter VECTOR_FILE = "sync_rtl/sample_ntt/TB/vectors/sample_ntt_input.hex";
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parameter RESULT_FILE = "sync_rtl/sample_ntt/TB/vectors/sample_ntt_result.hex";
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parameter EXPECT_FILE = "sync_rtl/sample_ntt/TB/vectors/sample_ntt_expected.hex";
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parameter MAX_VECTORS = 32;
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parameter TIMEOUT_CYCLES = 50000; // rejection sampling needs many cycles
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parameter N_COEFFS = 256;
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// ================================================================
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// DUT signals
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// ================================================================
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reg clk;
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reg rst_n;
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reg [255:0] rho_i;
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reg [2:0] k_i;
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reg [1:0] i_idx;
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reg [1:0] j_idx;
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reg valid_i;
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wire ready_o;
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wire [11:0] coeff_o;
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wire valid_o;
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reg ready_i;
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wire last_o;
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// ================================================================
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// DUT instantiation
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// ================================================================
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sample_ntt_sync u_dut (
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.clk (clk),
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.rst_n (rst_n),
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.rho_i (rho_i),
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.k_i (k_i),
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.i_idx (i_idx),
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.j_idx (j_idx),
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.valid_i (valid_i),
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.ready_o (ready_o),
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.coeff_o (coeff_o),
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.valid_o (valid_o),
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.ready_i (ready_i),
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.last_o (last_o)
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);
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// ================================================================
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// Clock generation: 100 MHz (10 ns period)
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// ================================================================
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initial clk = 1'b0;
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always #5 clk = ~clk;
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// ================================================================
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// Vector memory (loaded by $readmemh)
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// 264 bits per word: {1'b0, j_idx[1:0], i_idx[1:0], k_i[2:0], rho_i[255:0]}
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// Hex: 66 chars
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// ================================================================
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reg [263:0] vector_mem [0:MAX_VECTORS-1];
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integer vec_count;
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integer idx;
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integer cycle_count;
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integer result_fd;
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integer coeff_idx;
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// Test result tracking
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integer pass_count;
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integer fail_count;
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// ================================================================
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// Hex-to-ASCII conversion helper (for output file)
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// ================================================================
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function [7:0] nibble_to_ascii;
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input [3:0] nibble;
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begin
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if (nibble < 4'd10)
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nibble_to_ascii = 8'h30 + {4'd0, nibble}; // '0'-'9'
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else
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nibble_to_ascii = 8'h41 + ({4'd0, nibble} - 4'd10); // 'A'-'F'
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end
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endfunction
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// ================================================================
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// Main test sequence
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// ================================================================
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initial begin
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vec_count = 0;
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// Load vectors from hex file
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$readmemh(VECTOR_FILE, vector_mem);
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// Count non-zero/X entries to determine actual vector count
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begin
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integer found_end;
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found_end = 0;
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for (idx = 0; idx < MAX_VECTORS; idx = idx + 1) begin
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if (!found_end && (vector_mem[idx] === {264{1'bx}} || vector_mem[idx] === {264{1'bz}}))
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found_end = 1;
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else if (!found_end)
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vec_count = vec_count + 1;
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end
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end
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if (vec_count == 0) begin
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$display("ERROR: No vectors loaded from %s", VECTOR_FILE);
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$display(" Check that the file exists and is in the correct format.");
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$display(" Each line: <66 hex chars> = {j, i, k, rho}");
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$finish;
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end
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$display("INFO: Loaded %0d test vectors from %s", vec_count, VECTOR_FILE);
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// Open result file
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result_fd = $fopen(RESULT_FILE, "w");
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if (result_fd == 0) begin
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$display("ERROR: Cannot open result file: %s", RESULT_FILE);
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$finish;
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end
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// Initialize DUT inputs
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rho_i <= 256'd0;
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k_i <= 3'd0;
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i_idx <= 2'd0;
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j_idx <= 2'd0;
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valid_i <= 1'b0;
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ready_i <= 1'b1; // always ready to accept output
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// Reset sequence: rst_n low for 3 cycles, then high
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rst_n <= 1'b0;
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repeat (3) @(posedge clk);
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rst_n <= 1'b1;
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@(posedge clk);
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pass_count = 0;
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fail_count = 0;
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// ============================================================
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// Process each vector
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// ============================================================
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for (idx = 0; idx < vec_count; idx = idx + 1) begin
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begin
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reg [255:0] vec_rho;
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reg [2:0] vec_k;
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reg [1:0] vec_i;
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reg [1:0] vec_j;
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// Extract fields from packed vector_mem
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// vector_mem[263:0] = {1'b0, j_idx, i_idx, k_i, rho_i}
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vec_rho = vector_mem[idx][255:0];
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vec_k = vector_mem[idx][258:256];
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vec_i = vector_mem[idx][260:259];
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vec_j = vector_mem[idx][262:261];
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$display("INFO: Vector %0d - k=%0d, i=%0d, j=%0d, rho[0:31]=%0h...",
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idx, vec_k, vec_i, vec_j, vec_rho[31:0]);
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// Drive DUT with input
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rho_i <= vec_rho;
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k_i <= vec_k;
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i_idx <= vec_i;
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j_idx <= vec_j;
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valid_i <= 1'b1;
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@(posedge clk);
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valid_i <= 1'b0;
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// Wait for valid_o, then collect all 256 coefficients
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// The DUT uses ready/valid handshake; we set ready_i=1
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coeff_idx = 0;
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cycle_count = 0;
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// Write vector header to result file
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$fwrite(result_fd, "# VECTOR_%0d k=%0d i=%0d j=%0d rho=0x%064h\n",
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idx, vec_k, vec_i, vec_j, vec_rho);
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while (coeff_idx < N_COEFFS && cycle_count < TIMEOUT_CYCLES) begin
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@(posedge clk);
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cycle_count = cycle_count + 1;
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if (valid_o) begin
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// Capture coefficient
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begin
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integer k;
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reg [3:0] nib;
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for (k = 2; k >= 0; k = k - 1) begin
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nib = coeff_o[(k*4)+:4];
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$fwrite(result_fd, "%c", nibble_to_ascii(nib));
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end
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end
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coeff_idx = coeff_idx + 1;
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if (last_o)
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$fwrite(result_fd, " # last at coeff_idx=%0d", coeff_idx);
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$fwrite(result_fd, "\n");
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end
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end
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if (cycle_count >= TIMEOUT_CYCLES) begin
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$display("ERROR: Timeout on vector %0d (got %0d/%0d coefficients)",
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idx, coeff_idx, N_COEFFS);
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fail_count = fail_count + 1;
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end else if (coeff_idx != N_COEFFS) begin
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$display("ERROR: Vector %0d incomplete (got %0d/%0d coefficients)",
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idx, coeff_idx, N_COEFFS);
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fail_count = fail_count + 1;
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end else begin
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$display("INFO: Vector %0d PASSED (%0d coefficients in %0d cycles)",
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idx, coeff_idx, cycle_count);
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pass_count = pass_count + 1;
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end
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// Wait for DUT to return to IDLE before next vector
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// The DUT enters ST_DONE then ST_IDLE automatically
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@(posedge clk);
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end // inner begin block
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end
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// ============================================================
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// Summary
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// ============================================================
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$fclose(result_fd);
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$display("========================================");
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$display("TEST COMPLETE");
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$display(" Total vectors: %0d", vec_count);
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$display(" Passed: %0d", pass_count);
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$display(" Failed: %0d", fail_count);
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$display(" Results written to: %s", RESULT_FILE);
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$display("========================================");
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$finish;
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end
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// ================================================================
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// Timeout watchdog (global)
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// ================================================================
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initial begin
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#(TIMEOUT_CYCLES * 10 * 100); // TIMEOUT_CYCLES * 10ns * extra margin
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$display("FATAL: Global simulation timeout reached");
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$finish;
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end
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endmodule
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