feat(tb): add Vivado XSIM Verilog testbenches for all 10 sync modules

Add file-based vector testbenches ( + ) for:
- mod_add_sync, rng_sync, poly_arith_sync, comp_decomp_sync
- s_bram/sd_bram, sha3_chain_top
- ntt_core, poly_mul_sync
- sample_cbd_sync, sample_ntt_sync

Each module includes:
- tb_<module>_xsim.v: Vivado XSIM testbench
- gen_vectors.py: Python vector generator (stdlib only)
- vectors/<module>_input.hex: test input vectors
- xsim_run.tcl: compile + elaborate + simulate script

sync_rtl/sample_cbd/TB/vectors/sample_cbd_input.hex

@@ -0,0 +1,4 @@
+27F692D88854B85E2DF61697261CCC8931119F593F90A499EA6AD3229F6301D280E
+24A7D2BAA804507EA9069043D6D395FBF42E1BB02BE0A1894B98E8F5F734FE5C22A
+3C7E07D2297A5E9B056F40AA0AF595CB3121E03CCBB86CC25C012EC008D07DC8481
+3A0A67134FA9332AD1430AF5003D24E856EB38A0219B48B68A24C5C85E73AF79026