feat(tb): add Vivado XSIM Verilog testbenches for all 10 sync modules

Add file-based vector testbenches ( + ) for:
- mod_add_sync, rng_sync, poly_arith_sync, comp_decomp_sync
- s_bram/sd_bram, sha3_chain_top
- ntt_core, poly_mul_sync
- sample_cbd_sync, sample_ntt_sync

Each module includes:
- tb_<module>_xsim.v: Vivado XSIM testbench
- gen_vectors.py: Python vector generator (stdlib only)
- vectors/<module>_input.hex: test input vectors
- xsim_run.tcl: compile + elaborate + simulate script

sync_rtl/ntt/TB/xsim_run.tcl

@@ -0,0 +1,62 @@
+# xsim_run.tcl - Vivado xsim compilation and simulation script for NTT
+#
+# Compiles all NTT RTL sources plus testbench and runs simulation.
+# Run from the project root: ~/Dev/mlkem/
+#
+# Prerequisites:
+#   source /opt/Xilinx/Vivado/2019.2/settings64.sh
+#
+# Usage examples:
+#   # Run ntt_core testbench
+#   xsim ntt_core_sim -R
+#
+#   # Step-by-step:
+#   vivado -mode batch -source xsim_run.tcl
+
+# ================================================================
+# Configuration
+# ================================================================
+set SRC_DIR   sync_rtl/ntt
+set TB_DIR    sync_rtl/ntt/TB
+
+# ================================================================
+# Step 1: Compile all source files (xvlog)
+# ================================================================
+puts "=== Compiling RTL sources ==="
+
+# Barrett modular multiplier (combinational)
+xvlog -sv ${SRC_DIR}/barrett_mul.v
+
+# Zeta ROM (combinational)
+xvlog -sv ${SRC_DIR}/zeta_rom.v
+
+# Butterfly unit (combinational, instantiates barrett_mul)
+xvlog -sv ${SRC_DIR}/butterfly_unit.v
+
+# NTT core (FSM-based, instantiates butterfly_unit + zeta_rom + barrett_mul)
+xvlog -sv ${SRC_DIR}/ntt_core.v
+
+# ================================================================
+# Step 2: Compile testbench
+# ================================================================
+puts "=== Compiling testbench ==="
+
+# File-based vector testbench for ntt_core
+xvlog -sv ${TB_DIR}/tb_ntt_core_xsim.v
+
+# ================================================================
+# Step 3: Elaborate (xelab)
+# ================================================================
+puts "=== Elaborating snapshot ==="
+
+xelab tb_ntt_core_xsim -s ntt_core_sim
+
+# ================================================================
+# Step 4: Run simulation
+# ================================================================
+puts ""
+puts "=== Running ntt_core test ==="
+xsim ntt_core_sim -R
+
+puts ""
+puts "=== Simulation complete ==="