feat(tb): add Vivado XSIM Verilog testbenches for all 10 sync modules

Add file-based vector testbenches ( + ) for:
- mod_add_sync, rng_sync, poly_arith_sync, comp_decomp_sync
- s_bram/sd_bram, sha3_chain_top
- ntt_core, poly_mul_sync
- sample_cbd_sync, sample_ntt_sync

Each module includes:
- tb_<module>_xsim.v: Vivado XSIM testbench
- gen_vectors.py: Python vector generator (stdlib only)
- vectors/<module>_input.hex: test input vectors
- xsim_run.tcl: compile + elaborate + simulate script

sync_rtl/mod_add/TB/vectors/mod_add_input.hex

@@ -0,0 +1,39 @@
+000000
+0640c8
+1f43e8
+7d03e8
+5dc5dc
+d00000
+000d00
+bb812c
+12cbb8
+7d05dc
+7d07d0
+9c49c4
+bb83e8
+d00001
+001d00
+d00d00
+7d0d00
+d007d0
+9c43e8
+3e89c4
+4d2834
+1c8b54
+5dc724
+7255dc
+4578ae
+14d1bc
+309760
+bb714d
+1f4af0
+02a02a
+309539
+680680
+0c8c1c
+000001
+001000
+cff002
+3e8919
+032ccf
+6406c1