feat(tb): add Vivado XSIM Verilog testbenches for all 10 sync modules

Add file-based vector testbenches ( + ) for:
- mod_add_sync, rng_sync, poly_arith_sync, comp_decomp_sync
- s_bram/sd_bram, sha3_chain_top
- ntt_core, poly_mul_sync
- sample_cbd_sync, sample_ntt_sync

Each module includes:
- tb_<module>_xsim.v: Vivado XSIM testbench
- gen_vectors.py: Python vector generator (stdlib only)
- vectors/<module>_input.hex: test input vectors
- xsim_run.tcl: compile + elaborate + simulate script

sync_rtl/comp_decomp/TB/xsim_run.tcl

@@ -0,0 +1,60 @@
+# xsim_run.tcl - Vivado xsim compilation and simulation script for comp_decomp_sync
+#
+# Compiles comp_decomp_sync RTL + dependencies + testbench and runs simulation.
+# Run from the project root: ~/Dev/mlkem/
+#
+# Prerequisites:
+#   source /opt/Xilinx/Vivado/2019.2/settings64.sh
+#
+# Usage examples:
+#   # Step-by-step (from Tcl):
+#   xsim -runall xsim_run.tcl
+#
+#   # Or via Vivado batch mode:
+#   vivado -mode batch -source xsim_run.tcl
+#
+#   # Or manually:
+#   xvlog -sv sync_rtl/common/pipeline_reg.v sync_rtl/comp_decomp/comp_decomp_sync.v sync_rtl/comp_decomp/TB/tb_comp_decomp_xsim.v
+#   xelab tb_comp_decomp_xsim -s tb_comp_decomp_xsim
+#   xsim tb_comp_decomp_xsim -R
+
+# ================================================================
+# Configuration
+# ================================================================
+set RTL_DIR  sync_rtl
+set DUT_DIR  sync_rtl/comp_decomp
+set TB_DIR   sync_rtl/comp_decomp/TB
+
+# ================================================================
+# Step 1: Compile all source files (xvlog)
+# ================================================================
+puts "=== Compiling RTL sources for comp_decomp_sync ==="
+
+# Common dependency (pipeline register)
+xvlog -sv -include_dirs . ${RTL_DIR}/common/pipeline_reg.v
+
+# DUT (comp_decomp_sync) — uses `include "sync_rtl/common/defines.vh"
+xvlog -sv -include_dirs . ${DUT_DIR}/comp_decomp_sync.v
+
+# ================================================================
+# Step 2: Compile testbench
+# ================================================================
+puts "=== Compiling testbench ==="
+
+xvlog -sv ${TB_DIR}/tb_comp_decomp_xsim.v
+
+# ================================================================
+# Step 3: Elaborate snapshot (xelab)
+# ================================================================
+puts "=== Elaborating snapshot ==="
+
+xelab tb_comp_decomp_xsim -s tb_comp_decomp_xsim
+
+# ================================================================
+# Step 4: Run simulation
+# ================================================================
+puts "=== Running comp_decomp_sync XSIM test ==="
+xsim tb_comp_decomp_xsim -R
+
+puts ""
+puts "=== Simulation complete ==="