feat(tb): add Vivado XSIM Verilog testbenches for all 10 sync modules
Add file-based vector testbenches ( + ) for: - mod_add_sync, rng_sync, poly_arith_sync, comp_decomp_sync - s_bram/sd_bram, sha3_chain_top - ntt_core, poly_mul_sync - sample_cbd_sync, sample_ntt_sync Each module includes: - tb_<module>_xsim.v: Vivado XSIM testbench - gen_vectors.py: Python vector generator (stdlib only) - vectors/<module>_input.hex: test input vectors - xsim_run.tcl: compile + elaborate + simulate script
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254
sync_rtl/comp_decomp/TB/tb_comp_decomp_xsim.v
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254
sync_rtl/comp_decomp/TB/tb_comp_decomp_xsim.v
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// tb_comp_decomp_xsim.v - Standard Verilog testbench for comp_decomp_sync targeting Vivado xsim
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//
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// Reads test vectors from a hex file using $readmemh.
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// Each line is a 32-bit hex value (8 hex chars, no spaces):
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// bits[31:20] = expected[11:0]
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// bits[19:8] = coeff_in[11:0]
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// bits[7:3] = d[4:0]
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// bit[2] = mode (0=compress, 1=decompress)
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// bits[1:0] = padding
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//
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// Drives comp_decomp_sync, waits for valid_o, compares coeff_out with expected,
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// and reports pass/fail.
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//
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// Parameters:
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// VECTOR_FILE - path to input hex file (default: "sync_rtl/comp_decomp/TB/vectors/comp_decomp_input.hex")
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// RESULT_FILE - path to output file (default: "sync_rtl/comp_decomp/TB/vectors/comp_decomp_result.hex")
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//
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// Usage with xsim_run.tcl or manual:
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// xvlog -sv sync_rtl/common/pipeline_reg.v sync_rtl/comp_decomp/comp_decomp_sync.v tb_comp_decomp_xsim.v
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// xelab tb_comp_decomp_xsim -s tb_comp_decomp_xsim
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// xsim tb_comp_decomp_xsim -R
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`timescale 1ns / 1ps
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module tb_comp_decomp_xsim;
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// ================================================================
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// Parameters
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// ================================================================
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parameter VECTOR_FILE = "sync_rtl/comp_decomp/TB/vectors/comp_decomp_input.hex";
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parameter RESULT_FILE = "sync_rtl/comp_decomp/TB/vectors/comp_decomp_result.hex";
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parameter MAX_VECTORS = 512;
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parameter TIMEOUT_CYCLES = 10000;
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parameter Q = 3329;
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// ================================================================
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// DUT signals
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// ================================================================
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reg clk;
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reg rst_n;
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reg [11:0] coeff_in;
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reg [4:0] d;
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reg mode;
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reg valid_i;
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wire ready_o;
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wire [11:0] coeff_out;
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wire valid_o;
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reg ready_i;
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// ================================================================
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// DUT instantiation (named ports)
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// ================================================================
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comp_decomp_sync u_dut (
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.clk (clk),
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.rst_n (rst_n),
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.coeff_in (coeff_in),
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.d (d),
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.mode (mode),
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.valid_i (valid_i),
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.ready_o (ready_o),
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.coeff_out (coeff_out),
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.valid_o (valid_o),
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.ready_i (ready_i)
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);
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// ================================================================
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// Clock generation: 100 MHz (10 ns period)
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// ================================================================
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initial clk = 1'b0;
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always #5 clk = ~clk;
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// ================================================================
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// Vector memory (loaded by $readmemh)
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// 32 bits per word:
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// bits[31:20] = expected
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// bits[19:8] = coeff_in
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// bits[7:3] = d
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// bit[2] = mode
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// bits[1:0] = padding
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// ================================================================
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reg [31:0] vector_mem [0:MAX_VECTORS-1];
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integer vec_count;
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integer idx;
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integer cycle_count;
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integer result_fd;
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// Test result tracking
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integer pass_count;
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integer fail_count;
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// ================================================================
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// Hex-to-ASCII conversion helper
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// ================================================================
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function [7:0] nibble_to_ascii;
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input [3:0] nibble;
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begin
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if (nibble < 4'd10)
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nibble_to_ascii = 8'h30 + {4'd0, nibble}; // '0'-'9'
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else
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nibble_to_ascii = 8'h41 + ({4'd0, nibble} - 4'd10); // 'A'-'F'
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end
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endfunction
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// ================================================================
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// Main test sequence
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// ================================================================
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initial begin
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// Count loaded vectors
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vec_count = 0;
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// Load vectors from hex file
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$readmemh(VECTOR_FILE, vector_mem);
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// Count non-X/non-Z entries to determine actual vector count
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begin
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integer found_end;
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found_end = 0;
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for (idx = 0; idx < MAX_VECTORS; idx = idx + 1) begin
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if (!found_end && (vector_mem[idx] === 32'hx || vector_mem[idx] === 32'hz))
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found_end = 1;
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else if (!found_end)
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vec_count = vec_count + 1;
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end
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end
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if (vec_count == 0) begin
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$display("ERROR: No vectors loaded from %s", VECTOR_FILE);
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$display(" Check that the file exists and is in the correct format.");
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$display(" Each line: <8 hex chars> = {expected[11:0], coeff_in[11:0], d[4:0], mode, 2'b0}");
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$finish;
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end
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$display("INFO: Loaded %0d test vectors from %s", vec_count, VECTOR_FILE);
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// Open result file
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result_fd = $fopen(RESULT_FILE, "w");
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if (result_fd == 0) begin
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$display("ERROR: Cannot open result file: %s", RESULT_FILE);
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$finish;
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end
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// Initialize DUT inputs
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coeff_in <= 12'd0;
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d <= 5'd0;
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mode <= 1'b0;
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valid_i <= 1'b0;
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ready_i <= 1'b1; // always ready to accept output
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// Reset sequence: rst_n low for 3 cycles, then high
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rst_n <= 1'b0;
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repeat (3) @(posedge clk);
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rst_n <= 1'b1;
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@(posedge clk);
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pass_count = 0;
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fail_count = 0;
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// ============================================================
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// Process each vector
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// ============================================================
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for (idx = 0; idx < vec_count; idx = idx + 1) begin
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begin
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reg [11:0] vec_expected;
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reg [11:0] vec_coeff_in;
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reg [4:0] vec_d;
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reg vec_mode;
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reg [11:0] captured_out;
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// Extract fields from vector
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vec_expected = vector_mem[idx][31:20];
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vec_coeff_in = vector_mem[idx][19:8];
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vec_d = vector_mem[idx][7:3];
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vec_mode = vector_mem[idx][2];
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$display("INFO: Vector %0d - coeff=%0d d=%0d mode=%s expected=%0d",
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idx, vec_coeff_in, vec_d,
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vec_mode ? "DECOMPRESS" : "COMPRESS", vec_expected);
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// Drive DUT inputs
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coeff_in <= vec_coeff_in;
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d <= vec_d;
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mode <= vec_mode;
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valid_i <= 1'b1;
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@(posedge clk);
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valid_i <= 1'b0;
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// Wait for valid_o assertion (1 pipeline stage latency)
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cycle_count = 0;
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while (!valid_o && cycle_count < TIMEOUT_CYCLES) begin
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@(posedge clk);
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cycle_count = cycle_count + 1;
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end
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if (cycle_count >= TIMEOUT_CYCLES) begin
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$display("ERROR: Timeout waiting for valid_o on vector %0d", idx);
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fail_count = fail_count + 1;
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$fwrite(result_fd, "RESULT: VECTOR %0d TIMEOUT\n", idx);
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end else begin
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// Capture output (valid_o is high, coeff_out is valid)
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captured_out = coeff_out;
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// Compare with expected
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if (captured_out == vec_expected) begin
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pass_count = pass_count + 1;
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$fwrite(result_fd, "PASS: %0d - mode=%s coeff=%03X d=%0d expected=%03X got=%03X\n",
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idx, vec_mode ? "DECOMPRESS" : "COMPRESS",
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vec_coeff_in, vec_d, vec_expected, captured_out);
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end else begin
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$display("FAIL: Vector %0d - mode=%s coeff=%0d d=%0d expected=%0d got=%0d",
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idx, vec_mode ? "DECOMPRESS" : "COMPRESS",
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vec_coeff_in, vec_d, vec_expected, captured_out);
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fail_count = fail_count + 1;
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$fwrite(result_fd, "FAIL: %0d - mode=%s coeff=%03X d=%0d expected=%03X got=%03X\n",
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idx, vec_mode ? "DECOMPRESS" : "COMPRESS",
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vec_coeff_in, vec_d, vec_expected, captured_out);
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end
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end
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// One extra cycle for valid_o -> ready_i handshake (pipeline clears valid_o)
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@(posedge clk);
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end
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end
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// ============================================================
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// Summary
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// ============================================================
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$fclose(result_fd);
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$display("========================================");
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$display("TEST COMPLETE");
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$display(" Total vectors: %0d", vec_count);
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$display(" Passed: %0d", pass_count);
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$display(" Failed: %0d", fail_count);
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$display(" Results written to: %s", RESULT_FILE);
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if (fail_count == 0) begin
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$display(" STATUS: ALL TESTS PASSED");
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end else begin
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$display(" STATUS: %0d FAILURE(S) DETECTED", fail_count);
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end
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$display("========================================");
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$finish;
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end
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// ================================================================
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// Timeout watchdog (TIMEOUT_CYCLES * 10ns * vectors * margin)
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// ================================================================
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initial begin
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#(TIMEOUT_CYCLES * 10 * MAX_VECTORS * 2);
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$display("FATAL: Global simulation timeout reached");
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$finish;
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end
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endmodule
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