feat(tb): add Vivado XSIM Verilog testbenches for all 10 sync modules
Add file-based vector testbenches ( + ) for: - mod_add_sync, rng_sync, poly_arith_sync, comp_decomp_sync - s_bram/sd_bram, sha3_chain_top - ntt_core, poly_mul_sync - sample_cbd_sync, sample_ntt_sync Each module includes: - tb_<module>_xsim.v: Vivado XSIM testbench - gen_vectors.py: Python vector generator (stdlib only) - vectors/<module>_input.hex: test input vectors - xsim_run.tcl: compile + elaborate + simulate script
This commit is contained in:
179
sync_rtl/comp_decomp/TB/gen_vectors.py
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179
sync_rtl/comp_decomp/TB/gen_vectors.py
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#!/usr/bin/env python3
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"""gen_vectors.py - Generate test vectors for comp_decomp_sync XSIM testbench.
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Produces sync_rtl/comp_decomp/TB/vectors/comp_decomp_input.hex
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Each line is a 32-bit hex value (8 hex chars, no spaces):
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bits[31:26] = padding (0)
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bits[25:14] = expected[11:0]
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bits[13:2] = coeff_in[11:0]
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bit[1] = d[0] (d[4:0] split across bits [6:2] and bit[1])
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bit[0] = mode (0=compress, 1=decompress)
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Revised layout (cleaner, 32 bits):
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bits[31:20] = expected[11:0]
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bits[19:8] = coeff_in[11:0]
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bits[7:3] = d[4:0]
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bit[2] = mode (0=compress, 1=decompress)
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bits[1:0] = padding (0)
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FIPS 203 formulas:
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Compress_q(x, d) = round((2^d / Q) * x) mod 2^d
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= ((x * 2^d + Q//2) // Q) & ((1 << d) - 1)
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Decompress_q(y, d) = round((Q / 2^d) * y)
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= (y * Q + (1 << (d-1))) // (1 << d)
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Tests cover d in {4, 5, 10, 11} (ML-KEM standard values) plus edge d=1.
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"""
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import os
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import sys
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Q = 3329
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OUTPUT_DIR = os.path.join(os.path.dirname(os.path.abspath(__file__)), "vectors")
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OUTPUT_FILE = os.path.join(OUTPUT_DIR, "comp_decomp_input.hex")
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def compress_q(x: int, d: int) -> int:
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"""Compress_q(x, d) per FIPS 203."""
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if d == 0:
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return 0
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two_d = 1 << d
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# round((2^d / Q) * x) = floor((x * 2^d + Q/2) / Q)
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val = (x * two_d + Q // 2) // Q
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return val & (two_d - 1)
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def decompress_q(y: int, d: int) -> int:
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"""Decompress_q(y, d) per FIPS 203."""
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if d == 0:
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return 0
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two_d = 1 << d
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# round((Q / 2^d) * y) = floor((y * Q + 2^(d-1)) / 2^d)
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val = (y * Q + (two_d >> 1)) // two_d
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return val % Q
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def pack_vector(expected: int, coeff_in: int, d: int, mode: int) -> int:
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"""Pack a single test vector into a 32-bit value."""
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val = 0
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val |= (expected & 0xFFF) << 20 # bits 31:20
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val |= (coeff_in & 0xFFF) << 8 # bits 19:8
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val |= (d & 0x1F) << 3 # bits 7:3
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val |= (mode & 0x1) << 2 # bit 2
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# bits 1:0 are padding = 0
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return val
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def generate() -> list[int]:
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"""Generate all test vectors. Returns list of packed 32-bit values."""
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vectors: list[int] = []
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def add_vector(x: int, d: int, mode: int) -> None:
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if mode == 0:
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exp = compress_q(x, d)
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else:
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exp = decompress_q(x, d)
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vectors.append(pack_vector(exp, x, d, mode))
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# Standard ML-KEM d values
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d_values = [4, 5, 10, 11]
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# Test coefficient values: edges and mid-range
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coeffs = [
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0, # zero
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1, # minimal
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3328, # max (Q-1)
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1000, # mid-range
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2000, # mid-range
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1664, # Q/2
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42, # small
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]
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# ---- COMPRESS (mode=0) ----
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for d in d_values:
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for c in coeffs:
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add_vector(c, d, 0)
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# Compress edge: max input
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add_vector(3328, d, 0)
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# Compress: some systematic sweep
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for c in [0, 500, 1000, 1500, 2000, 2500, 3000, 3328]:
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add_vector(c, d, 0)
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# ---- DECOMPRESS (mode=1) ----
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# For decompress, input is in [0, 2^d-1]
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for d in d_values:
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two_d_mask = (1 << d) - 1
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# Zero
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add_vector(0, d, 1)
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# Max in range
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add_vector(two_d_mask, d, 1)
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# Mid-range
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mid = two_d_mask // 2
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if mid > 0:
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add_vector(mid, d, 1)
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add_vector(mid - 1, d, 1) if mid > 1 else None
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add_vector(mid + 1, d, 1) if mid + 1 <= two_d_mask else None
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# Systematic sweep through valid range
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step = max(1, two_d_mask // 8)
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for y in range(0, two_d_mask + 1, step):
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add_vector(y, d, 1)
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# ---- Edge case: d=1 (minimum non-zero) ----
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add_vector(0, 1, 0)
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add_vector(3328, 1, 0)
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add_vector(0, 1, 1)
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add_vector(1, 1, 1)
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# ---- d=12 (max for 12-bit operands, though not in ML-KEM) ----
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add_vector(0, 12, 0)
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add_vector(3328, 12, 0)
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return vectors
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def write_vectors(vectors: list[int]) -> None:
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"""Write vectors to hex file."""
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os.makedirs(OUTPUT_DIR, exist_ok=True)
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with open(OUTPUT_FILE, "w") as f:
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for v in vectors:
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# 32 bits = 8 hex digits
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f.write(f"{v:08X}\n")
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print(f"Generated {len(vectors)} test vectors -> {OUTPUT_FILE}")
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def main() -> int:
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vectors = generate()
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write_vectors(vectors)
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# Print statistics and samples
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print(f"\nTotal vectors: {len(vectors)}")
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compress_count = sum(1 for v in vectors if ((v >> 2) & 1) == 0)
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decompress_count = sum(1 for v in vectors if ((v >> 2) & 1) == 1)
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print(f" Compress: {compress_count}")
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print(f" Decompress: {decompress_count}")
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print("\nSample vectors (first 5):")
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for i, v in enumerate(vectors[:5]):
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exp = (v >> 20) & 0xFFF
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coeff = (v >> 8) & 0xFFF
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d = (v >> 3) & 0x1F
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mode = (v >> 2) & 0x1
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op = "COMPRESS" if mode == 0 else "DECOMPRESS"
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if mode == 0:
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print(f" [{i}] {op} x={coeff:04d} d={d:02d} expected={exp:04d}")
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else:
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print(f" [{i}] {op} y={coeff:04d} d={d:02d} expected={exp:04d}")
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return 0
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if __name__ == "__main__":
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sys.exit(main())
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254
sync_rtl/comp_decomp/TB/tb_comp_decomp_xsim.v
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254
sync_rtl/comp_decomp/TB/tb_comp_decomp_xsim.v
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@@ -0,0 +1,254 @@
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// tb_comp_decomp_xsim.v - Standard Verilog testbench for comp_decomp_sync targeting Vivado xsim
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//
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// Reads test vectors from a hex file using $readmemh.
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// Each line is a 32-bit hex value (8 hex chars, no spaces):
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// bits[31:20] = expected[11:0]
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// bits[19:8] = coeff_in[11:0]
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// bits[7:3] = d[4:0]
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// bit[2] = mode (0=compress, 1=decompress)
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// bits[1:0] = padding
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//
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// Drives comp_decomp_sync, waits for valid_o, compares coeff_out with expected,
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// and reports pass/fail.
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//
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// Parameters:
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// VECTOR_FILE - path to input hex file (default: "sync_rtl/comp_decomp/TB/vectors/comp_decomp_input.hex")
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// RESULT_FILE - path to output file (default: "sync_rtl/comp_decomp/TB/vectors/comp_decomp_result.hex")
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//
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// Usage with xsim_run.tcl or manual:
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// xvlog -sv sync_rtl/common/pipeline_reg.v sync_rtl/comp_decomp/comp_decomp_sync.v tb_comp_decomp_xsim.v
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// xelab tb_comp_decomp_xsim -s tb_comp_decomp_xsim
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// xsim tb_comp_decomp_xsim -R
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`timescale 1ns / 1ps
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module tb_comp_decomp_xsim;
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// ================================================================
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// Parameters
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// ================================================================
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parameter VECTOR_FILE = "sync_rtl/comp_decomp/TB/vectors/comp_decomp_input.hex";
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parameter RESULT_FILE = "sync_rtl/comp_decomp/TB/vectors/comp_decomp_result.hex";
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parameter MAX_VECTORS = 512;
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parameter TIMEOUT_CYCLES = 10000;
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parameter Q = 3329;
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// ================================================================
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// DUT signals
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// ================================================================
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reg clk;
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reg rst_n;
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reg [11:0] coeff_in;
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reg [4:0] d;
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reg mode;
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reg valid_i;
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wire ready_o;
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wire [11:0] coeff_out;
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wire valid_o;
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reg ready_i;
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// ================================================================
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// DUT instantiation (named ports)
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// ================================================================
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comp_decomp_sync u_dut (
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.clk (clk),
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.rst_n (rst_n),
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.coeff_in (coeff_in),
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.d (d),
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.mode (mode),
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.valid_i (valid_i),
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.ready_o (ready_o),
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.coeff_out (coeff_out),
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.valid_o (valid_o),
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.ready_i (ready_i)
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);
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// ================================================================
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// Clock generation: 100 MHz (10 ns period)
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// ================================================================
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initial clk = 1'b0;
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always #5 clk = ~clk;
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// ================================================================
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// Vector memory (loaded by $readmemh)
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// 32 bits per word:
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// bits[31:20] = expected
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// bits[19:8] = coeff_in
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// bits[7:3] = d
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// bit[2] = mode
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// bits[1:0] = padding
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// ================================================================
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reg [31:0] vector_mem [0:MAX_VECTORS-1];
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integer vec_count;
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integer idx;
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integer cycle_count;
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integer result_fd;
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// Test result tracking
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integer pass_count;
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integer fail_count;
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// ================================================================
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// Hex-to-ASCII conversion helper
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// ================================================================
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function [7:0] nibble_to_ascii;
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input [3:0] nibble;
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begin
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if (nibble < 4'd10)
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nibble_to_ascii = 8'h30 + {4'd0, nibble}; // '0'-'9'
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else
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nibble_to_ascii = 8'h41 + ({4'd0, nibble} - 4'd10); // 'A'-'F'
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end
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endfunction
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// ================================================================
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// Main test sequence
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// ================================================================
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initial begin
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// Count loaded vectors
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vec_count = 0;
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// Load vectors from hex file
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$readmemh(VECTOR_FILE, vector_mem);
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// Count non-X/non-Z entries to determine actual vector count
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begin
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integer found_end;
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found_end = 0;
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for (idx = 0; idx < MAX_VECTORS; idx = idx + 1) begin
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if (!found_end && (vector_mem[idx] === 32'hx || vector_mem[idx] === 32'hz))
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found_end = 1;
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else if (!found_end)
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vec_count = vec_count + 1;
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end
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end
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if (vec_count == 0) begin
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$display("ERROR: No vectors loaded from %s", VECTOR_FILE);
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$display(" Check that the file exists and is in the correct format.");
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$display(" Each line: <8 hex chars> = {expected[11:0], coeff_in[11:0], d[4:0], mode, 2'b0}");
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$finish;
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end
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$display("INFO: Loaded %0d test vectors from %s", vec_count, VECTOR_FILE);
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// Open result file
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result_fd = $fopen(RESULT_FILE, "w");
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if (result_fd == 0) begin
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$display("ERROR: Cannot open result file: %s", RESULT_FILE);
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$finish;
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end
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// Initialize DUT inputs
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coeff_in <= 12'd0;
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d <= 5'd0;
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mode <= 1'b0;
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valid_i <= 1'b0;
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ready_i <= 1'b1; // always ready to accept output
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// Reset sequence: rst_n low for 3 cycles, then high
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rst_n <= 1'b0;
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repeat (3) @(posedge clk);
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rst_n <= 1'b1;
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@(posedge clk);
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pass_count = 0;
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fail_count = 0;
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// ============================================================
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// Process each vector
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// ============================================================
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for (idx = 0; idx < vec_count; idx = idx + 1) begin
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begin
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reg [11:0] vec_expected;
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reg [11:0] vec_coeff_in;
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reg [4:0] vec_d;
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reg vec_mode;
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reg [11:0] captured_out;
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// Extract fields from vector
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vec_expected = vector_mem[idx][31:20];
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vec_coeff_in = vector_mem[idx][19:8];
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vec_d = vector_mem[idx][7:3];
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vec_mode = vector_mem[idx][2];
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$display("INFO: Vector %0d - coeff=%0d d=%0d mode=%s expected=%0d",
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idx, vec_coeff_in, vec_d,
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vec_mode ? "DECOMPRESS" : "COMPRESS", vec_expected);
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// Drive DUT inputs
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coeff_in <= vec_coeff_in;
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d <= vec_d;
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mode <= vec_mode;
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valid_i <= 1'b1;
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@(posedge clk);
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valid_i <= 1'b0;
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// Wait for valid_o assertion (1 pipeline stage latency)
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cycle_count = 0;
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while (!valid_o && cycle_count < TIMEOUT_CYCLES) begin
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@(posedge clk);
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cycle_count = cycle_count + 1;
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end
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if (cycle_count >= TIMEOUT_CYCLES) begin
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$display("ERROR: Timeout waiting for valid_o on vector %0d", idx);
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fail_count = fail_count + 1;
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$fwrite(result_fd, "RESULT: VECTOR %0d TIMEOUT\n", idx);
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end else begin
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// Capture output (valid_o is high, coeff_out is valid)
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captured_out = coeff_out;
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// Compare with expected
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if (captured_out == vec_expected) begin
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pass_count = pass_count + 1;
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$fwrite(result_fd, "PASS: %0d - mode=%s coeff=%03X d=%0d expected=%03X got=%03X\n",
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idx, vec_mode ? "DECOMPRESS" : "COMPRESS",
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vec_coeff_in, vec_d, vec_expected, captured_out);
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end else begin
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$display("FAIL: Vector %0d - mode=%s coeff=%0d d=%0d expected=%0d got=%0d",
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idx, vec_mode ? "DECOMPRESS" : "COMPRESS",
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vec_coeff_in, vec_d, vec_expected, captured_out);
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fail_count = fail_count + 1;
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$fwrite(result_fd, "FAIL: %0d - mode=%s coeff=%03X d=%0d expected=%03X got=%03X\n",
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idx, vec_mode ? "DECOMPRESS" : "COMPRESS",
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vec_coeff_in, vec_d, vec_expected, captured_out);
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end
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end
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// One extra cycle for valid_o -> ready_i handshake (pipeline clears valid_o)
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@(posedge clk);
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end
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end
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// ============================================================
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// Summary
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// ============================================================
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$fclose(result_fd);
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$display("========================================");
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$display("TEST COMPLETE");
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$display(" Total vectors: %0d", vec_count);
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$display(" Passed: %0d", pass_count);
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$display(" Failed: %0d", fail_count);
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$display(" Results written to: %s", RESULT_FILE);
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if (fail_count == 0) begin
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$display(" STATUS: ALL TESTS PASSED");
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end else begin
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$display(" STATUS: %0d FAILURE(S) DETECTED", fail_count);
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end
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$display("========================================");
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$finish;
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end
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// ================================================================
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// Timeout watchdog (TIMEOUT_CYCLES * 10ns * vectors * margin)
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// ================================================================
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initial begin
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#(TIMEOUT_CYCLES * 10 * MAX_VECTORS * 2);
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$display("FATAL: Global simulation timeout reached");
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$finish;
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end
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endmodule
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135
sync_rtl/comp_decomp/TB/vectors/comp_decomp_input.hex
Normal file
135
sync_rtl/comp_decomp/TB/vectors/comp_decomp_input.hex
Normal file
@@ -0,0 +1,135 @@
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00000020
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00000120
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000D0020
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0053E820
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00A7D020
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00868020
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00002A20
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000D0020
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00000020
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0021F420
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0053E820
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||||
0075DC20
|
||||
00A7D020
|
||||
00C9C420
|
||||
00EBB820
|
||||
000D0020
|
||||
00000028
|
||||
00000128
|
||||
000D0028
|
||||
00A3E828
|
||||
0137D028
|
||||
01068028
|
||||
00002A28
|
||||
000D0028
|
||||
00000028
|
||||
0051F428
|
||||
00A3E828
|
||||
00E5DC28
|
||||
0137D028
|
||||
0189C428
|
||||
01DBB828
|
||||
000D0028
|
||||
00000050
|
||||
00000150
|
||||
000D0050
|
||||
1343E850
|
||||
2677D050
|
||||
20068050
|
||||
00D02A50
|
||||
000D0050
|
||||
00000050
|
||||
09A1F450
|
||||
1343E850
|
||||
1CD5DC50
|
||||
2677D050
|
||||
3019C450
|
||||
39BBB850
|
||||
000D0050
|
||||
00000058
|
||||
00100158
|
||||
7FFD0058
|
||||
2673E858
|
||||
4CE7D058
|
||||
40068058
|
||||
01A02A58
|
||||
7FFD0058
|
||||
00000058
|
||||
1341F458
|
||||
2673E858
|
||||
39B5DC58
|
||||
4CE7D058
|
||||
6029C458
|
||||
736BB858
|
||||
7FFD0058
|
||||
00000024
|
||||
C3100F24
|
||||
5B000724
|
||||
4E000624
|
||||
68100824
|
||||
00000024
|
||||
0D000124
|
||||
1A000224
|
||||
27000324
|
||||
34000424
|
||||
41000524
|
||||
4E000624
|
||||
5B000724
|
||||
68100824
|
||||
75100924
|
||||
82100A24
|
||||
8F100B24
|
||||
9C100C24
|
||||
A9100D24
|
||||
B6100E24
|
||||
C3100F24
|
||||
0000002C
|
||||
C9901F2C
|
||||
61800F2C
|
||||
5B000E2C
|
||||
6810102C
|
||||
0000002C
|
||||
1380032C
|
||||
2700062C
|
||||
3A80092C
|
||||
4E000C2C
|
||||
61800F2C
|
||||
7510122C
|
||||
8890152C
|
||||
9C10182C
|
||||
AF901B2C
|
||||
C3101E2C
|
||||
00000054
|
||||
CFE3FF54
|
||||
67D1FF54
|
||||
67A1FE54
|
||||
68120054
|
||||
00000054
|
||||
19D07F54
|
||||
33A0FE54
|
||||
4D717D54
|
||||
6731FC54
|
||||
81027B54
|
||||
9AD2FA54
|
||||
B4A37954
|
||||
CE73F854
|
||||
0000005C
|
||||
CFF7FF5C
|
||||
67F3FF5C
|
||||
67D3FE5C
|
||||
6814005C
|
||||
0000005C
|
||||
19E0FF5C
|
||||
33D1FE5C
|
||||
4DB2FD5C
|
||||
67A3FC5C
|
||||
8184FB5C
|
||||
9B75FA5C
|
||||
B556F95C
|
||||
CF47F85C
|
||||
00000008
|
||||
000D0008
|
||||
0000000C
|
||||
6810010C
|
||||
00000060
|
||||
FFFD0060
|
||||
60
sync_rtl/comp_decomp/TB/xsim_run.tcl
Normal file
60
sync_rtl/comp_decomp/TB/xsim_run.tcl
Normal file
@@ -0,0 +1,60 @@
|
||||
# xsim_run.tcl - Vivado xsim compilation and simulation script for comp_decomp_sync
|
||||
#
|
||||
# Compiles comp_decomp_sync RTL + dependencies + testbench and runs simulation.
|
||||
# Run from the project root: ~/Dev/mlkem/
|
||||
#
|
||||
# Prerequisites:
|
||||
# source /opt/Xilinx/Vivado/2019.2/settings64.sh
|
||||
#
|
||||
# Usage examples:
|
||||
# # Step-by-step (from Tcl):
|
||||
# xsim -runall xsim_run.tcl
|
||||
#
|
||||
# # Or via Vivado batch mode:
|
||||
# vivado -mode batch -source xsim_run.tcl
|
||||
#
|
||||
# # Or manually:
|
||||
# xvlog -sv sync_rtl/common/pipeline_reg.v sync_rtl/comp_decomp/comp_decomp_sync.v sync_rtl/comp_decomp/TB/tb_comp_decomp_xsim.v
|
||||
# xelab tb_comp_decomp_xsim -s tb_comp_decomp_xsim
|
||||
# xsim tb_comp_decomp_xsim -R
|
||||
|
||||
# ================================================================
|
||||
# Configuration
|
||||
# ================================================================
|
||||
set RTL_DIR sync_rtl
|
||||
set DUT_DIR sync_rtl/comp_decomp
|
||||
set TB_DIR sync_rtl/comp_decomp/TB
|
||||
|
||||
# ================================================================
|
||||
# Step 1: Compile all source files (xvlog)
|
||||
# ================================================================
|
||||
puts "=== Compiling RTL sources for comp_decomp_sync ==="
|
||||
|
||||
# Common dependency (pipeline register)
|
||||
xvlog -sv -include_dirs . ${RTL_DIR}/common/pipeline_reg.v
|
||||
|
||||
# DUT (comp_decomp_sync) — uses `include "sync_rtl/common/defines.vh"
|
||||
xvlog -sv -include_dirs . ${DUT_DIR}/comp_decomp_sync.v
|
||||
|
||||
# ================================================================
|
||||
# Step 2: Compile testbench
|
||||
# ================================================================
|
||||
puts "=== Compiling testbench ==="
|
||||
|
||||
xvlog -sv ${TB_DIR}/tb_comp_decomp_xsim.v
|
||||
|
||||
# ================================================================
|
||||
# Step 3: Elaborate snapshot (xelab)
|
||||
# ================================================================
|
||||
puts "=== Elaborating snapshot ==="
|
||||
|
||||
xelab tb_comp_decomp_xsim -s tb_comp_decomp_xsim
|
||||
|
||||
# ================================================================
|
||||
# Step 4: Run simulation
|
||||
# ================================================================
|
||||
puts "=== Running comp_decomp_sync XSIM test ==="
|
||||
xsim tb_comp_decomp_xsim -R
|
||||
|
||||
puts ""
|
||||
puts "=== Simulation complete ==="
|
||||
Reference in New Issue
Block a user