diff --git a/sync_rtl/top/mlkem_top.v b/sync_rtl/top/mlkem_top.v
index 61463d1..d926c02 100644
--- a/sync_rtl/top/mlkem_top.v
+++ b/sync_rtl/top/mlkem_top.v
@@ -99,7 +99,26 @@ module mlkem_top #(
     localparam PA_AW = 12;                // bank_a addr width (4096)
     localparam PSE_AW = 11;               // bank_se addr width (2048)
     localparam PT_AW = 10;                // bank_t addr width (1024)
-    reg [11:0] bank_a  [0:(1<<PA_AW)-1];
+
+    // bank_a: A_hat. Reader = ST_M load (pm_a) + dbg. Writer = ST_A.
+    // Read port muxed by phase; sd_bram's internal rd_addr_r register is the
+    // 1-cycle read pipeline (replaces the explicit pm_a_rd reg). Write port is
+    // driven combinationally (sd_bram registers the write at posedge, matching
+    // the old reg-array nonblocking write timing).
+    wire [PA_AW-1:0] ba_rd_addr;
+    wire [11:0]      ba_rd_data;
+    wire             ba_we;
+    wire [PA_AW-1:0] ba_wa;
+    wire [11:0]      ba_wd;
+    sd_bram #(.W(12), .D(1<<PA_AW), .A(PA_AW)) u_bank_a (
+        .clk(clk), .rd_addr(ba_rd_addr), .rd_data(ba_rd_data),
+        .wr_en(ba_we), .wr_addr(ba_wa), .wr_data(ba_wd)
+    );
+    // ST_A write: commit snt_coeff to A_hat[a_slot] the cycle it is accepted.
+    assign ba_we = (st == ST_A) && a_busy && snt_vo && snt_ack;
+    assign ba_wa = (a_slot*256 + a_widx) & ((1<<PA_AW)-1);
+    assign ba_wd = snt_coeff;
+
     reg [11:0] bank_se [0:(1<<PSE_AW)-1];
     reg [11:0] bank_t  [0:(1<<PT_AW)-1];
 
@@ -111,10 +130,12 @@ module mlkem_top #(
     wire [13:0] dbg_a_addr  = dbg_slot_i*256 + dbg_idx_i;
     wire [13:0] dbg_se_addr = (dbg_slot_i - slot_s_rt)*256 + dbg_idx_i;
     wire [13:0] dbg_t_addr  = (dbg_slot_i - slot_t_rt)*256 + dbg_idx_i;
+    // bank_a read port: ST_M load drives pm_a_full; otherwise debug index.
+    assign ba_rd_addr = (st == ST_M) ? pm_a_full[PA_AW-1:0] : dbg_a_addr[PA_AW-1:0];
     always @(posedge clk) begin
         if (dbg_slot_i >= slot_t_rt)      dbg_coeff_r <= bank_t [dbg_t_addr[PT_AW-1:0]];
         else if (dbg_slot_i >= slot_s_rt) dbg_coeff_r <= bank_se[dbg_se_addr[PSE_AW-1:0]];
-        else                              dbg_coeff_r <= bank_a [dbg_a_addr[PA_AW-1:0]];
+        else                              dbg_coeff_r <= ba_rd_data;  // bank_a (registered in sd_bram)
     end
     assign dbg_coeff_o = dbg_coeff_r;
 
@@ -493,8 +514,8 @@ module mlkem_top #(
     // poly_mul one cycle later (pm_valid delayed 1 cyc), like ST_N.
     wire [13:0] pm_a_full = m_aslot*256 + m_ld[7:0];
     wire [13:0] pm_b_full = m_j*256 + m_ld[7:0];
-    reg  [11:0]  pm_a_rd, pm_b_rd;       // registered bank reads (sd_bram timing)
-    wire [11:0]  pm_a_in = pm_a_rd;
+    reg  [11:0]  pm_b_rd;                // registered bank_se read (sd_bram timing)
+    wire [11:0]  pm_a_in = ba_rd_data;   // bank_a sd_bram registered read
     wire [11:0]  pm_b_in = pm_b_rd;
 
     poly_mul_sync u_pmul (
@@ -579,7 +600,6 @@ module mlkem_top #(
             m_loading  <= 1'b0;
             m_pending  <= 1'b0;
             pm_valid   <= 1'b0;
-            pm_a_rd    <= 12'd0;
             pm_b_rd    <= 12'd0;
             m_acc_rd   <= 12'd0;
             e_poly     <= 3'd0;
@@ -647,9 +667,11 @@ module mlkem_top #(
                     a_busy    <= 1'b1;
                 end
 
-                // store each output coefficient only while busy (ignore stale last coeff from prior poly)
+                // store each output coefficient only while busy (ignore stale
+                // last coeff from prior poly). The bank_a write itself is the
+                // combinational ba_we/ba_wa/ba_wd assigns above; here we only
+                // advance the write index and (i,j) bookkeeping.
                 if (a_busy && snt_vo && snt_ack) begin
-                    bank_a[(a_slot*256 + a_widx) & ((1<<PA_AW)-1)] <= snt_coeff;
                     if (snt_last) begin
                         // finished this poly; advance (i,j) in row-major order
                         a_pair <= a_pair + 5'd1;
@@ -787,7 +809,8 @@ module mlkem_top #(
                         m_ld      <= 9'd0;
                         m_oidx    <= 8'd0;
                     end else begin
-                        pm_a_rd <= bank_a [pm_a_full[PA_AW-1:0]];
+                        // bank_a read is via sd_bram (ba_rd_addr=pm_a_full);
+                        // ba_rd_data lands next cycle == old pm_a_rd timing.
                         pm_b_rd <= bank_se[pm_b_full[PSE_AW-1:0]];
                         m_ld    <= m_ld + 9'd1;
                         pm_valid <= 1'b1;      // pair presented last cycle is valid