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Improve timing reports and register poly mul inputs

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FallenSigh
2026-07-08 00:50:20 +08:00
parent 372a90e601
commit ce998bb49a
7 changed files with 121 additions and 18 deletions
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41
sync_rtl/poly_mul/poly_mul_sync.v
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@@ -55,7 +55,11 @@ module poly_mul_sync (
reg [7:0] load_cnt; // 0..256 for loading 256 pairs
reg [6:0] comp_k; // 0..127, current base-case index
// Registered basecase_mul results
// Registered basecase_mul inputs/results
reg [11:0] bc_a0_reg, bc_a1_reg;
reg [11:0] bc_b0_reg, bc_b1_reg;
reg [11:0] bc_zeta_reg;
reg bc_valid_reg;
reg [11:0] c0_reg, c1_reg;
// Combinational read signals for COMP_CALC
@@ -73,19 +77,19 @@ module poly_mul_sync (
.zeta (zeta)
);
// Pipelined basecase multiply. One request is issued at a time; the
// output interface is unchanged for top-level consumers.
// Pipelined basecase multiply. One request is issued at a time; inputs are
// registered locally so comp_k does not directly drive the DSP input muxes.
wire [11:0] bc_c0, bc_c1;
wire bc_vo;
basecase_mul_pipe u_bc (
.clk (clk),
.rst_n(rst_n),
.valid_i(state == S_COMP_ISSUE),
.a0 (mem_a0),
.a1 (mem_a1),
.b0 (mem_b0),
.b1 (mem_b1),
.zeta(zeta),
.valid_i(bc_valid_reg),
.a0 (bc_a0_reg),
.a1 (bc_a1_reg),
.b0 (bc_b0_reg),
.b1 (bc_b1_reg),
.zeta(bc_zeta_reg),
.c0 (bc_c0),
.c1 (bc_c1),
.valid_o(bc_vo)
@@ -122,6 +126,12 @@ module poly_mul_sync (
state <= S_IDLE;
load_cnt <= 8'd0;
comp_k <= 7'd0;
bc_a0_reg <= 12'd0;
bc_a1_reg <= 12'd0;
bc_b0_reg <= 12'd0;
bc_b1_reg <= 12'd0;
bc_zeta_reg <= 12'd0;
bc_valid_reg <= 1'b0;
c0_reg <= 12'd0;
c1_reg <= 12'd0;
for (i = 0; i < 256; i = i + 1) begin
@@ -130,6 +140,7 @@ module poly_mul_sync (
end
end else begin
state <= next_state;
bc_valid_reg <= 1'b0;
// ---- LOAD phase ----
// First coefficient captured on IDLE → LOAD transition
@@ -147,6 +158,18 @@ module poly_mul_sync (
end
// ---- COMPUTE phase ----
// COMP_ISSUE: cut the comp_k -> memory mux -> basecase DSP path.
// bc_valid_reg pulses on the following cycle, while these regs hold
// stable inputs through the basecase pipeline launch.
if (state == S_COMP_ISSUE) begin
bc_a0_reg <= mem_a0;
bc_a1_reg <= mem_a1;
bc_b0_reg <= mem_b0;
bc_b1_reg <= mem_b1;
bc_zeta_reg <= zeta;
bc_valid_reg <= 1'b1;
end
// COMP_WAIT: capture pipelined basecase_mul results when ready.
if (state == S_COMP_WAIT && bc_vo) begin
c0_reg <= bc_c0;