feat(phase3): implement storage BRAMs and Compress/Decompress

Phase 3.1 + 3.3:
- sd_bram.v: simple dual-port RAM (behavioral, auto-infer to BRAM)
- s_bram.v: single-port RAM (rd_en/wr_en, write priority)
- comp_decomp_sync.v: streaming compress/decompress with round-half-up

Verified: storage 5/5, comp_decomp 60/60 all PASS

test_framework/modules/storage/test_plan.json

@@ -0,0 +1,17 @@
+{
+  "module": "storage",
+  "rtl_top": "sync_rtl/storage/sd_bram.v",
+  "rtl_deps": ["sync_rtl/storage/s_bram.v"],
+  "tb_cpp": "sync_rtl/storage/TB/tb_storage.cpp",
+  "simulator": "verilator",
+  "timeout_s": 30,
+  "cases": [
+    {
+      "id": "rw_test",
+      "description": "Write-read test for sd_bram (s_bram compiled as dep)",
+      "params": {},
+      "num_vectors": 5,
+      "tolerance": "bit_exact"
+    }
+  ]
+}