feat(phase3): implement storage BRAMs and Compress/Decompress

Phase 3.1 + 3.3:
- sd_bram.v: simple dual-port RAM (behavioral, auto-infer to BRAM)
- s_bram.v: single-port RAM (rd_en/wr_en, write priority)
- comp_decomp_sync.v: streaming compress/decompress with round-half-up

Verified: storage 5/5, comp_decomp 60/60 all PASS

test_framework/modules/storage/gen_vectors.py

@@ -0,0 +1,67 @@
+"""gen_vectors.py - Test vector generator for storage (sd_bram) module.
+
+Generates (addr, data) write pairs and expected read-back values.
+Address space: 0..63 (6-bit) | Data width: 48-bit.
+"""
+
+import os
+import sys
+
+sys.path.insert(0, os.path.join(os.path.dirname(__file__), '..', '..', 'lib'))
+
+from vector_gen import VectorGenerator
+
+
+class StorageVectorGenerator(VectorGenerator):
+    """Generates write/read test vectors for sd_bram behavioral RAM."""
+
+    def generate_one(self, params: dict) -> dict:
+        """Generate a single (addr, data) write pair.
+
+        Uses sequential addresses 0..N-1 and deterministic 48-bit data
+        patterns for reproducible testing.
+
+        Args:
+            params: Unused for storage basic case.
+
+        Returns:
+            dict with 'input' and 'expected' keys.
+        """
+        # Sequential address assignment during generation
+        # addr is determined by position; data is a deterministic pattern
+        # The actual index is handled in write_hex_file for sequential addresses
+        return {
+            'data': 0  # placeholder — filled in write_hex_file by index
+        }
+
+    def write_hex_file(self, vectors: list[dict], filepath: str) -> None:
+        """Write input vectors as "AA DDDDDDDDDDDD" hex lines.
+
+        Uses sequential addresses 0..N-1 and deterministic 48-bit data:
+        data = (addr * 0x100000000001 + 0xDEADBEEFCAFE) & 0xFFFF_FFFF_FFFF
+
+        Args:
+            vectors: List of vector dicts from generate_one().
+            filepath: Path to write the hex file.
+        """
+        os.makedirs(os.path.dirname(filepath), exist_ok=True)
+        with open(filepath, 'w') as f:
+            for i in range(len(vectors)):
+                addr = i
+                # Deterministic 48-bit pattern: spreads bits across the word
+                data = ((addr + 1) * 0x100000000001 + 0xDEADBEEFCAFE) & 0xFFFFFFFFFFFF
+                f.write(f'{addr:02X} {data:012X}\n')
+
+    def write_expected_file(self, vectors: list[dict], filepath: str) -> None:
+        """Write expected read-back values (same patterns as written).
+
+        Args:
+            vectors: List of vector dicts from generate_one().
+            filepath: Path to write the expected hex file.
+        """
+        os.makedirs(os.path.dirname(filepath), exist_ok=True)
+        with open(filepath, 'w') as f:
+            for i in range(len(vectors)):
+                addr = i
+                data = ((addr + 1) * 0x100000000001 + 0xDEADBEEFCAFE) & 0xFFFFFFFFFFFF
+                f.write(f'{data:012X}\n')

test_framework/modules/storage/test_plan.json

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+{
+  "module": "storage",
+  "rtl_top": "sync_rtl/storage/sd_bram.v",
+  "rtl_deps": ["sync_rtl/storage/s_bram.v"],
+  "tb_cpp": "sync_rtl/storage/TB/tb_storage.cpp",
+  "simulator": "verilator",
+  "timeout_s": 30,
+  "cases": [
+    {
+      "id": "rw_test",
+      "description": "Write-read test for sd_bram (s_bram compiled as dep)",
+      "params": {},
+      "num_vectors": 5,
+      "tolerance": "bit_exact"
+    }
+  ]
+}