feat(phase3): implement storage BRAMs and Compress/Decompress

Phase 3.1 + 3.3:
- sd_bram.v: simple dual-port RAM (behavioral, auto-infer to BRAM)
- s_bram.v: single-port RAM (rd_en/wr_en, write priority)
- comp_decomp_sync.v: streaming compress/decompress with round-half-up

Verified: storage 5/5, comp_decomp 60/60 all PASS

test_framework/modules/comp_decomp/test_plan.json

@@ -0,0 +1,38 @@
+{
+  "module": "comp_decomp",
+  "rtl_top": "sync_rtl/comp_decomp/comp_decomp_sync.v",
+  "rtl_deps": ["sync_rtl/common/pipeline_reg.v"],
+  "tb_cpp": "sync_rtl/comp_decomp/TB/tb_comp_decomp.cpp",
+  "simulator": "verilator",
+  "timeout_s": 30,
+  "cases": [
+    {
+      "id": "compress_du10",
+      "description": "Compress with du=10 (ML-KEM-512/768)",
+      "params": {"mode": "compress", "d": 10},
+      "num_vectors": 20,
+      "tolerance": "bit_exact"
+    },
+    {
+      "id": "compress_dv4",
+      "description": "Compress with dv=4 (ML-KEM-512/768)",
+      "params": {"mode": "compress", "d": 4},
+      "num_vectors": 20,
+      "tolerance": "bit_exact"
+    },
+    {
+      "id": "decompress_du10",
+      "description": "Decompress with du=10",
+      "params": {"mode": "decompress", "d": 10},
+      "num_vectors": 10,
+      "tolerance": "bit_exact"
+    },
+    {
+      "id": "decompress_dv4",
+      "description": "Decompress with dv=4",
+      "params": {"mode": "decompress", "d": 4},
+      "num_vectors": 10,
+      "tolerance": "bit_exact"
+    }
+  ]
+}