feat(phase3): implement storage BRAMs and Compress/Decompress

Phase 3.1 + 3.3:
- sd_bram.v: simple dual-port RAM (behavioral, auto-infer to BRAM)
- s_bram.v: single-port RAM (rd_en/wr_en, write priority)
- comp_decomp_sync.v: streaming compress/decompress with round-half-up

Verified: storage 5/5, comp_decomp 60/60 all PASS

sync_rtl/storage/sd_bram.v

@@ -0,0 +1,32 @@
+// sd_bram.v - Simple dual-port behavioral RAM (1 read + 1 write port)
+//
+// Vivado auto-infers this as BRAM when W >= 12 and D >= 64.
+// Read:  rd_addr sampled at posedge → rd_addr_r → rd_data = mem[rd_addr_r]
+// Write: wr_data written to mem[wr_addr] at posedge when wr_en=1
+// No valid/ready handshake — pure combinational-read / registered-write memory.
+
+module sd_bram #(
+    parameter W = 48,
+    parameter D = 64,
+    parameter A = 6
+) (
+    input  wire          clk,
+    input  wire [A-1:0]  rd_addr,
+    output wire [W-1:0]  rd_data,
+    input  wire          wr_en,
+    input  wire [A-1:0]  wr_addr,
+    input  wire [W-1:0]  wr_data
+);
+
+    reg [W-1:0] mem [0:D-1];
+    reg [A-1:0] rd_addr_r;
+
+    always @(posedge clk) begin
+        rd_addr_r <= rd_addr;
+        if (wr_en)
+            mem[wr_addr] <= wr_data;
+    end
+
+    assign rd_data = mem[rd_addr_r];
+
+endmodule