feat(phase3): implement storage BRAMs and Compress/Decompress

Phase 3.1 + 3.3:
- sd_bram.v: simple dual-port RAM (behavioral, auto-infer to BRAM)
- s_bram.v: single-port RAM (rd_en/wr_en, write priority)
- comp_decomp_sync.v: streaming compress/decompress with round-half-up

Verified: storage 5/5, comp_decomp 60/60 all PASS

sync_rtl/comp_decomp/TB/tb_comp_decomp.cpp

@@ -0,0 +1,125 @@
+// tb_comp_decomp.cpp - Verilator C++ testbench for comp_decomp_sync
+//
+// Reads test vectors from a hex file specified by +VECTOR_FILE= plusarg.
+// Each line: "MODE D COEFF" (e.g. "C A 3FF" for compress d=10 coeff=0x3FF).
+// MODE: 'C' for compress, 'D' for decompress.
+// Drives the DUT, waits for valid_o, writes "RESULT: COEFF" to stdout.
+//
+// Clock: 10 ns period. Reset: 2 cycles low. Timeout: 100,000 cycles.
+
+#include <iostream>
+#include <fstream>
+#include <string>
+#include <sstream>
+#include <cstdlib>
+#include "Vcomp_decomp_sync.h"
+#include "verilated.h"
+
+#define CLK_PERIOD_NS    10.0
+#define TIMEOUT_CYCLES   100000
+
+static vluint64_t main_time = 0;
+
+double sc_time_stamp() {
+    return main_time;
+}
+
+int main(int argc, char** argv) {
+    Verilated::commandArgs(argc, argv);
+
+    // Parse +VECTOR_FILE= plusarg
+    const char* vector_file = NULL;
+    for (int i = 1; i < argc; i++) {
+        std::string arg(argv[i]);
+        if (arg.rfind("+VECTOR_FILE=", 0) == 0) {
+            vector_file = argv[i] + 13; // skip "+VECTOR_FILE="
+        }
+    }
+
+    if (!vector_file) {
+        std::cerr << "ERROR: +VECTOR_FILE= not specified" << std::endl;
+        return 1;
+    }
+
+    std::ifstream infile(vector_file);
+    if (!infile.is_open()) {
+        std::cerr << "ERROR: Cannot open vector file: " << vector_file << std::endl;
+        return 1;
+    }
+
+    // Instantiate DUT
+    Vcomp_decomp_sync* dut = new Vcomp_decomp_sync;
+
+    // Initialize
+    dut->clk      = 0;
+    dut->rst_n    = 0;
+    dut->coeff_in = 0;
+    dut->d        = 0;
+    dut->mode     = 0;
+    dut->valid_i  = 0;
+    dut->ready_i  = 0;
+
+    // Reset: 2 cycles low
+    for (int i = 0; i < 4; i++) {
+        dut->clk = !dut->clk;
+        main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
+        dut->eval();
+        dut->clk = !dut->clk;
+        main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
+        dut->eval();
+    }
+    dut->rst_n = 1;
+
+    // Always ready to receive results
+    dut->ready_i = 1;
+
+    std::string line;
+    vluint64_t cycle = 0;
+
+    while (std::getline(infile, line)) {
+        // Skip empty lines and comments
+        if (line.empty() || line[0] == '#') continue;
+
+        // Parse: MODE D COEFF
+        std::istringstream iss(line);
+        char mode_char;
+        unsigned int d_val, coeff_val;
+        if (!(iss >> mode_char >> std::hex >> d_val >> coeff_val)) continue;
+
+        if (mode_char == 'C')
+            dut->mode = 0;
+        else if (mode_char == 'D')
+            dut->mode = 1;
+        else
+            continue;
+
+        dut->d        = d_val & 0x1F;
+        dut->coeff_in = coeff_val & 0xFFF;
+        dut->valid_i  = 1;
+
+        // posedge: DUT samples valid_i, pipeline_reg captures data
+        dut->clk = !dut->clk;
+        main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
+        dut->eval();
+        dut->clk = !dut->clk;
+        main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
+        dut->eval();
+        cycle++;
+        dut->valid_i = 0;
+
+        // posedge: pipeline_reg sends result out (valid_o=1)
+        dut->clk = !dut->clk;
+        main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
+        dut->eval();
+        dut->clk = !dut->clk;
+        main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
+        dut->eval();
+        cycle++;
+
+        printf("RESULT: %03X\n", dut->coeff_out & 0xFFF);
+    }
+
+    infile.close();
+    delete dut;
+    return 0;
+}