From a0bd07bdf89fe1cf8243f8f8fd1f9061668d9bc1 Mon Sep 17 00:00:00 2001 From: FallenSigh Date: Wed, 8 Jul 2026 00:57:05 +0800 Subject: [PATCH] Reduce NTT butterfly dispatch latency --- sync_rtl/ntt/ntt_core.v | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/sync_rtl/ntt/ntt_core.v b/sync_rtl/ntt/ntt_core.v index 35dfe0f..0b77159 100644 --- a/sync_rtl/ntt/ntt_core.v +++ b/sync_rtl/ntt/ntt_core.v @@ -2,7 +2,7 @@ // // Uses 256 individual 12-bit registers and a deeply pipelined butterfly path. // The arithmetic hot path is split into: -// address -> operand/zeta register -> pipelined Barrett butterfly -> writeback +// address/operand/zeta register -> pipelined Barrett butterfly -> writeback // In inverse mode, final x3303 output scaling also uses a pipelined Barrett // multiplier so the output path does not reintroduce a combinational reducer. @@ -96,7 +96,7 @@ module ntt_core ( case (state) S_IDLE: if (valid_i) next_state = S_LOAD; S_LOAD: if (load_cnt >= 8'd255 && valid_i) next_state = S_CMP_A; - S_CMP_A: next_state = bf_done ? S_OUT_PREP : S_CMP_B; + S_CMP_A: next_state = bf_done ? S_OUT_PREP : S_CMP_ISSUE; S_CMP_B: next_state = bf_done ? S_OUT_PREP : S_CMP_ISSUE; S_CMP_ISSUE: next_state = S_CMP_WAIT; S_CMP_WAIT: if (bf_valid) next_state = S_CMP_WB; @@ -169,12 +169,9 @@ module ntt_core ( load_cnt <= load_cnt + 8'd1; end - if (state == S_CMP_A) begin + if (state == S_CMP_A && !bf_done) begin r_wa <= j; r_wb <= j + layer_len; - end - - if (state == S_CMP_B) begin r_a <= cr[j]; r_b <= cr[j + layer_len]; r_zeta <= zeta;