From 92f851da847552670d817640eda4ee88fa3385d6 Mon Sep 17 00:00:00 2001
From: FallenSigh <fallensigh@gmail.com>
Date: Thu, 25 Jun 2026 22:23:15 +0800
Subject: [PATCH] chore: record journal

---
 .trellis/workspace/FallenSigh/index.md     |  5 ++--
 .trellis/workspace/FallenSigh/journal-1.md | 33 ++++++++++++++++++++++
 2 files changed, 36 insertions(+), 2 deletions(-)

diff --git a/.trellis/workspace/FallenSigh/index.md b/.trellis/workspace/FallenSigh/index.md
index dd40f1a..2f02d2c 100644
--- a/.trellis/workspace/FallenSigh/index.md
+++ b/.trellis/workspace/FallenSigh/index.md
@@ -8,7 +8,7 @@
 
 <!-- @@@auto:current-status -->
 - **Active File**: `journal-1.md`
-- **Total Sessions**: 1
+- **Total Sessions**: 2
 - **Last Active**: 2026-06-25
 <!-- @@@/auto:current-status -->
 
@@ -19,7 +19,7 @@
 <!-- @@@auto:active-documents -->
 | File | Lines | Status |
 |------|-------|--------|
-| `journal-1.md` | ~43 | Active |
+| `journal-1.md` | ~76 | Active |
 <!-- @@@/auto:active-documents -->
 
 ---
@@ -29,6 +29,7 @@
 <!-- @@@auto:session-history -->
 | # | Date | Title | Commits | Branch |
 |---|------|-------|---------|--------|
+| 2 | 2026-06-25 | Fix 7 failing Vivado XSIM testbenches | `f5365c9` | `main` |
 | 1 | 2026-06-25 | Add Vivado XSIM Verilog testbenches for all 10 sync modules | `d4c3fc8`, `52c625b`, `79653ac`, `db0a559` | `main` |
 <!-- @@@/auto:session-history -->
 
diff --git a/.trellis/workspace/FallenSigh/journal-1.md b/.trellis/workspace/FallenSigh/journal-1.md
index 600a8d4..1aba56c 100644
--- a/.trellis/workspace/FallenSigh/journal-1.md
+++ b/.trellis/workspace/FallenSigh/journal-1.md
@@ -41,3 +41,36 @@ Created file-based vector Verilog testbenches () for all 10 top-level sync modul
 ### Next Steps
 
 - None - task complete
+
+
+## Session 2: Fix 7 failing Vivado XSIM testbenches
+
+**Date**: 2026-06-25
+**Task**: Fix 7 failing Vivado XSIM testbenches
+**Branch**: `main`
+
+### Summary
+
+Fixed 7 testbench failures on Vivado 2019.2: (1) sha3_top.v declaration ordering, (2) TCL variable paths + --relax flag, (3) Verilog part-select changed to +: operator, (4) BRAM read latency timing, (5) comp_decomp d=12 edge case, (6) sample_ntt TB timing bug (DUT Keccak pipeline drain). All 10 modules now pass.
+
+### Main Changes
+
+(Add details)
+
+### Git Commits
+
+| Hash | Message |
+|------|---------|
+| `f5365c9` | (see git log) |
+
+### Testing
+
+- [OK] (Add test results)
+
+### Status
+
+[OK] **Completed**
+
+### Next Steps
+
+- None - task complete