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Fix ML-KEM arithmetic timing paths

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FallenSigh
2026-07-07 18:28:47 +08:00
parent 2fb1cd67e3
commit 8c3f4317f5
12 changed files with 5030 additions and 63 deletions
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34
sync_rtl/poly_mul/poly_mul_sync.v
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@@ -4,7 +4,7 @@
// 256-coefficient NTT-domain polynomials.
//
// Operation flow:
// IDLE → LOAD (256× A+B pairs) → COMP_CALC (read+compute, 1 cycle)
// IDLE → LOAD (256× A+B pairs) → COMP_ISSUE → COMP_WAIT
// → COMP_C0 (output c0) → COMP_C1 (output c1) → DONE → IDLE
//
// The LOAD phase accepts both A and B coefficients simultaneously
@@ -39,10 +39,11 @@ module poly_mul_sync (
// State definitions
localparam S_IDLE = 3'd0;
localparam S_LOAD = 3'd1;
localparam S_COMP_CALC = 3'd2;
localparam S_COMP_C0 = 3'd3;
localparam S_COMP_C1 = 3'd4;
localparam S_DONE = 3'd5;
localparam S_COMP_ISSUE = 3'd2;
localparam S_COMP_WAIT = 3'd3;
localparam S_COMP_C0 = 3'd4;
localparam S_COMP_C1 = 3'd5;
localparam S_DONE = 3'd6;
reg [2:0] state, next_state;
@@ -72,16 +73,22 @@ module poly_mul_sync (
.zeta (zeta)
);
// Basecase multiply
// Pipelined basecase multiply. One request is issued at a time; the
// output interface is unchanged for top-level consumers.
wire [11:0] bc_c0, bc_c1;
basecase_mul u_bc (
wire bc_vo;
basecase_mul_pipe u_bc (
.clk (clk),
.rst_n(rst_n),
.valid_i(state == S_COMP_ISSUE),
.a0 (mem_a0),
.a1 (mem_a1),
.b0 (mem_b0),
.b1 (mem_b1),
.zeta(zeta),
.c0 (bc_c0),
.c1 (bc_c1)
.c1 (bc_c1),
.valid_o(bc_vo)
);
// Output interface
@@ -95,12 +102,13 @@ module poly_mul_sync (
case (state)
S_IDLE: if (valid_i && ready_o) next_state = S_LOAD;
S_LOAD: if (load_cnt >= 255 && valid_i && ready_o)
next_state = S_COMP_CALC;
S_COMP_CALC: next_state = S_COMP_C0;
next_state = S_COMP_ISSUE;
S_COMP_ISSUE: next_state = S_COMP_WAIT;
S_COMP_WAIT: if (bc_vo) next_state = S_COMP_C0;
S_COMP_C0: if (valid_o && ready_i) next_state = S_COMP_C1;
S_COMP_C1: if (valid_o && ready_i) begin
if (comp_k >= 127) next_state = S_DONE;
else next_state = S_COMP_CALC;
else next_state = S_COMP_ISSUE;
end
S_DONE: next_state = S_IDLE;
default: next_state = S_IDLE;
@@ -139,8 +147,8 @@ module poly_mul_sync (
end
// ---- COMPUTE phase ----
// COMP_CALC: capture basecase_mul results
if (state == S_COMP_CALC) begin
// COMP_WAIT: capture pipelined basecase_mul results when ready.
if (state == S_COMP_WAIT && bc_vo) begin
c0_reg <= bc_c0;
c1_reg <= bc_c1;
end