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Fix ML-KEM arithmetic timing paths

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FallenSigh
2026-07-07 18:28:47 +08:00
parent 2fb1cd67e3
commit 8c3f4317f5
12 changed files with 5030 additions and 63 deletions
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reports/timing_synth.rpt Normal file
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Tue Jul 7 15:28:57 2026
| Host : fedora running 64-bit unknown
| Command : report_timing_summary -file /home/fallensigh/Dev/mlkem/reports/timing_synth.rpt
| Design : mlkem_top
| Device : 7a200t-fbg676
| Speed File : -1 PRODUCTION 1.23 2018-06-13
-------------------------------------------------------------------------------------------------
Timing Summary Report
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : No
Borrow Time for Max Delay Exceptions : Yes
Merge Timing Exceptions : Yes
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
check_timing report
Table of Contents
-----------------
1. checking no_clock
2. checking constant_clock
3. checking pulse_width_clock
4. checking unconstrained_internal_endpoints
5. checking no_input_delay
6. checking no_output_delay
7. checking multiple_clock
8. checking generated_clocks
9. checking loops
10. checking partial_input_delay
11. checking partial_output_delay
12. checking latch_loops
1. checking no_clock
--------------------
There are 0 register/latch pins with no clock.
2. checking constant_clock
--------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock
-----------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints
--------------------------------------------
There are 0 pins that are not constrained for maximum delay.
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay
--------------------------
There are 629 input ports with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay
---------------------------
There are 2342 ports with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock
--------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks
----------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops
-----------------
There are 0 combinational loops in the design.
10. checking partial_input_delay
--------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay
---------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops
------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
-40.169 -37681.270 3108 45226 0.080 0.000 0 45226 9.020 0.000 0 23791
Timing constraints are not met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
sysclk {0.000 10.000} 20.000 50.000
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
sysclk -40.169 -37681.270 3108 45226 0.080 0.000 0 45226 9.020 0.000 0 23791
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
From Clock: sysclk
To Clock: sysclk
Setup : 3108 Failing Endpoints, Worst Slack -40.169ns, Total Violation -37681.271ns
Hold : 0 Failing Endpoints, Worst Slack 0.080ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 9.020ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (VIOLATED) : -40.169ns (required time - arrival time)
Source: st_reg[3]/C
(rising edge-triggered cell FDCE clocked by sysclk {rise@0.000ns fall@10.000ns period=20.000ns})
Destination: u_comp/u_pipe/data_r_reg[0]/D
(rising edge-triggered cell FDCE clocked by sysclk {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: sysclk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 20.000ns (sysclk rise@20.000ns - sysclk rise@0.000ns)
Data Path Delay: 60.018ns (logic 37.409ns (62.330%) route 22.609ns (37.670%))
Logic Levels: 115 (CARRY4=105 LUT1=1 LUT2=2 LUT3=2 LUT5=3 LUT6=2)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.106ns = ( 22.106 - 20.000 )
Source Clock Delay (SCD): 2.430ns
Clock Pessimism Removal (CPR): 0.178ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sysclk rise edge) 0.000 0.000 r
0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 clk
IBUF (Prop_ibuf_I_O) 0.950 0.950 r clk_IBUF_inst/O
net (fo=1, unplaced) 0.800 1.750 clk_IBUF
BUFG (Prop_bufg_I_O) 0.096 1.846 r clk_IBUF_BUFG_inst/O
net (fo=23790, unplaced) 0.584 2.430 clk_IBUF_BUFG
FDCE r st_reg[3]/C
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.456 2.886 f st_reg[3]/Q
net (fo=118, unplaced) 0.910 3.796 u_bank_a/snt_valid_reg[2]
LUT5 (Prop_lut5_I0_O) 0.295 4.091 r u_bank_a/valid_r_i_2/O
net (fo=211, unplaced) 0.567 4.658 u_bank_a_n_38
LUT3 (Prop_lut3_I1_O) 0.124 4.782 r data_r[11]_i_227/O
net (fo=2, unplaced) 0.460 5.242 cd_in_mux[7]
LUT2 (Prop_lut2_I1_O) 0.124 5.366 r data_r[11]_i_170/O
net (fo=1, unplaced) 0.000 5.366 data_r[11]_i_170_n_0
CARRY4 (Prop_carry4_S[1]_CO[3])
0.550 5.916 r data_r_reg[11]_i_135/CO[3]
net (fo=1, unplaced) 0.009 5.925 data_r_reg[11]_i_135_n_0
CARRY4 (Prop_carry4_CI_O[1])
0.348 6.273 r data_r_reg[11]_i_140/O[1]
net (fo=3, unplaced) 0.629 6.902 data_r_reg[11]_i_140_n_6
LUT3 (Prop_lut3_I0_O) 0.306 7.208 r data_r[11]_i_141/O
net (fo=2, unplaced) 0.460 7.668 data_r[11]_i_141_n_0
LUT5 (Prop_lut5_I4_O) 0.124 7.792 r data_r[11]_i_130/O
net (fo=2, unplaced) 0.460 8.252 data_r[11]_i_130_n_0
LUT6 (Prop_lut6_I0_O) 0.124 8.376 r data_r[11]_i_134/O
net (fo=1, unplaced) 0.000 8.376 data_r[11]_i_134_n_0
CARRY4 (Prop_carry4_S[0]_CO[3])
0.532 8.908 r data_r_reg[11]_i_101/CO[3]
net (fo=1, unplaced) 0.000 8.908 data_r_reg[11]_i_101_n_0
CARRY4 (Prop_carry4_CI_O[1])
0.348 9.256 r data_r_reg[11]_i_252/O[1]
net (fo=1, unplaced) 0.715 9.971 product[17]
CARRY4 (Prop_carry4_S[1]_CO[3])
0.854 10.825 r data_r_reg[11]_i_203/CO[3]
net (fo=1, unplaced) 0.000 10.825 data_r_reg[11]_i_203_n_0
CARRY4 (Prop_carry4_CI_O[3])
0.329 11.154 r data_r_reg[11]_i_321/O[3]
net (fo=1, unplaced) 0.618 11.772 dividend[23]
LUT2 (Prop_lut2_I1_O) 0.307 12.079 r data_r[11]_i_365/O
net (fo=1, unplaced) 0.000 12.079 data_r[11]_i_365_n_0
CARRY4 (Prop_carry4_S[0]_CO[2])
0.536 12.615 r data_r_reg[11]_i_351/CO[2]
net (fo=3, unplaced) 0.354 12.969 data_r_reg[11]_i_351_n_1
CARRY4 (Prop_carry4_CYINIT_CO[3])
0.766 13.735 r data_r_reg[11]_i_338/CO[3]
net (fo=3, unplaced) 0.838 14.573 data_r_reg[11]_i_338_n_0
CARRY4 (Prop_carry4_CYINIT_CO[2])
0.617 15.190 r data_r_reg[11]_i_334/CO[2]
net (fo=2, unplaced) 0.347 15.537 data_r_reg[11]_i_334_n_1
CARRY4 (Prop_carry4_CYINIT_CO[3])
0.766 16.303 r data_r_reg[11]_i_306/CO[3]
net (fo=23, unplaced) 0.981 17.284 data_r_reg[11]_i_306_n_0
LUT6 (Prop_lut6_I5_O) 0.124 17.408 r data_r[11]_i_311/O
net (fo=1, unplaced) 0.639 18.047 data_r[11]_i_311_n_0
CARRY4 (Prop_carry4_DI[1]_CO[3])
0.507 18.554 r data_r_reg[11]_i_286/CO[3]
net (fo=1, unplaced) 0.000 18.554 data_r_reg[11]_i_286_n_0
CARRY4 (Prop_carry4_CI_CO[1])
0.178 18.732 r data_r_reg[11]_i_285/CO[1]
net (fo=20, unplaced) 0.585 19.317 data_r_reg[11]_i_285_n_2
CARRY4 (Prop_carry4_CYINIT_CO[3])
0.788 20.105 r data_r_reg[11]_i_316/CO[3]
net (fo=1, unplaced) 0.009 20.114 data_r_reg[11]_i_316_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 20.228 r data_r_reg[11]_i_289/CO[3]
net (fo=1, unplaced) 0.000 20.228 data_r_reg[11]_i_289_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 20.342 r data_r_reg[11]_i_261/CO[3]
net (fo=1, unplaced) 0.000 20.342 data_r_reg[11]_i_261_n_0
CARRY4 (Prop_carry4_CI_CO[1])
0.178 20.520 r data_r_reg[11]_i_260/CO[1]
net (fo=20, unplaced) 0.585 21.105 data_r_reg[11]_i_260_n_2
CARRY4 (Prop_carry4_CYINIT_CO[3])
0.788 21.893 r data_r_reg[11]_i_294/CO[3]
net (fo=1, unplaced) 0.009 21.902 data_r_reg[11]_i_294_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 22.016 r data_r_reg[11]_i_264/CO[3]
net (fo=1, unplaced) 0.000 22.016 data_r_reg[11]_i_264_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 22.130 r data_r_reg[11]_i_236/CO[3]
net (fo=1, unplaced) 0.000 22.130 data_r_reg[11]_i_236_n_0
CARRY4 (Prop_carry4_CI_CO[1])
0.178 22.308 r data_r_reg[11]_i_235/CO[1]
net (fo=20, unplaced) 0.585 22.893 data_r_reg[11]_i_235_n_2
CARRY4 (Prop_carry4_CYINIT_CO[3])
0.788 23.681 r data_r_reg[11]_i_269/CO[3]
net (fo=1, unplaced) 0.009 23.690 data_r_reg[11]_i_269_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 23.804 r data_r_reg[11]_i_239/CO[3]
net (fo=1, unplaced) 0.000 23.804 data_r_reg[11]_i_239_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 23.918 r data_r_reg[11]_i_190/CO[3]
net (fo=1, unplaced) 0.000 23.918 data_r_reg[11]_i_190_n_0
CARRY4 (Prop_carry4_CI_CO[1])
0.178 24.096 r data_r_reg[11]_i_189/CO[1]
net (fo=20, unplaced) 0.585 24.681 data_r_reg[11]_i_189_n_2
CARRY4 (Prop_carry4_CYINIT_CO[3])
0.788 25.469 r data_r_reg[11]_i_244/CO[3]
net (fo=1, unplaced) 0.009 25.478 data_r_reg[11]_i_244_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 25.592 r data_r_reg[11]_i_193/CO[3]
net (fo=1, unplaced) 0.000 25.592 data_r_reg[11]_i_193_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 25.706 r data_r_reg[11]_i_144/CO[3]
net (fo=1, unplaced) 0.000 25.706 data_r_reg[11]_i_144_n_0
CARRY4 (Prop_carry4_CI_CO[1])
0.178 25.884 r data_r_reg[11]_i_143/CO[1]
net (fo=20, unplaced) 0.585 26.469 data_r_reg[11]_i_143_n_2
CARRY4 (Prop_carry4_CYINIT_CO[3])
0.788 27.257 r data_r_reg[11]_i_198/CO[3]
net (fo=1, unplaced) 0.009 27.266 data_r_reg[11]_i_198_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 27.380 r data_r_reg[11]_i_147/CO[3]
net (fo=1, unplaced) 0.000 27.380 data_r_reg[11]_i_147_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 27.494 r data_r_reg[11]_i_111/CO[3]
net (fo=1, unplaced) 0.000 27.494 data_r_reg[11]_i_111_n_0
CARRY4 (Prop_carry4_CI_CO[1])
0.178 27.672 r data_r_reg[11]_i_110/CO[1]
net (fo=20, unplaced) 0.585 28.257 data_r_reg[11]_i_110_n_2
CARRY4 (Prop_carry4_CYINIT_CO[3])
0.788 29.045 r data_r_reg[11]_i_152/CO[3]
net (fo=1, unplaced) 0.009 29.054 data_r_reg[11]_i_152_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 29.168 r data_r_reg[11]_i_114/CO[3]
net (fo=1, unplaced) 0.000 29.168 data_r_reg[11]_i_114_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 29.282 r data_r_reg[11]_i_85/CO[3]
net (fo=1, unplaced) 0.000 29.282 data_r_reg[11]_i_85_n_0
CARRY4 (Prop_carry4_CI_CO[1])
0.178 29.460 r data_r_reg[11]_i_84/CO[1]
net (fo=20, unplaced) 0.585 30.045 data_r_reg[11]_i_84_n_2
CARRY4 (Prop_carry4_CYINIT_CO[3])
0.788 30.833 r data_r_reg[11]_i_119/CO[3]
net (fo=1, unplaced) 0.009 30.842 data_r_reg[11]_i_119_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 30.956 r data_r_reg[11]_i_88/CO[3]
net (fo=1, unplaced) 0.000 30.956 data_r_reg[11]_i_88_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 31.070 r data_r_reg[11]_i_64/CO[3]
net (fo=1, unplaced) 0.000 31.070 data_r_reg[11]_i_64_n_0
CARRY4 (Prop_carry4_CI_CO[1])
0.178 31.248 r data_r_reg[11]_i_63/CO[1]
net (fo=20, unplaced) 0.585 31.833 data_r_reg[11]_i_63_n_2
CARRY4 (Prop_carry4_CYINIT_CO[3])
0.788 32.621 r data_r_reg[11]_i_93/CO[3]
net (fo=1, unplaced) 0.009 32.630 data_r_reg[11]_i_93_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 32.744 r data_r_reg[11]_i_67/CO[3]
net (fo=1, unplaced) 0.000 32.744 data_r_reg[11]_i_67_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 32.858 r data_r_reg[11]_i_44/CO[3]
net (fo=1, unplaced) 0.000 32.858 data_r_reg[11]_i_44_n_0
CARRY4 (Prop_carry4_CI_CO[1])
0.178 33.036 r data_r_reg[11]_i_43/CO[1]
net (fo=20, unplaced) 0.585 33.621 data_r_reg[11]_i_43_n_2
CARRY4 (Prop_carry4_CYINIT_CO[3])
0.788 34.409 r data_r_reg[11]_i_72/CO[3]
net (fo=1, unplaced) 0.009 34.418 data_r_reg[11]_i_72_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 34.532 r data_r_reg[11]_i_47/CO[3]
net (fo=1, unplaced) 0.000 34.532 data_r_reg[11]_i_47_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 34.646 r data_r_reg[11]_i_28/CO[3]
net (fo=1, unplaced) 0.000 34.646 data_r_reg[11]_i_28_n_0
CARRY4 (Prop_carry4_CI_CO[1])
0.178 34.824 r data_r_reg[11]_i_27/CO[1]
net (fo=20, unplaced) 0.585 35.409 data_r_reg[11]_i_27_n_2
CARRY4 (Prop_carry4_CYINIT_CO[3])
0.788 36.197 r data_r_reg[11]_i_52/CO[3]
net (fo=1, unplaced) 0.009 36.206 data_r_reg[11]_i_52_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 36.320 r data_r_reg[11]_i_31/CO[3]
net (fo=1, unplaced) 0.000 36.320 data_r_reg[11]_i_31_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 36.434 r data_r_reg[11]_i_16/CO[3]
net (fo=1, unplaced) 0.000 36.434 data_r_reg[11]_i_16_n_0
CARRY4 (Prop_carry4_CI_CO[1])
0.178 36.612 r data_r_reg[11]_i_15/CO[1]
net (fo=20, unplaced) 0.585 37.197 data_r_reg[11]_i_15_n_2
CARRY4 (Prop_carry4_CYINIT_CO[3])
0.788 37.985 r data_r_reg[11]_i_37/CO[3]
net (fo=1, unplaced) 0.009 37.994 data_r_reg[11]_i_37_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 38.108 r data_r_reg[11]_i_22/CO[3]
net (fo=1, unplaced) 0.000 38.108 data_r_reg[11]_i_22_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 38.222 r data_r_reg[11]_i_14/CO[3]
net (fo=1, unplaced) 0.000 38.222 data_r_reg[11]_i_14_n_0
CARRY4 (Prop_carry4_CI_CO[1])
0.178 38.400 r data_r_reg[11]_i_6/CO[1]
net (fo=23, unplaced) 0.588 38.988 div_result[11]
CARRY4 (Prop_carry4_CYINIT_CO[3])
0.788 39.776 r data_r_reg[10]_i_11/CO[3]
net (fo=1, unplaced) 0.009 39.785 data_r_reg[10]_i_11_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 39.899 r data_r_reg[10]_i_6/CO[3]
net (fo=1, unplaced) 0.000 39.899 data_r_reg[10]_i_6_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 40.013 r data_r_reg[10]_i_3/CO[3]
net (fo=1, unplaced) 0.000 40.013 data_r_reg[10]_i_3_n_0
CARRY4 (Prop_carry4_CI_CO[1])
0.178 40.191 r data_r_reg[10]_i_2/CO[1]
net (fo=23, unplaced) 0.588 40.779 div_result[10]
CARRY4 (Prop_carry4_CYINIT_CO[3])
0.788 41.567 r data_r_reg[9]_i_16/CO[3]
net (fo=1, unplaced) 0.009 41.576 data_r_reg[9]_i_16_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 41.690 r data_r_reg[9]_i_11/CO[3]
net (fo=1, unplaced) 0.000 41.690 data_r_reg[9]_i_11_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 41.804 r data_r_reg[9]_i_4/CO[3]
net (fo=1, unplaced) 0.000 41.804 data_r_reg[9]_i_4_n_0
CARRY4 (Prop_carry4_CI_CO[1])
0.178 41.982 r data_r_reg[9]_i_2/CO[1]
net (fo=23, unplaced) 0.588 42.570 div_result[9]
CARRY4 (Prop_carry4_CYINIT_CO[3])
0.788 43.358 r data_r_reg[8]_i_11/CO[3]
net (fo=1, unplaced) 0.009 43.367 data_r_reg[8]_i_11_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 43.481 r data_r_reg[8]_i_6/CO[3]
net (fo=1, unplaced) 0.000 43.481 data_r_reg[8]_i_6_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 43.595 r data_r_reg[8]_i_3/CO[3]
net (fo=1, unplaced) 0.000 43.595 data_r_reg[8]_i_3_n_0
CARRY4 (Prop_carry4_CI_CO[1])
0.178 43.773 r data_r_reg[8]_i_2/CO[1]
net (fo=23, unplaced) 0.588 44.361 div_result[8]
CARRY4 (Prop_carry4_CYINIT_CO[3])
0.788 45.149 r data_r_reg[7]_i_21/CO[3]
net (fo=1, unplaced) 0.009 45.158 data_r_reg[7]_i_21_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 45.272 r data_r_reg[7]_i_16/CO[3]
net (fo=1, unplaced) 0.000 45.272 data_r_reg[7]_i_16_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 45.386 r data_r_reg[7]_i_13/CO[3]
net (fo=1, unplaced) 0.000 45.386 data_r_reg[7]_i_13_n_0
CARRY4 (Prop_carry4_CI_CO[1])
0.178 45.564 r data_r_reg[7]_i_4/CO[1]
net (fo=23, unplaced) 0.588 46.152 div_result[7]
CARRY4 (Prop_carry4_CYINIT_CO[3])
0.788 46.940 r data_r_reg[6]_i_11/CO[3]
net (fo=1, unplaced) 0.009 46.949 data_r_reg[6]_i_11_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 47.063 r data_r_reg[6]_i_6/CO[3]
net (fo=1, unplaced) 0.000 47.063 data_r_reg[6]_i_6_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 47.177 r data_r_reg[6]_i_3/CO[3]
net (fo=1, unplaced) 0.000 47.177 data_r_reg[6]_i_3_n_0
CARRY4 (Prop_carry4_CI_CO[1])
0.178 47.355 r data_r_reg[6]_i_2/CO[1]
net (fo=23, unplaced) 0.588 47.943 div_result[6]
CARRY4 (Prop_carry4_CYINIT_CO[3])
0.788 48.731 r data_r_reg[5]_i_11/CO[3]
net (fo=1, unplaced) 0.009 48.740 data_r_reg[5]_i_11_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 48.854 r data_r_reg[5]_i_6/CO[3]
net (fo=1, unplaced) 0.000 48.854 data_r_reg[5]_i_6_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 48.968 r data_r_reg[5]_i_3/CO[3]
net (fo=1, unplaced) 0.000 48.968 data_r_reg[5]_i_3_n_0
CARRY4 (Prop_carry4_CI_CO[1])
0.178 49.146 r data_r_reg[5]_i_2/CO[1]
net (fo=23, unplaced) 0.588 49.734 div_result[5]
CARRY4 (Prop_carry4_CYINIT_CO[3])
0.788 50.522 r data_r_reg[4]_i_11/CO[3]
net (fo=1, unplaced) 0.009 50.531 data_r_reg[4]_i_11_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 50.645 r data_r_reg[4]_i_6/CO[3]
net (fo=1, unplaced) 0.000 50.645 data_r_reg[4]_i_6_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 50.759 r data_r_reg[4]_i_3/CO[3]
net (fo=1, unplaced) 0.000 50.759 data_r_reg[4]_i_3_n_0
CARRY4 (Prop_carry4_CI_CO[1])
0.178 50.937 r data_r_reg[4]_i_2/CO[1]
net (fo=23, unplaced) 0.588 51.525 div_result[4]
CARRY4 (Prop_carry4_CYINIT_CO[3])
0.788 52.313 r data_r_reg[3]_i_20/CO[3]
net (fo=1, unplaced) 0.009 52.322 data_r_reg[3]_i_20_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 52.436 r data_r_reg[3]_i_15/CO[3]
net (fo=1, unplaced) 0.000 52.436 data_r_reg[3]_i_15_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 52.550 r data_r_reg[3]_i_12/CO[3]
net (fo=1, unplaced) 0.000 52.550 data_r_reg[3]_i_12_n_0
CARRY4 (Prop_carry4_CI_CO[1])
0.178 52.728 r data_r_reg[3]_i_4/CO[1]
net (fo=23, unplaced) 0.588 53.316 div_result[3]
CARRY4 (Prop_carry4_CYINIT_CO[3])
0.788 54.104 r data_r_reg[2]_i_11/CO[3]
net (fo=1, unplaced) 0.009 54.113 data_r_reg[2]_i_11_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 54.227 r data_r_reg[2]_i_6/CO[3]
net (fo=1, unplaced) 0.000 54.227 data_r_reg[2]_i_6_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 54.341 r data_r_reg[2]_i_3/CO[3]
net (fo=1, unplaced) 0.000 54.341 data_r_reg[2]_i_3_n_0
CARRY4 (Prop_carry4_CI_CO[1])
0.178 54.519 r data_r_reg[2]_i_2/CO[1]
net (fo=23, unplaced) 0.588 55.107 div_result[2]
CARRY4 (Prop_carry4_CYINIT_CO[3])
0.788 55.895 r data_r_reg[1]_i_11/CO[3]
net (fo=1, unplaced) 0.009 55.904 data_r_reg[1]_i_11_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 56.018 r data_r_reg[1]_i_6/CO[3]
net (fo=1, unplaced) 0.000 56.018 data_r_reg[1]_i_6_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 56.132 r data_r_reg[1]_i_3/CO[3]
net (fo=1, unplaced) 0.000 56.132 data_r_reg[1]_i_3_n_0
CARRY4 (Prop_carry4_CI_CO[1])
0.178 56.310 r data_r_reg[1]_i_2/CO[1]
net (fo=23, unplaced) 0.588 56.898 div_result[1]
CARRY4 (Prop_carry4_CYINIT_CO[3])
0.788 57.686 r data_r_reg[0]_i_10/CO[3]
net (fo=1, unplaced) 0.009 57.695 data_r_reg[0]_i_10_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 57.809 r data_r_reg[0]_i_5/CO[3]
net (fo=1, unplaced) 0.000 57.809 data_r_reg[0]_i_5_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 57.923 r data_r_reg[0]_i_3/CO[3]
net (fo=1, unplaced) 0.000 57.923 data_r_reg[0]_i_3_n_0
CARRY4 (Prop_carry4_CI_CO[0])
0.293 58.216 f data_r_reg[0]_i_2/CO[0]
net (fo=3, unplaced) 0.329 58.545 u_comp/u_pipe/div_result[0]
LUT1 (Prop_lut1_I0_O) 0.367 58.912 r u_comp/u_pipe/data_r[3]_i_11/O
net (fo=1, unplaced) 0.000 58.912 u_comp/u_pipe/data_r[3]_i_11_n_0
CARRY4 (Prop_carry4_S[0]_CO[3])
0.532 59.444 r u_comp/u_pipe/data_r_reg[3]_i_3/CO[3]
net (fo=1, unplaced) 0.009 59.453 u_comp/u_pipe/data_r_reg[3]_i_3_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.114 59.567 r u_comp/u_pipe/data_r_reg[7]_i_3/CO[3]
net (fo=1, unplaced) 0.000 59.567 u_comp/u_pipe/data_r_reg[7]_i_3_n_0
CARRY4 (Prop_carry4_CI_O[3])
0.329 59.896 r u_comp/u_pipe/data_r_reg[11]_i_5/O[3]
net (fo=2, unplaced) 0.824 60.720 u_comp/u_pipe/data_r_reg[11]_i_5_n_4
CARRY4 (Prop_carry4_S[3]_CO[3])
0.709 61.429 r u_comp/u_pipe/data_r_reg[11]_i_3/CO[3]
net (fo=1, unplaced) 0.000 61.429 u_comp/u_pipe/data_r_reg[11]_i_3_n_0
CARRY4 (Prop_carry4_CI_CO[0])
0.293 61.722 r u_comp/u_pipe/data_r_reg[11]_i_4/CO[0]
net (fo=12, unplaced) 0.359 62.081 u_comp/u_pipe/data_r_reg[11]_i_4_n_3
LUT5 (Prop_lut5_I1_O) 0.367 62.448 r u_comp/u_pipe/data_r[0]_i_1/O
net (fo=1, unplaced) 0.000 62.448 u_comp/u_pipe/mod_result[0]
FDCE r u_comp/u_pipe/data_r_reg[0]/D
------------------------------------------------------------------- -------------------
(clock sysclk rise edge) 20.000 20.000 r
0.000 20.000 r clk (IN)
net (fo=0) 0.000 20.000 clk
IBUF (Prop_ibuf_I_O) 0.817 20.817 r clk_IBUF_inst/O
net (fo=1, unplaced) 0.760 21.576 clk_IBUF
BUFG (Prop_bufg_I_O) 0.091 21.667 r clk_IBUF_BUFG_inst/O
net (fo=23790, unplaced) 0.439 22.106 u_comp/u_pipe/clk_IBUF_BUFG
FDCE r u_comp/u_pipe/data_r_reg[0]/C
clock pessimism 0.178 22.285
clock uncertainty -0.035 22.249
FDCE (Setup_fdce_C_D) 0.029 22.278 u_comp/u_pipe/data_r_reg[0]
-------------------------------------------------------------------
required time 22.278
arrival time -62.448
-------------------------------------------------------------------
slack -40.169
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.080ns (arrival time - required time)
Source: u_pmul/FSM_onehot_state_reg[3]/C
(rising edge-triggered cell FDCE clocked by sysclk {rise@0.000ns fall@10.000ns period=20.000ns})
Destination: u_pmul/u_bc/valid_sr_reg[4]_srl5_u_pmul_u_bc_valid_sr_reg_c_3/D
(rising edge-triggered cell SRL16E clocked by sysclk {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: sysclk
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (sysclk rise@0.000ns - sysclk rise@0.000ns)
Data Path Delay: 0.289ns (logic 0.141ns (48.726%) route 0.148ns (51.274%))
Logic Levels: 0
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.011ns
Source Clock Delay (SCD): 0.656ns
Clock Pessimism Removal (CPR): 0.209ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sysclk rise edge) 0.000 0.000 r
0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 clk
IBUF (Prop_ibuf_I_O) 0.179 0.179 r clk_IBUF_inst/O
net (fo=1, unplaced) 0.337 0.516 clk_IBUF
BUFG (Prop_bufg_I_O) 0.026 0.542 r clk_IBUF_BUFG_inst/O
net (fo=23790, unplaced) 0.114 0.656 u_pmul/clk_IBUF_BUFG
FDCE r u_pmul/FSM_onehot_state_reg[3]/C
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.141 0.797 r u_pmul/FSM_onehot_state_reg[3]/Q
net (fo=3, unplaced) 0.148 0.946 u_pmul/u_bc/Q[3]
SRL16E r u_pmul/u_bc/valid_sr_reg[4]_srl5_u_pmul_u_bc_valid_sr_reg_c_3/D
------------------------------------------------------------------- -------------------
(clock sysclk rise edge) 0.000 0.000 r
0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 clk
IBUF (Prop_ibuf_I_O) 0.368 0.368 r clk_IBUF_inst/O
net (fo=1, unplaced) 0.355 0.723 clk_IBUF
BUFG (Prop_bufg_I_O) 0.029 0.752 r clk_IBUF_BUFG_inst/O
net (fo=23790, unplaced) 0.259 1.011 u_pmul/u_bc/clk_IBUF_BUFG
SRL16E r u_pmul/u_bc/valid_sr_reg[4]_srl5_u_pmul_u_bc_valid_sr_reg_c_3/CLK
clock pessimism -0.209 0.801
SRL16E (Hold_srl16e_CLK_D)
0.064 0.865 u_pmul/u_bc/valid_sr_reg[4]_srl5_u_pmul_u_bc_valid_sr_reg_c_3
-------------------------------------------------------------------
required time -0.865
arrival time 0.946
-------------------------------------------------------------------
slack 0.080
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: sysclk
Waveform(ns): { 0.000 10.000 }
Period(ns): 20.000
Sources: { clk }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 u_ct_bram/mem_reg/CLKARDCLK
Low Pulse Width Slow SRL16E/CLK n/a 0.980 10.000 9.020 u_pmul/u_bc/t1_s4_reg[0]_srl2_u_pmul_u_bc_valid_sr_reg_c_0/CLK
High Pulse Width Fast SRL16E/CLK n/a 0.980 10.000 9.020 u_pmul/u_bc/t1_s4_reg[0]_srl2_u_pmul_u_bc_valid_sr_reg_c_0/CLK