fix(tb): fix Vivado 2019.2 compatibility and add run_tb.sh

- Replace -include_dirs . with -i . (Vivado 2019.2 syntax)
- Add --timescale 1ns/1ps to all xelab commands
- Add LD_PRELOAD comment for ncurses compatibility
- Add run_tb.sh convenience script
  Usage: ./run_tb.sh mod_add
         ./run_tb.sh --list
- Update spec with Vivado 2019.2 compatibility notes

sync_rtl/mod_add/TB/xsim_run.tcl

@@ -1,3 +1,7 @@
+# NOTE: On some systems, you may need:
+#   export LD_PRELOAD=/usr/lib64/libtinfo.so.5
+# before running this script.
+
 # xsim_run.tcl - Vivado xsim compilation and simulation script for mod_add_sync
 #
 # Compiles mod_add_sync RTL plus the file-based vector testbench and runs simulation.
@@ -29,10 +33,10 @@ set COMMON_DIR sync_rtl/common
 puts "=== Compiling RTL sources ==="
 
 # Common pipeline register
-xvlog -sv -include_dirs . ${COMMON_DIR}/pipeline_reg.v
+xvlog -sv -i . ${COMMON_DIR}/pipeline_reg.v
 
 # mod_add_sync (includes defines.vh from common/)
-xvlog -sv -include_dirs . ${SRC_DIR}/mod_add_sync.v
+xvlog -sv -i . ${SRC_DIR}/mod_add_sync.v
 
 # ================================================================
 # Step 2: Compile testbench
@@ -47,7 +51,7 @@ xvlog -sv ${TB_DIR}/tb_mod_add_xsim.v
 # ================================================================
 puts "=== Elaborating snapshot ==="
 
-xelab tb_mod_add_xsim -s tb_mod_add_xsim
+xelab tb_mod_add_xsim -s tb_mod_add_xsim --timescale 1ns/1ps
 
 # ================================================================
 # Step 4: Run simulation