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fix(tb): fix Vivado 2019.2 compatibility and add run_tb.sh

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- Replace -include_dirs . with -i . (Vivado 2019.2 syntax)
- Add --timescale 1ns/1ps to all xelab commands
- Add LD_PRELOAD comment for ncurses compatibility
- Add run_tb.sh convenience script
  Usage: ./run_tb.sh mod_add
         ./run_tb.sh --list
- Update spec with Vivado 2019.2 compatibility notes
This commit is contained in:
FallenSigh
2026-06-25 20:53:47 +08:00
parent 52c625b3ef
commit 79653ac3a5
13 changed files with 181 additions and 27 deletions
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10
sync_rtl/comp_decomp/TB/xsim_run.tcl
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@@ -1,3 +1,7 @@
# NOTE: On some systems, you may need:
# export LD_PRELOAD=/usr/lib64/libtinfo.so.5
# before running this script.
# xsim_run.tcl - Vivado xsim compilation and simulation script for comp_decomp_sync
#
# Compiles comp_decomp_sync RTL + dependencies + testbench and runs simulation.
@@ -31,10 +35,10 @@ set TB_DIR sync_rtl/comp_decomp/TB
puts "=== Compiling RTL sources for comp_decomp_sync ==="
# Common dependency (pipeline register)
xvlog -sv -include_dirs . ${RTL_DIR}/common/pipeline_reg.v
xvlog -sv -i . ${RTL_DIR}/common/pipeline_reg.v
# DUT (comp_decomp_sync) — uses `include "sync_rtl/common/defines.vh"
xvlog -sv -include_dirs . ${DUT_DIR}/comp_decomp_sync.v
xvlog -sv -i . ${DUT_DIR}/comp_decomp_sync.v
# ================================================================
# Step 2: Compile testbench
@@ -48,7 +52,7 @@ xvlog -sv ${TB_DIR}/tb_comp_decomp_xsim.v
# ================================================================
puts "=== Elaborating snapshot ==="
xelab tb_comp_decomp_xsim -s tb_comp_decomp_xsim
xelab tb_comp_decomp_xsim -s tb_comp_decomp_xsim --timescale 1ns/1ps
# ================================================================
# Step 4: Run simulation

10
sync_rtl/mod_add/TB/xsim_run.tcl
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@@ -1,3 +1,7 @@
# NOTE: On some systems, you may need:
# export LD_PRELOAD=/usr/lib64/libtinfo.so.5
# before running this script.
# xsim_run.tcl - Vivado xsim compilation and simulation script for mod_add_sync
#
# Compiles mod_add_sync RTL plus the file-based vector testbench and runs simulation.
@@ -29,10 +33,10 @@ set COMMON_DIR sync_rtl/common
puts "=== Compiling RTL sources ==="
# Common pipeline register
xvlog -sv -include_dirs . ${COMMON_DIR}/pipeline_reg.v
xvlog -sv -i . ${COMMON_DIR}/pipeline_reg.v
# mod_add_sync (includes defines.vh from common/)
xvlog -sv -include_dirs . ${SRC_DIR}/mod_add_sync.v
xvlog -sv -i . ${SRC_DIR}/mod_add_sync.v
# ================================================================
# Step 2: Compile testbench
@@ -47,7 +51,7 @@ xvlog -sv ${TB_DIR}/tb_mod_add_xsim.v
# ================================================================
puts "=== Elaborating snapshot ==="
xelab tb_mod_add_xsim -s tb_mod_add_xsim
xelab tb_mod_add_xsim -s tb_mod_add_xsim --timescale 1ns/1ps
# ================================================================
# Step 4: Run simulation

6
sync_rtl/ntt/TB/xsim_run.tcl
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@@ -1,3 +1,7 @@
# NOTE: On some systems, you may need:
# export LD_PRELOAD=/usr/lib64/libtinfo.so.5
# before running this script.
# xsim_run.tcl - Vivado xsim compilation and simulation script for NTT
#
# Compiles all NTT RTL sources plus testbench and runs simulation.
@@ -49,7 +53,7 @@ xvlog -sv ${TB_DIR}/tb_ntt_core_xsim.v
# ================================================================
puts "=== Elaborating snapshot ==="
xelab tb_ntt_core_xsim -s ntt_core_sim
xelab tb_ntt_core_xsim -s ntt_core_sim --timescale 1ns/1ps
# ================================================================
# Step 4: Run simulation

10
sync_rtl/poly_arith/TB/xsim_run.tcl
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@@ -1,3 +1,7 @@
# NOTE: On some systems, you may need:
# export LD_PRELOAD=/usr/lib64/libtinfo.so.5
# before running this script.
# xsim_run.tcl - Vivado xsim compilation and simulation script for poly_arith_sync
#
# Compiles poly_arith_sync RTL + dependencies + testbench and runs simulation.
@@ -31,10 +35,10 @@ set TB_DIR sync_rtl/poly_arith/TB
puts "=== Compiling RTL sources for poly_arith_sync ==="
# Common dependency (pipeline register)
xvlog -sv -include_dirs . ${RTL_DIR}/common/pipeline_reg.v
xvlog -sv -i . ${RTL_DIR}/common/pipeline_reg.v
# DUT (poly_arith_sync) — uses `include "sync_rtl/common/defines.vh"
xvlog -sv -include_dirs . ${DUT_DIR}/poly_arith_sync.v
xvlog -sv -i . ${DUT_DIR}/poly_arith_sync.v
# ================================================================
# Step 2: Compile testbench
@@ -48,7 +52,7 @@ xvlog -sv ${TB_DIR}/tb_poly_arith_xsim.v
# ================================================================
puts "=== Elaborating snapshot ==="
xelab tb_poly_arith_xsim -s tb_poly_arith_xsim
xelab tb_poly_arith_xsim -s tb_poly_arith_xsim --timescale 1ns/1ps
# ================================================================
# Step 4: Run simulation

6
sync_rtl/poly_mul/TB/xsim_run.tcl
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@@ -1,3 +1,7 @@
# NOTE: On some systems, you may need:
# export LD_PRELOAD=/usr/lib64/libtinfo.so.5
# before running this script.
# xsim_run.tcl - Vivado xsim compilation and simulation script for PolyMul
#
# Compiles all PolyMul RTL sources plus dependencies, then testbench,
@@ -56,7 +60,7 @@ xvlog -sv ${TB_DIR}/tb_poly_mul_xsim.v
# ================================================================
puts "=== Elaborating snapshot ==="
xelab tb_poly_mul_xsim -s poly_mul_sim
xelab tb_poly_mul_xsim -s poly_mul_sim --timescale 1ns/1ps
# ================================================================
# Step 5: Run simulation

6
sync_rtl/rng/TB/xsim_run.tcl
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@@ -1,3 +1,7 @@
# NOTE: On some systems, you may need:
# export LD_PRELOAD=/usr/lib64/libtinfo.so.5
# before running this script.
# xsim_run.tcl - Vivado xsim compilation and simulation script for rng_sync
#
# Compiles rng_sync RTL plus the file-based vector testbench and runs simulation.
@@ -42,7 +46,7 @@ xvlog -sv ${TB_DIR}/tb_rng_xsim.v
# ================================================================
puts "=== Elaborating snapshot ==="
xelab tb_rng_xsim -s tb_rng_xsim
xelab tb_rng_xsim -s tb_rng_xsim --timescale 1ns/1ps
# ================================================================
# Step 4: Run simulation

6
sync_rtl/sample_cbd/TB/xsim_run.tcl
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@@ -1,3 +1,7 @@
# NOTE: On some systems, you may need:
# export LD_PRELOAD=/usr/lib64/libtinfo.so.5
# before running this script.
# xsim_run.tcl - Vivado xsim compilation and simulation for sample_cbd_sync
#
# Compiles sample_cbd_sync RTL + SHA3 dependencies + testbench and runs simulation.
@@ -44,7 +48,7 @@ xvlog -sv ${TB_DIR}/tb_sample_cbd_xsim.v
# Step 3: Elaborate snapshot (xelab)
# ================================================================
puts "=== Elaborating snapshot ==="
xelab tb_sample_cbd_xsim -s tb_sample_cbd_xsim
xelab tb_sample_cbd_xsim -s tb_sample_cbd_xsim --timescale 1ns/1ps
# ================================================================
# Step 4: Run simulation

12
sync_rtl/sample_ntt/TB/xsim_run.tcl
View File

@@ -1,3 +1,7 @@
# NOTE: On some systems, you may need:
# export LD_PRELOAD=/usr/lib64/libtinfo.so.5
# before running this script.
# xsim_run.tcl - Vivado xsim compilation and simulation for sample_ntt_sync
#
# Compiles sample_ntt_sync RTL + SHA3 dependencies + testbench and runs simulation.
@@ -26,13 +30,13 @@ set TB_DIR sync_rtl/sample_ntt/TB
puts "=== Compiling RTL sources ==="
# Keccak round (combinational, used by keccak_core)
xvlog -sv -include_dirs . ${SHA3_DIR}/keccak_round.v
xvlog -sv -i . ${SHA3_DIR}/keccak_round.v
# Keccak core (24-round sequential core, used by sample_ntt_sync)
xvlog -sv -include_dirs . ${SHA3_DIR}/keccak_core.v
xvlog -sv -i . ${SHA3_DIR}/keccak_core.v
# sample_ntt_sync (DUT) — uses `include "sync_rtl/common/defines.vh"
xvlog -sv -include_dirs . ${SRC_DIR}/sample_ntt_sync.v
xvlog -sv -i . ${SRC_DIR}/sample_ntt_sync.v
# ================================================================
# Step 2: Compile testbench
@@ -44,7 +48,7 @@ xvlog -sv ${TB_DIR}/tb_sample_ntt_xsim.v
# Step 3: Elaborate snapshot (xelab)
# ================================================================
puts "=== Elaborating snapshot ==="
xelab tb_sample_ntt_xsim -s tb_sample_ntt_xsim
xelab tb_sample_ntt_xsim -s tb_sample_ntt_xsim --timescale 1ns/1ps
# ================================================================
# Step 4: Run simulation

10
sync_rtl/sha3/TB/xsim_run.tcl
View File

@@ -1,3 +1,7 @@
# NOTE: On some systems, you may need:
# export LD_PRELOAD=/usr/lib64/libtinfo.so.5
# before running this script.
# xsim_run.tcl - Vivado xsim compilation and simulation script
#
# Compiles all SHA3 RTL sources plus testbenches and runs simulation.
@@ -62,13 +66,13 @@ xvlog -sv ${TB_DIR}/tb_sha3_xsim.v
puts "=== Elaborating snapshots ==="
# Simple sha3_top testbench (G mode, hardcoded vector)
xelab tb_sha3_xsim_simple -s sha3_simple_sim
xelab tb_sha3_xsim_simple -s sha3_simple_sim --timescale 1ns/1ps
# Keccak core testbench (all-zero input)
xelab tb_keccak_core_xsim -s keccak_core_sim
xelab tb_keccak_core_xsim -s keccak_core_sim --timescale 1ns/1ps
# File-based sha3_top testbench (reads vectors/g_basic_input.hex)
xelab tb_sha3_xsim -s tb_sha3_xsim
xelab tb_sha3_xsim -s tb_sha3_xsim --timescale 1ns/1ps
# ================================================================
# Step 4: Run simulations

6
sync_rtl/sha3_chain/TB/xsim_run.tcl
View File

@@ -1,3 +1,7 @@
# NOTE: On some systems, you may need:
# export LD_PRELOAD=/usr/lib64/libtinfo.so.5
# before running this script.
# xsim_run.tcl - Vivado xsim compilation and simulation script
#
# Compiles sha3_chain_top with all SHA3 dependencies plus testbench.
@@ -52,7 +56,7 @@ xvlog -sv ${TB_DIR}/tb_sha3_chain_xsim.v
# ================================================================
puts "=== Elaborating snapshot ==="
xelab tb_sha3_chain_xsim -s tb_sha3_chain_xsim
xelab tb_sha3_chain_xsim -s tb_sha3_chain_xsim --timescale 1ns/1ps
# ================================================================
# Step 4: Run simulation

6
sync_rtl/storage/TB/xsim_run.tcl
View File

@@ -1,3 +1,7 @@
# NOTE: On some systems, you may need:
# export LD_PRELOAD=/usr/lib64/libtinfo.so.5
# before running this script.
# xsim_run.tcl - Vivado xsim compilation and simulation script
#
# Compiles s_bram, sd_bram, and tb_storage_xsim testbench.
@@ -36,7 +40,7 @@ xvlog -sv ${TB_DIR}/tb_storage_xsim.v
# ================================================================
puts "=== Elaborating snapshot ==="
xelab tb_storage_xsim -s tb_storage_xsim
xelab tb_storage_xsim -s tb_storage_xsim --timescale 1ns/1ps
# ================================================================
# Step 4: Run simulation