diff --git a/sync_rtl/sample_ntt/TB/tb_sample_ntt_xsim.v b/sync_rtl/sample_ntt/TB/tb_sample_ntt_xsim.v
index 3618a4c..28a50d4 100644
--- a/sync_rtl/sample_ntt/TB/tb_sample_ntt_xsim.v
+++ b/sync_rtl/sample_ntt/TB/tb_sample_ntt_xsim.v
@@ -208,8 +208,22 @@ module tb_sample_ntt_xsim;
                 // Wait for DUT to return to IDLE before next vector.
                 // The DUT may still be processing its last Keccak permutation
                 // (ST_WAIT → ST_DONE → ST_IDLE), which takes ~20+ cycles.
-                while (!ready_o) begin
-                    @(posedge clk);
+                // ASSERTION: after the 256th coeff (last_o), valid_o must stay
+                // low until IDLE — any extra pulse is a spurious 257th output
+                // (regression guard for the phase-1 need_more fix).
+                begin
+                    integer extra_pulses;
+                    extra_pulses = 0;
+                    while (!ready_o) begin
+                        @(posedge clk);
+                        if (valid_o) extra_pulses = extra_pulses + 1;
+                    end
+                    if (extra_pulses != 0) begin
+                        $display("ERROR: Vector %0d emitted %0d spurious valid_o pulse(s) after last_o",
+                                 idx, extra_pulses);
+                        fail_count = fail_count + 1;
+                        if (pass_count > 0) pass_count = pass_count - 1; // revoke the earlier PASS
+                    end
                 end
             end  // inner begin block
         end
diff --git a/sync_rtl/sample_ntt/sample_ntt_sync.v b/sync_rtl/sample_ntt/sample_ntt_sync.v
index 97621a0..3a20aee 100644
--- a/sync_rtl/sample_ntt/sample_ntt_sync.v
+++ b/sync_rtl/sample_ntt/sample_ntt_sync.v
@@ -334,7 +334,7 @@ module sample_ntt_sync #(parameter K = 4) (
 
                     // ----- Phase 1: output d1 -----
                     2'd1: begin
-                        if (d1_acc_r) begin
+                        if (d1_acc_r && need_more) begin
                             if (!valid_o_r) begin
                                 // First cycle: assert output
                                 coeff_o_r <= d1_r;
@@ -349,7 +349,7 @@ module sample_ntt_sync #(parameter K = 4) (
                                 end
                             end
                         end else begin
-                            // d1 rejected, skip to phase 2
+                            // d1 rejected or no longer needed: skip to phase 2
                             valid_o_r  <= 1'b0;
                             sq_phase_r <= 2'd2;
                         end
diff --git a/sync_rtl/sample_ntt/sample_ntt_sync_shared.v b/sync_rtl/sample_ntt/sample_ntt_sync_shared.v
index 5339a4b..da03515 100644
--- a/sync_rtl/sample_ntt/sample_ntt_sync_shared.v
+++ b/sync_rtl/sample_ntt/sample_ntt_sync_shared.v
@@ -348,7 +348,7 @@ module sample_ntt_sync_shared #(parameter K = 4) (
 
                     // ----- Phase 1: output d1 -----
                     2'd1: begin
-                        if (d1_acc_r) begin
+                        if (d1_acc_r && need_more) begin
                             if (!valid_o_r) begin
                                 // First cycle: assert output
                                 coeff_o_r <= d1_r;
@@ -363,7 +363,7 @@ module sample_ntt_sync_shared #(parameter K = 4) (
                                 end
                             end
                         end else begin
-                            // d1 rejected, skip to phase 2
+                            // d1 rejected or no longer needed: skip to phase 2
                             valid_o_r  <= 1'b0;
                             sq_phase_r <= 2'd2;
                         end