feat(phase1): implement RNG, SampleCBD, SampleNTT modules + xsim TBs

Phase 1 complete — all 4 leaf modules verified:
- rng_sync.v: 256-bit Galois LFSR PRNG (10/10 PASS)
- sample_cbd_sync.v: CBD sampler with keccak_core PRF (2560/2560 PASS)
- sample_ntt_sync.v: SHAKE-128 rejection sampling for A matrix (1536/1536 PASS)
- xsim Verilog TBs for sha3 module (tb_sha3_xsim.v, tb_sha3_xsim_simple.v, tb_keccak_core_xsim.v)

sync_rtl/rng/TB/tb_rng.cpp

@@ -0,0 +1,94 @@
+// tb_rng.cpp - Verilator C++ testbench for rng_sync
+//
+// Drives valid_i pulses and prints 256-bit LFSR output values.
+// Reads a hex input file to determine how many vectors to generate
+// (one line per vector, content ignored).
+// Prints "RESULT: <64-char hex>" for each output.
+//
+// Clock: 10ns period. Reset: 2 cycles low.
+// Timeout: 100,000 cycles.
+
+#include <iostream>
+#include <fstream>
+#include <string>
+#include <cstdio>
+#include "Vrng_sync.h"
+#include "verilated.h"
+
+#define CLK_PERIOD_NS 10.0
+
+static vluint64_t main_time = 0;
+
+double sc_time_stamp() {
+    return main_time;
+}
+
+int main(int argc, char** argv) {
+    Verilated::commandArgs(argc, argv);
+
+    // Parse +VECTOR_FILE= plusarg
+    const char* vector_file = NULL;
+    for (int i = 1; i < argc; i++) {
+        std::string arg(argv[i]);
+        if (arg.rfind("+VECTOR_FILE=", 0) == 0) {
+            vector_file = argv[i] + 13;
+        }
+    }
+
+    if (!vector_file) {
+        std::cerr << "ERROR: +VECTOR_FILE= not specified" << std::endl;
+        return 1;
+    }
+
+    std::ifstream infile(vector_file);
+    if (!infile.is_open()) {
+        std::cerr << "ERROR: Cannot open vector file: " << vector_file << std::endl;
+        return 1;
+    }
+
+    // Count non-empty, non-comment lines to determine vector count
+    int num_vectors = 0;
+    std::string line;
+    while (std::getline(infile, line)) {
+        if (!line.empty() && line[0] != '#')
+            num_vectors++;
+    }
+    infile.close();
+
+    // Instantiate DUT
+    Vrng_sync* dut = new Vrng_sync;
+
+    // Initialize
+    dut->clk     = 0;
+    dut->rst_n   = 0;
+    dut->valid_i = 0;
+    dut->ready_i = 0;
+
+    // Reset: 2 cycles low
+    for (int i = 0; i < 4; i++) {
+        dut->clk = 1; main_time += 5; dut->eval();
+        dut->clk = 0; main_time += 5; dut->eval();
+    }
+    dut->rst_n   = 1;
+    dut->ready_i = 1;
+
+    // Generate vectors
+    for (int n = 0; n < num_vectors; n++) {
+        // Drive valid_i and posedge → LFSR advances, valid_o→1
+        dut->valid_i = 1;
+        dut->clk = 1; main_time += 5; dut->eval();
+        dut->clk = 0; main_time += 5; dut->eval();
+        dut->valid_i = 0;
+
+        // Posedge to consume → valid_o→0
+        dut->clk = 1; main_time += 5; dut->eval();
+        // Print 256-bit result (8 × 32-bit words, MSB first)
+        printf("RESULT: %08X%08X%08X%08X%08X%08X%08X%08X\n",
+               dut->data_o[7], dut->data_o[6], dut->data_o[5], dut->data_o[4],
+               dut->data_o[3], dut->data_o[2], dut->data_o[1], dut->data_o[0]);
+        dut->clk = 0; main_time += 5; dut->eval();
+    }
+
+    delete dut;
+    return 0;
+}

sync_rtl/rng/rng_sync.v

@@ -0,0 +1,50 @@
+// rng_sync.v - 256-bit Galois LFSR PRNG (taps: 255,253,252,247,0)
+module rng_sync #(
+    parameter [255:0] SEED = 256'hDEADBEEFCAFEBABEFEEDFACEDECAFBAD1234567887654321ABCDEF010FEDCBA9
+) (
+    input              clk,
+    input              rst_n,
+    input              valid_i,
+    output             ready_o,
+    output [255:0]     data_o,
+    output             valid_o,
+    input              ready_i
+);
+
+    reg  [255:0] state;
+    reg          valid_r;
+    reg  [255:0] lfsr_next;
+    wire         feedback;
+    integer      i;
+
+    assign ready_o = 1'b1;
+    assign valid_o = valid_r;
+    assign data_o  = state;
+    assign feedback = state[0];
+
+    always @(*) begin
+        for (i = 0; i < 255; i = i + 1)
+            lfsr_next[i] = state[i+1];
+        lfsr_next[255] = feedback;
+        lfsr_next[254] = lfsr_next[254] ^ feedback;
+        lfsr_next[252] = lfsr_next[252] ^ feedback;
+        lfsr_next[251] = lfsr_next[251] ^ feedback;
+        lfsr_next[246] = lfsr_next[246] ^ feedback;
+    end
+
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            state   <= SEED;
+            valid_r <= 1'b0;
+        end else begin
+            if (valid_r && ready_i)
+                valid_r <= 1'b0;
+
+            if (valid_i) begin
+                state   <= lfsr_next;
+                valid_r <= 1'b1;
+            end
+        end
+    end
+
+endmodule