diff --git a/create_project.tcl b/create_project.tcl
index b4f7bfc..96716bc 100644
--- a/create_project.tcl
+++ b/create_project.tcl
@@ -36,11 +36,11 @@ set_property target_simulator XSim [current_project]
 # ── SHA3 / Keccak ──
 read_verilog -sv ${PROJECT_DIR}/sync_rtl/sha3/keccak_round.v
 read_verilog -sv ${PROJECT_DIR}/sync_rtl/sha3/keccak_core.v
-read_verilog -sv ${PROJECT_DIR}/sync_rtl/sha3/sha3_top.v
+read_verilog -sv ${PROJECT_DIR}/sync_rtl/sha3/sha3_top_shared.v
 
-# ── 采样 ──
-read_verilog -sv ${PROJECT_DIR}/sync_rtl/sample_ntt/sample_ntt_sync.v
-read_verilog -sv ${PROJECT_DIR}/sync_rtl/sample_cbd/sample_cbd_sync.v
+# ── 采样（共享 keccak_core 变体）──
+read_verilog -sv ${PROJECT_DIR}/sync_rtl/sample_ntt/sample_ntt_sync_shared.v
+read_verilog -sv ${PROJECT_DIR}/sync_rtl/sample_cbd/sample_cbd_sync_shared.v
 
 # ── NTT ──
 read_verilog -sv ${PROJECT_DIR}/sync_rtl/ntt/barrett_mul.v