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chore(enc): merge run_enc.sh into run_tb.sh; TB dumps hardware ct

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run_tb.sh gains an 'enc' module that shares the 'top' KeyGen tcl compile
list (same RTL datapath) and swaps in tb_mlkem_enc_katK_xsim. Usage mirrors
'top': ./run_tb.sh enc [K] [CASE]; no args -> full sweep K=2/3/4 cases 0..2.
--list shows enc; per-case summary lines parse PASS (E7). run_enc.sh deleted.

tb_mlkem_enc_katK_xsim verify_e7 now dumps the hardware-produced ct (read
from ct_bram via the dbg_ct tap) on one line (byte 0 first), same format as
ml-kem-r's encaps_io example, so ss/ct can be eyeballed and diffed. On
mismatch it re-scans to print the first 8 differing byte positions.

Verified: ./run_tb.sh enc -> 9/9 PASS (E7) (ct==KAT.ct && ss==KAT.ss);
./run_tb.sh top 3 0 KeyGen unregressed.
This commit is contained in:
FallenSigh
2026-06-29 12:32:29 +08:00
parent 7228bebb78
commit 4091fd0676
4 changed files with 92 additions and 54 deletions
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22
sync_rtl/top/TB/tb_mlkem_enc_katK_xsim.v
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@@ -254,16 +254,34 @@ module tb_mlkem_enc_katK_xsim;
integer be;
begin
be = 0;
// Dump the hardware-produced ct (read from ct_bram via dbg_ct tap),
// then compare to KAT.ct byte-exact. The $write loop prints the whole
// ciphertext on one line (byte 0 first), same format as ml-kem-r's
// encaps_io example, so the two can be eyeballed / diffed.
$write(" ct = ");
for (i = 0; i < CTB; i = i + 1) begin
dbg_ct_idx_i = i[10:0];
@(posedge clk); @(posedge clk); @(posedge clk);
$write("%02x", dbg_ct_o);
if (dbg_ct_o !== ct_b[i]) begin
if (be < 8) $display(" CT[%0d] got=%02x exp=%02x", i, dbg_ct_o, ct_b[i]);
be = be + 1;
end
end
$write("\n");
if (be == 0) $display("K=%0d CASE %0d PASS (E7): ct (%0d B) == KAT.ct [ct==KAT.ct && ss==KAT.ss]", KP, casenum, CTB);
else $display("K=%0d CASE %0d FAIL (E7): %0d ct byte mismatches", KP, casenum, be);
else begin
$display("K=%0d CASE %0d FAIL (E7): %0d ct byte mismatches", KP, casenum, be);
// re-scan to print the first few mismatching byte positions
be = 0;
for (i = 0; i < CTB; i = i + 1) begin
dbg_ct_idx_i = i[10:0];
@(posedge clk); @(posedge clk); @(posedge clk);
if (dbg_ct_o !== ct_b[i]) begin
if (be < 8) $display(" CT[%0d] got=%02x exp=%02x", i, dbg_ct_o, ct_b[i]);
be = be + 1;
end
end
end
end
endtask
endmodule