{
  "module": "mod_add",
  "rtl_top": "sync_rtl/mod_add/mod_add_sync.v",
  "rtl_deps": ["sync_rtl/common/pipeline_reg.v"],
  "tb_cpp": "sync_rtl/mod_add/TB/tb_mod_add.cpp",
  "simulator": "verilator",
  "timeout_s": 30,
  "cases": [
    {
      "id": "basic",
      "description": "Random (a+b) mod Q pairs, no overflow, with overflow, edge cases",
      "params": {},
      "num_vectors": 50,
      "tolerance": "bit_exact"
    }
  ]
}
