// mod_add_sync.v - Synchronous modular adder for ML-KEM
//
// Computes (a + b) mod Q where Q = 3329.
// Uses pipeline_reg internally for the computation stage.
// Result is valid one cycle after valid_i && ready_o.
//
// Interface:
//   clk, rst_n    - clock, active-low reset
//   a, b          - operands (0 <= a,b < Q)
//   valid_i, ready_o, sum, valid_o, ready_i - valid/ready handshake

`include "sync_rtl/common/defines.vh"

module mod_add_sync (
    input         clk,
    input         rst_n,
    input  [11:0] a,
    input  [11:0] b,
    input         valid_i,
    output        ready_o,
    output [11:0] sum,
    output        valid_o,
    input         ready_i
);

    // Compute (a + b) mod Q
    wire [12:0] add_raw;       // 13 bits to hold potential overflow
    wire [11:0] add_sub_q;     // (a + b) - Q
    wire [11:0] mod_result;    // final (a + b) mod Q

    assign add_raw   = {1'b0, a} + {1'b0, b};
    assign add_sub_q = add_raw[11:0] - `Q;
    assign mod_result = (add_raw < `Q) ? add_raw[11:0] : add_sub_q;

    // Pipeline the result through pipeline_reg
    pipeline_reg #(.DW(12)) u_pipe (
        .clk    (clk),
        .rst_n  (rst_n),
        .data_i (mod_result),
        .valid_i(valid_i),
        .ready_o(ready_o),
        .data_o (sum),
        .valid_o(valid_o),
        .ready_i(ready_i)
    );

endmodule
