// s_bram.v - Single-port behavioral RAM (shared read/write port)
//
// One port: either read or write per cycle (+1 cycle read latency).
// When both rd_en and wr_en are high, write takes priority.
// Read data is registered (1-cycle latency after rd_en).
// No valid/ready handshake — pure memory, handshake managed at higher level.

module s_bram #(
    parameter W = 48,
    parameter D = 512,
    parameter A = 9
) (
    input  wire          clk,
    input  wire          rd_en,
    input  wire [A-1:0]  rd_addr,
    output reg  [W-1:0]  rd_data,
    input  wire          wr_en,
    input  wire [A-1:0]  wr_addr,
    input  wire [W-1:0]  wr_data
);

    reg [W-1:0] mem [0:D-1];

    always @(posedge clk) begin
        if (wr_en)
            mem[wr_addr] <= wr_data;
        else if (rd_en)
            rd_data <= mem[rd_addr];
    end

endmodule
