# NOTE: On some systems, you may need:
#   export LD_PRELOAD=/usr/lib64/libtinfo.so.5
# before running this script.

# xsim_run.tcl - Vivado xsim compilation and simulation script for NTT
#
# Compiles all NTT RTL sources plus testbench and runs simulation.
# Run from the project root: ~/Dev/mlkem/
#
# Prerequisites:
#   source /opt/Xilinx/Vivado/2019.2/settings64.sh
#
# Usage examples:
#   # Run ntt_core testbench
#   xsim ntt_core_sim -R
#
#   # Step-by-step:
#   vivado -mode batch -source xsim_run.tcl

# ================================================================
# Configuration
# ================================================================
set SRC_DIR   sync_rtl/ntt
set TB_DIR    sync_rtl/ntt/TB

# ================================================================
# Step 1: Compile all source files (xvlog)
# ================================================================
puts "=== Compiling RTL sources ==="

# Barrett modular multiplier (combinational)
xvlog -sv ${SRC_DIR}/barrett_mul.v

# Zeta ROM (combinational)
xvlog -sv ${SRC_DIR}/zeta_rom.v

# Butterfly unit (combinational, instantiates barrett_mul)
xvlog -sv ${SRC_DIR}/butterfly_unit.v

# NTT core (FSM-based, instantiates butterfly_unit + zeta_rom + barrett_mul)
xvlog -sv ${SRC_DIR}/ntt_core.v

# ================================================================
# Step 2: Compile testbench
# ================================================================
puts "=== Compiling testbench ==="

# File-based vector testbench for ntt_core
xvlog -sv ${TB_DIR}/tb_ntt_core_xsim.v

# ================================================================
# Step 3: Elaborate (xelab)
# ================================================================
puts "=== Elaborating snapshot ==="

xelab tb_ntt_core_xsim -s ntt_core_sim --timescale 1ns/1ps

# ================================================================
# Step 4: Run simulation
# ================================================================
puts ""
puts "=== Running ntt_core test ==="
xsim ntt_core_sim -R

puts ""
puts "=== Simulation complete ==="
