# NOTE: On some systems, you may need:
#   export LD_PRELOAD=/usr/lib64/libtinfo.so.5
# before running this script.

# xsim_run.tcl - Vivado xsim compilation and simulation script for mod_add_sync
#
# Compiles mod_add_sync RTL plus the file-based vector testbench and runs simulation.
# Run from the project root: ~/Dev/mlkem/
#
# Prerequisites:
#   source /opt/Xilinx/Vivado/2019.2/settings64.sh
#
# Usage:
#   vivado -mode batch -source sync_rtl/mod_add/TB/xsim_run.tcl
#
#   # Or step-by-step:
#   xvlog -sv sync_rtl/common/pipeline_reg.v
#   xvlog -sv sync_rtl/mod_add/mod_add_sync.v
#   xvlog -sv sync_rtl/mod_add/TB/tb_mod_add_xsim.v
#   xelab tb_mod_add_xsim -s tb_mod_add_xsim
#   xsim tb_mod_add_xsim -R

# ================================================================
# Configuration
# ================================================================
set SRC_DIR  sync_rtl/mod_add
set TB_DIR   sync_rtl/mod_add/TB
set COMMON_DIR sync_rtl/common

# ================================================================
# Step 1: Compile all source files (xvlog)
# ================================================================
puts "=== Compiling RTL sources ==="

# Common pipeline register
xvlog -sv -i . ${COMMON_DIR}/pipeline_reg.v

# mod_add_sync (includes defines.vh from common/)
xvlog -sv -i . ${SRC_DIR}/mod_add_sync.v

# ================================================================
# Step 2: Compile testbench
# ================================================================
puts "=== Compiling testbench ==="

# File-based vector testbench
xvlog -sv ${TB_DIR}/tb_mod_add_xsim.v

# ================================================================
# Step 3: Elaborate snapshot (xelab)
# ================================================================
puts "=== Elaborating snapshot ==="

xelab tb_mod_add_xsim -s tb_mod_add_xsim --timescale 1ns/1ps

# ================================================================
# Step 4: Run simulation
# ================================================================
puts "=== Running mod_add_sync file-based vector test ==="
xsim tb_mod_add_xsim -R

puts ""
puts "=== mod_add_sync simulation complete ==="
