54 lines
1.3 KiB
Verilog
54 lines
1.3 KiB
Verilog
module fpga_sram_dp #(
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parameter AW = 16,
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parameter Init_File = "none"
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)
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(
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input wire CLK,
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input wire [AW-1:0] ram_raddr,
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output wire [31 :0] ram_rdata,
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input wire ram_ren ,
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input wire [AW-1:0] ram_waddr,
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input wire [31 :0] ram_wdata,
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input wire [3 :0] ram_wen
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);
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localparam AWT = ((1<<(AW-0))-1);
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localparam V_STYLE = "block";
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localparam P_STYLE = (V_STYLE == "ultra") ? "uram" :
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(V_STYLE == "distributed") ? "select_ram" :
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"block_ram";
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(*ram_style = V_STYLE*)reg [31:0] BRAM [AWT:0]/*synthesis syn_ramstyle=P_STYLE*/;
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initial begin
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if(Init_File != "none") begin
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$readmemb(Init_File,BRAM);
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end
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end
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reg [AW-1:0] addr_q1;
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always@(posedge CLK) begin
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if(ram_wen[0]) BRAM[ram_waddr][7:0] <= ram_wdata[7:0];
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end
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always@(posedge CLK) begin
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if(ram_wen[1]) BRAM[ram_waddr][15:8] <= ram_wdata[15:8];
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end
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always@(posedge CLK) begin
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if(ram_wen[2]) BRAM[ram_waddr][23:16] <= ram_wdata[23:16];
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end
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always@(posedge CLK) begin
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if(ram_wen[3]) BRAM[ram_waddr][31:24] <= ram_wdata[31:24];
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end
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always @ (posedge CLK) begin
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if(ram_ren)
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addr_q1 <= ram_raddr;
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end
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assign ram_rdata = BRAM[addr_q1];
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endmodule
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