18 lines
276 B
Verilog
18 lines
276 B
Verilog
module rst_sync(
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input clk,
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input rst_n_in,
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output rst_n_out
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);
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reg [1:0] delay;
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always @(posedge clk or negedge rst_n_in) begin
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if(~rst_n_in) begin
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delay <= 2'b00;
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end
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else begin
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delay <= {delay[0],1'b1};
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end
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end
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assign rst_n_out = delay[1];
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endmodule |