194 lines
5.1 KiB
Verilog
194 lines
5.1 KiB
Verilog
/*------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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Copyright (c) 2016, Loongson Technology Corporation Limited.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation and/or
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other materials provided with the distribution.
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3. Neither the name of Loongson Technology Corporation Limited nor the names of
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its contributors may be used to endorse or promote products derived from this
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software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
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TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--------------------------------------------------------------------------------
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------------------------------------------------------------------------------*/
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`include "uart_defines.h"
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module uart_rfifo (clk,
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wb_rst_i, data_in, data_out,
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push,
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pop,
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overrun,
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count,
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error_bit,
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fifo_reset,
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reset_status
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);
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parameter fifo_width = `UART_FIFO_WIDTH;
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parameter fifo_depth = `UART_FIFO_DEPTH;
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parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
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parameter fifo_counter_w = `UART_FIFO_COUNTER_W;
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input clk;
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input wb_rst_i;
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input push;
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input pop;
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input [fifo_width-1:0] data_in;
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input fifo_reset;
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input reset_status;
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output [fifo_width-1:0] data_out;
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output overrun;
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output [fifo_counter_w-1:0] count;
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output error_bit;
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wire [fifo_width-1:0] data_out;
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wire [7:0] data8_out;
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reg [2:0] fifo[fifo_depth-1:0];
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reg [fifo_pointer_w-1:0] top;
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reg [fifo_pointer_w-1:0] bottom;
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reg [fifo_counter_w-1:0] count;
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reg overrun;
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wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1;
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raminfr #(fifo_pointer_w,8,fifo_depth) rfifo (.clk(clk),
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.we(push),
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.a(top),
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.dpra(bottom),
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.di(data_in[fifo_width-1:fifo_width-8]),
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.dpo(data8_out)
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);
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always @(posedge clk)
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begin
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if (wb_rst_i)
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begin
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top <= 0;
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bottom <= 1'b0;
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count <= 0;
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fifo[0] <= 0;
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fifo[1] <= 0;
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fifo[2] <= 0;
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fifo[3] <= 0;
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fifo[4] <= 0;
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fifo[5] <= 0;
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fifo[6] <= 0;
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fifo[7] <= 0;
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fifo[8] <= 0;
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fifo[9] <= 0;
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fifo[10]<= 0;
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fifo[11]<= 0;
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fifo[12]<= 0;
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fifo[13]<= 0;
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fifo[14]<= 0;
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fifo[15]<= 0;
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end
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else
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if (fifo_reset) begin
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top <= 0;
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bottom <= 1'b0;
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count <= 0;
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fifo[0] <= 0;
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fifo[1] <= 0;
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fifo[2] <= 0;
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fifo[3] <= 0;
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fifo[4] <= 0;
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fifo[5] <= 0;
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fifo[6] <= 0;
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fifo[7] <= 0;
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fifo[8] <= 0;
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fifo[9] <= 0;
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fifo[10]<= 0;
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fifo[11]<= 0;
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fifo[12]<= 0;
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fifo[13]<= 0;
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fifo[14]<= 0;
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fifo[15]<= 0;
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end
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else
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begin
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case ({push, pop})
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2'b10 : if (count<fifo_depth)
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begin
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top <= top_plus_1;
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fifo[top] <= data_in[2:0];
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count <= count + 1'b1;
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end
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2'b01 : if(count>0)
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begin
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fifo[bottom] <= 0;
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bottom <= bottom + 1'b1;
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count <= count - 1'b1;
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end
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2'b11 : begin
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bottom <= bottom + 1'b1;
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top <= top_plus_1;
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fifo[top] <= data_in[2:0];
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end
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default: ;
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endcase
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end
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end
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always @(posedge clk)
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begin
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if (wb_rst_i)
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overrun <= 1'b0;
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else
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if(fifo_reset | reset_status)
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overrun <= 1'b0;
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else
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if(push & ~pop & (count==fifo_depth))
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overrun <= 1'b1;
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end
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assign data_out = {data8_out,fifo[bottom]};
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wire [2:0] word0 = fifo[0];
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wire [2:0] word1 = fifo[1];
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wire [2:0] word2 = fifo[2];
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wire [2:0] word3 = fifo[3];
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wire [2:0] word4 = fifo[4];
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wire [2:0] word5 = fifo[5];
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wire [2:0] word6 = fifo[6];
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wire [2:0] word7 = fifo[7];
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wire [2:0] word8 = fifo[8];
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wire [2:0] word9 = fifo[9];
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wire [2:0] word10 = fifo[10];
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wire [2:0] word11 = fifo[11];
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wire [2:0] word12 = fifo[12];
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wire [2:0] word13 = fifo[13];
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wire [2:0] word14 = fifo[14];
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wire [2:0] word15 = fifo[15];
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assign error_bit = |(word0[2:0] | word1[2:0] | word2[2:0] | word3[2:0] |
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word4[2:0] | word5[2:0] | word6[2:0] | word7[2:0] |
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word8[2:0] | word9[2:0] | word10[2:0] | word11[2:0] |
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word12[2:0] | word13[2:0] | word14[2:0] | word15[2:0] );
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endmodule
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