378 lines
16 KiB
Systemverilog
378 lines
16 KiB
Systemverilog
// ============================================================================
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// snix_axil_cdma_mux.sv
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// Multi-Channel AXI-Lite MUX Wrapper for snix_axi_mm2mm engine
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//
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// Register Map (per channel, offset 0x40):
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// 0x00: READ_ADDR (Source Address)
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// 0x04: WRITE_ADDR (Destination Address)
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// 0x08: LENGTH (Transfer length in bytes)
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// 0x0C: TAG (User tag, purely for software tracking)
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// 0x10: CTRL (Write 1 to bit 0 to trigger)
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// [5:3] = AXI AxSIZE (0=1B, 1=2B, 2=4B, 3=8B...)
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// [13:6] = AXI AxLEN (0=1 beat, 15=16 beats...)
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// 0x14: STATUS (Bit 0: Busy RO, Bit 1: Done W1C)
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// ============================================================================
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`timescale 1ns / 1ps
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module snix_axil_cdma_mux #(
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parameter int ADDR_WIDTH = 32,
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parameter int DATA_WIDTH = 32, // Matches engine default
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parameter int AXIL_ADDR_WIDTH = 32,
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parameter int AXIL_DATA_WIDTH = 32,
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parameter int ID_WIDTH = 4,
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parameter int USER_WIDTH = 1,
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parameter int PORTS = 8,
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parameter int FIFO_DEPTH = 16
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) (
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input logic clk,
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input logic rst_n,
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// ==========================================
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// AXI-Lite Slave Interface (CPU CSR Access)
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// ==========================================
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input logic [AXIL_ADDR_WIDTH-1:0] s_axil_awaddr,
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input logic s_axil_awvalid,
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output logic s_axil_awready,
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input logic [AXIL_DATA_WIDTH-1:0] s_axil_wdata,
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input logic [AXIL_DATA_WIDTH/8-1:0] s_axil_wstrb,
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input logic s_axil_wvalid,
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output logic s_axil_wready,
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output logic [1:0] s_axil_bresp,
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output logic s_axil_bvalid,
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input logic s_axil_bready,
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input logic [AXIL_ADDR_WIDTH-1:0] s_axil_araddr,
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input logic s_axil_arvalid,
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output logic s_axil_arready,
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output logic [AXIL_DATA_WIDTH-1:0] s_axil_rdata,
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output logic [1:0] s_axil_rresp,
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output logic s_axil_rvalid,
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input logic s_axil_rready,
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// ==========================================
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// AXI4 Master Interface (To Crossbar/Memory)
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// ==========================================
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output logic [ID_WIDTH-1:0] mm2mm_awid,
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output logic [ADDR_WIDTH-1:0] mm2mm_awaddr,
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output logic [7:0] mm2mm_awlen,
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output logic [2:0] mm2mm_awsize,
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output logic [1:0] mm2mm_awburst,
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output logic mm2mm_awlock,
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output logic [3:0] mm2mm_awcache,
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output logic [2:0] mm2mm_awprot,
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output logic [3:0] mm2mm_awqos,
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output logic [USER_WIDTH-1:0] mm2mm_awuser,
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output logic mm2mm_awvalid,
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input logic mm2mm_awready,
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output logic [DATA_WIDTH-1:0] mm2mm_wdata,
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output logic [DATA_WIDTH/8-1:0] mm2mm_wstrb,
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output logic mm2mm_wlast,
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output logic [USER_WIDTH-1:0] mm2mm_wuser,
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output logic mm2mm_wvalid,
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input logic mm2mm_wready,
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input logic [ID_WIDTH-1:0] mm2mm_bid,
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input logic [1:0] mm2mm_bresp,
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input logic [USER_WIDTH-1:0] mm2mm_buser,
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input logic mm2mm_bvalid,
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output logic mm2mm_bready,
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output logic [ID_WIDTH-1:0] mm2mm_arid,
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output logic [ADDR_WIDTH-1:0] mm2mm_araddr,
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output logic [7:0] mm2mm_arlen,
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output logic [2:0] mm2mm_arsize,
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output logic [1:0] mm2mm_arburst,
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output logic mm2mm_arlock,
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output logic [3:0] mm2mm_arcache,
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output logic [2:0] mm2mm_arprot,
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output logic [3:0] mm2mm_arqos,
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output logic [USER_WIDTH-1:0] mm2mm_aruser,
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output logic mm2mm_arvalid,
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input logic mm2mm_arready,
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input logic [ID_WIDTH-1:0] mm2mm_rid,
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input logic [DATA_WIDTH-1:0] mm2mm_rdata,
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input logic [1:0] mm2mm_rresp,
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input logic mm2mm_rlast,
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input logic [USER_WIDTH-1:0] mm2mm_ruser,
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input logic mm2mm_rvalid,
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output logic mm2mm_rready,
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// Global Interrupt (OR'd from all channels)
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output logic dma_finish
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);
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// ==========================================
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// Local Parameters & Utilities
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// ==========================================
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localparam int CH_BITS = $clog2(PORTS);
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// Function to safely apply WSTRB to 32-bit registers
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function automatic logic [31:0] apply_wstrb(
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input logic [31:0] old_val,
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input logic [31:0] new_val,
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input logic [3:0] wstrb
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);
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logic [31:0] res;
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res[7:0] = wstrb[0] ? new_val[7:0] : old_val[7:0];
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res[15:8] = wstrb[1] ? new_val[15:8] : old_val[15:8];
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res[23:16] = wstrb[2] ? new_val[23:16] : old_val[23:16];
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res[31:24] = wstrb[3] ? new_val[31:24] : old_val[31:24];
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return res;
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endfunction
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// ==========================================
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// Internal Registers (Per Channel)
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// ==========================================
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logic [ADDR_WIDTH-1:0] ch_src_addr [PORTS];
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logic [ADDR_WIDTH-1:0] ch_dst_addr [PORTS];
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logic [31:0] ch_len [PORTS];
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logic [31:0] ch_tag [PORTS];
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logic [31:0] ch_ctrl [PORTS];
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logic [PORTS-1:0] ch_req; // Pending requests (Busy)
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logic [PORTS-1:0] ch_done; // Completion flags
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logic [PORTS-1:0] arb_set_done; // From Arbiter to CSR
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// ==========================================
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// Address Decoding (0x40 offset per channel)
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// ==========================================
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wire [CH_BITS-1:0] wr_ch = s_axil_awaddr[6 +: CH_BITS];
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wire [5:0] wr_reg = s_axil_awaddr[5:0];
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wire [CH_BITS-1:0] rd_ch = s_axil_araddr[6 +: CH_BITS];
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wire [5:0] rd_reg = s_axil_araddr[5:0];
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// ==========================================
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// AXI-Lite Slave Logic (Robust Backpressure)
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// ==========================================
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assign s_axil_bresp = 2'b00;
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assign s_axil_rresp = 2'b00;
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// Write Path Handshake
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always_ff @(posedge clk) begin
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if (!rst_n) begin
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s_axil_awready <= 1'b0;
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s_axil_wready <= 1'b0;
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end else begin
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if (s_axil_awvalid && s_axil_wvalid && !s_axil_awready && (!s_axil_bvalid || s_axil_bready)) begin
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s_axil_awready <= 1'b1;
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s_axil_wready <= 1'b1;
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end else begin
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s_axil_awready <= 1'b0;
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s_axil_wready <= 1'b0;
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end
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end
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end
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wire do_write = s_axil_awready && s_axil_awvalid && s_axil_wready && s_axil_wvalid;
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always_ff @(posedge clk) begin
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if (!rst_n) begin
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s_axil_bvalid <= 1'b0;
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end else begin
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if (do_write) begin
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s_axil_bvalid <= 1'b1;
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end else if (s_axil_bready && s_axil_bvalid) begin
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s_axil_bvalid <= 1'b0;
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end
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end
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end
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// Read Path Handshake
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always_ff @(posedge clk) begin
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if (!rst_n) begin
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s_axil_arready <= 1'b0;
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end else begin
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if (s_axil_arvalid && !s_axil_arready && (!s_axil_rvalid || s_axil_rready)) begin
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s_axil_arready <= 1'b1;
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end else begin
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s_axil_arready <= 1'b0;
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end
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end
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end
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wire do_read = s_axil_arready && s_axil_arvalid;
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always_ff @(posedge clk) begin
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if (!rst_n) begin
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s_axil_rvalid <= 1'b0;
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s_axil_rdata <= '0;
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end else begin
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if (do_read) begin
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s_axil_rvalid <= 1'b1;
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if (rd_ch < PORTS) begin
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case (rd_reg)
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6'h00: s_axil_rdata <= ch_src_addr[rd_ch];
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6'h04: s_axil_rdata <= ch_dst_addr[rd_ch];
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6'h08: s_axil_rdata <= ch_len[rd_ch];
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6'h0C: s_axil_rdata <= ch_tag[rd_ch];
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6'h10: s_axil_rdata <= ch_ctrl[rd_ch];
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6'h14: s_axil_rdata <= {30'd0, ch_done[rd_ch], ch_req[rd_ch]};
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default: s_axil_rdata <= 32'd0;
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endcase
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end else begin
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s_axil_rdata <= 32'd0; // Out of bounds
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end
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end else if (s_axil_rready && s_axil_rvalid) begin
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s_axil_rvalid <= 1'b0;
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end
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end
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end
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// ==========================================
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// Register File Write Logic
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// ==========================================
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assign dma_finish = |ch_done;
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always_ff @(posedge clk) begin
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if (!rst_n) begin
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ch_req <= '0;
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ch_done <= '0;
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for (int i=0; i<PORTS; i++) begin
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ch_src_addr[i] <= '0; ch_dst_addr[i] <= '0;
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ch_len[i] <= '0; ch_tag[i] <= '0; ch_ctrl[i] <= '0;
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end
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end else begin
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// 1. Process Hardware Status Updates (Highest Priority for Done flag)
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for (int i=0; i<PORTS; i++) begin
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if (arb_set_done[i]) begin
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ch_req[i] <= 1'b0;
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ch_done[i] <= 1'b1;
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end
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end
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// 2. Process CPU Writes
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if (do_write && wr_ch < PORTS) begin
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case (wr_reg)
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6'h00: if (!ch_req[wr_ch]) ch_src_addr[wr_ch] <= apply_wstrb(ch_src_addr[wr_ch], s_axil_wdata, s_axil_wstrb);
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6'h04: if (!ch_req[wr_ch]) ch_dst_addr[wr_ch] <= apply_wstrb(ch_dst_addr[wr_ch], s_axil_wdata, s_axil_wstrb);
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6'h08: if (!ch_req[wr_ch]) ch_len[wr_ch] <= apply_wstrb(ch_len[wr_ch], s_axil_wdata, s_axil_wstrb);
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6'h0C: if (!ch_req[wr_ch]) ch_tag[wr_ch] <= apply_wstrb(ch_tag[wr_ch], s_axil_wdata, s_axil_wstrb);
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6'h10: begin
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ch_ctrl[wr_ch] <= apply_wstrb(ch_ctrl[wr_ch], s_axil_wdata, s_axil_wstrb);
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// Trigger Bit Processing
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if (s_axil_wstrb[0] && s_axil_wdata[0]) begin
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ch_req[wr_ch] <= 1'b1;
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// Clean up done bit automatically upon new start
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if (!arb_set_done[wr_ch]) ch_done[wr_ch] <= 1'b0;
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end
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end
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6'h14: begin
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// Software W1C for Done flag (Bit 1)
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// ONLY clear if hardware is not setting it in the exact same cycle
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if (s_axil_wstrb[0] && s_axil_wdata[1]) begin
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if (!arb_set_done[wr_ch]) ch_done[wr_ch] <= 1'b0;
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end
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end
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endcase
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end
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end
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end
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// ==========================================
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// Round-Robin Arbiter & Engine Driver
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// ==========================================
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typedef enum logic [1:0] {IDLE, RUN} state_t;
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state_t state;
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logic [CH_BITS-1:0] cur_ch;
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logic [CH_BITS-1:0] rr_ptr;
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// Interfaces to Engine
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logic engine_start;
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logic [ADDR_WIDTH-1:0] engine_src;
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logic [ADDR_WIDTH-1:0] engine_dst;
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logic [31:0] engine_bytes;
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logic [7:0] engine_len;
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logic [2:0] engine_size;
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logic engine_done;
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// Dynamic routing to the engine based on current active channel
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assign engine_src = ch_src_addr[cur_ch];
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assign engine_dst = ch_dst_addr[cur_ch];
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assign engine_bytes = ch_len[cur_ch];
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assign engine_len = ch_ctrl[cur_ch][13:6];
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assign engine_size = ch_ctrl[cur_ch][5:3];
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always_ff @(posedge clk) begin
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if (!rst_n) begin
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state <= IDLE;
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engine_start <= 1'b0;
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rr_ptr <= '0;
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cur_ch <= '0;
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arb_set_done <= '0;
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end else begin
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arb_set_done <= '0;
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engine_start <= 1'b0;
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case (state)
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IDLE: begin
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for (int i = 0; i < PORTS; i++) begin
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// Calculate next channel safely avoiding modulo operators in loop
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logic [CH_BITS:0] check_ch_ext = {1'b0, rr_ptr} + i[CH_BITS:0];
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logic [CH_BITS-1:0] check_ch = (check_ch_ext >= PORTS) ? (check_ch_ext - PORTS) : check_ch_ext[CH_BITS-1:0];
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if (ch_req[check_ch] && !arb_set_done[check_ch]) begin
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cur_ch <= check_ch;
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rr_ptr <= (check_ch == (PORTS - 1)) ? '0 : (check_ch + 1);
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engine_start <= 1'b1;
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state <= RUN;
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break;
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end
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end
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end
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RUN: begin
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if (engine_done) begin
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arb_set_done[cur_ch] <= 1'b1;
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state <= IDLE;
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end
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// Optional: Add a watchdog timeout counter here if dealing with untrusted PCIe/AXI endpoints
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end
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endcase
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end
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end
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// ==========================================
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// Instantiate The Original Core Engine
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// ==========================================
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snix_axi_mm2mm #(
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.ADDR_WIDTH(ADDR_WIDTH),
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.DATA_WIDTH(DATA_WIDTH),
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.ID_WIDTH (ID_WIDTH),
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.USER_WIDTH(USER_WIDTH),
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.FIFO_DEPTH(FIFO_DEPTH)
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) u_core_engine (
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.clk (clk),
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.rst_n (rst_n),
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.ctrl_start (engine_start),
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.ctrl_stop (1'b0), // Tied off; can be wired if global abort is needed
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.ctrl_src_addr (engine_src),
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.ctrl_dst_addr (engine_dst),
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.ctrl_len (engine_len),
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.ctrl_size (engine_size),
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.ctrl_transfer_len (engine_bytes),
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.ctrl_done (engine_done),
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// AXI4 Port Connections
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.mm2mm_awid (mm2mm_awid), .mm2mm_awaddr (mm2mm_awaddr),
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.mm2mm_awlen (mm2mm_awlen), .mm2mm_awsize (mm2mm_awsize),
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.mm2mm_awburst(mm2mm_awburst),.mm2mm_awlock (mm2mm_awlock),
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.mm2mm_awcache(mm2mm_awcache),.mm2mm_awprot (mm2mm_awprot),
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.mm2mm_awqos (mm2mm_awqos), .mm2mm_awuser (mm2mm_awuser),
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.mm2mm_awvalid(mm2mm_awvalid),.mm2mm_awready(mm2mm_awready),
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.mm2mm_wdata (mm2mm_wdata), .mm2mm_wstrb (mm2mm_wstrb),
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.mm2mm_wlast (mm2mm_wlast), .mm2mm_wuser (mm2mm_wuser),
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.mm2mm_wvalid (mm2mm_wvalid), .mm2mm_wready (mm2mm_wready),
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.mm2mm_bid (mm2mm_bid), .mm2mm_bresp (mm2mm_bresp),
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.mm2mm_buser (mm2mm_buser), .mm2mm_bvalid (mm2mm_bvalid),
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.mm2mm_bready (mm2mm_bready),
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.mm2mm_arid (mm2mm_arid), .mm2mm_araddr (mm2mm_araddr),
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.mm2mm_arlen (mm2mm_arlen), .mm2mm_arsize (mm2mm_arsize),
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.mm2mm_arburst(mm2mm_arburst),.mm2mm_arlock (mm2mm_arlock),
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.mm2mm_arcache(mm2mm_arcache),.mm2mm_arprot (mm2mm_arprot),
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.mm2mm_arqos (mm2mm_arqos), .mm2mm_aruser (mm2mm_aruser),
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.mm2mm_arvalid(mm2mm_arvalid),.mm2mm_arready(mm2mm_arready),
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.mm2mm_rid (mm2mm_rid), .mm2mm_rdata (mm2mm_rdata),
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.mm2mm_rresp (mm2mm_rresp), .mm2mm_rlast (mm2mm_rlast),
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.mm2mm_ruser (mm2mm_ruser), .mm2mm_rvalid (mm2mm_rvalid),
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.mm2mm_rready (mm2mm_rready)
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);
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endmodule |