521 lines
20 KiB
Verilog
521 lines
20 KiB
Verilog
//+FHDR-----------------------------------------------------------------
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// (C) Copyright Loongson Technology Corporation Limited. All rights reserved
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// Loongson Confidential Proprietary
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//-FHDR-----------------------------------------------------------------
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module axi2sram_dp#(
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parameter BUS_WIDTH = 32,
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parameter DATA_WIDTH = 64,
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parameter CPU_WIDTH = 32
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)
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(
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input wire aclk ,
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input wire aresetn ,
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output wire [BUS_WIDTH-1 :0] ram_raddr,
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input wire [DATA_WIDTH-1 :0] ram_rdata,
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output wire ram_ren ,
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output wire [BUS_WIDTH-1 :0] ram_waddr,
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output wire [DATA_WIDTH-1 :0] ram_wdata,
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output wire [DATA_WIDTH/8-1 :0] ram_wen ,
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input wire [BUS_WIDTH-1 :0] m_araddr ,
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input wire [1 :0] m_arburst,
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input wire [3 :0] m_arcache,
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input wire [4 :0] m_arid ,
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input wire [3 :0] m_arlen ,
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input wire [1 :0] m_arlock ,
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input wire [2 :0] m_arprot ,
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output wire m_arready,
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input wire [2 :0] m_arsize ,
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input wire m_arvalid,
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input wire [BUS_WIDTH-1 :0] m_awaddr ,
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input wire [1 :0] m_awburst,
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input wire [3 :0] m_awcache,
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input wire [4 :0] m_awid ,
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input wire [3 :0] m_awlen ,
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input wire [1 :0] m_awlock ,
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input wire [2 :0] m_awprot ,
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output wire m_awready,
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input wire [2 :0] m_awsize ,
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input wire m_awvalid,
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output wire [4 :0] m_bid ,
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input wire m_bready ,
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output wire [1 :0] m_bresp ,
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output wire m_bvalid ,
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output wire [DATA_WIDTH-1 :0] m_rdata ,
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output wire [4 :0] m_rid ,
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output wire m_rlast ,
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input wire m_rready ,
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output wire [1 :0] m_rresp ,
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output wire m_rvalid ,
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input wire [DATA_WIDTH-1 :0] m_wdata ,
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input wire m_wlast ,
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output wire m_wready ,
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input wire [DATA_WIDTH/8-1 :0] m_wstrb ,
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input wire m_wvalid
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);
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localparam ADDR_INCR_BASE=($clog2(DATA_WIDTH) - 3);
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wire [BUS_WIDTH+13-1 :0] ram_r_a_data ;
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reg [BUS_WIDTH-1 :0] ram_r_a_data_araddr ;
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wire [BUS_WIDTH-1 :0] ram_r_a_data_araddr_fixed ;
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wire [BUS_WIDTH-1 :0] ram_r_a_data_araddr_incr ;
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wire [BUS_WIDTH-1 :0] ram_r_a_data_araddr_next ;
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wire ram_r_a_data_araddr_update ;
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wire [BUS_WIDTH-1 :0] ram_r_a_data_araddr_wrap ;
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reg [1 :0] ram_r_a_data_arburst ;
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wire ram_r_a_data_arburst_fixed ;
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wire ram_r_a_data_arburst_incr ;
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wire ram_r_a_data_arburst_wrap ;
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reg [4 :0] ram_r_a_data_arid ;
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reg [3 :0] ram_r_a_data_arlen ;
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wire ram_r_a_data_arlen_last ;
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reg [2 :0] ram_r_a_data_arsize ;
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wire ram_r_a_data_push ;
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wire ram_r_a_full ;
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wire ram_r_a_pop ;
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wire ram_r_a_push ;
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wire [BUS_WIDTH+14-1 :0] ram_r_a_push_data ;
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reg [BUS_WIDTH+14-1 :0] ram_r_a_queue_datas ;
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wire [BUS_WIDTH-1 :0] ram_r_a_queue_datas_araddr ;
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wire [1 :0] ram_r_a_queue_datas_arburst;
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wire [4 :0] ram_r_a_queue_datas_arid ;
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wire [3 :0] ram_r_a_queue_datas_arlen ;
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wire [2 :0] ram_r_a_queue_datas_arsize ;
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wire ram_r_a_queue_empty ;
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wire ram_r_a_queue_full ;
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wire ram_r_a_queue_pop ;
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wire ram_r_a_queue_push ;
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reg ram_r_a_queue_valid ;
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reg ram_r_a_valid ;
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wire [BUS_WIDTH-1 :0] ram_r_addr ;
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wire ram_r_allow_out ;
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wire [DATA_WIDTH-1 :0] ram_r_data ;
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wire ram_r_en ;
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reg [3 :0] ram_r_rcur ;
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wire ram_r_rcur_reset ;
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reg [4 :0] ram_r_rid ;
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reg ram_r_rlast ;
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reg ram_r_rvalid ;
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wire [BUS_WIDTH+13-1 :0] ram_w_a_data ;
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reg [BUS_WIDTH-1 :0] ram_w_a_data_awaddr ;
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wire [BUS_WIDTH-1 :0] ram_w_a_data_awaddr_fixed ;
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wire [BUS_WIDTH-1 :0] ram_w_a_data_awaddr_incr ;
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wire [BUS_WIDTH-1 :0] ram_w_a_data_awaddr_next ;
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wire ram_w_a_data_awaddr_update ;
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wire [BUS_WIDTH-1 :0] ram_w_a_data_awaddr_wrap ;
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reg [1 :0] ram_w_a_data_awburst ;
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wire ram_w_a_data_awburst_fixed ;
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wire ram_w_a_data_awburst_incr ;
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wire ram_w_a_data_awburst_wrap ;
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reg [4 :0] ram_w_a_data_awid ;
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reg [3 :0] ram_w_a_data_awlen ;
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reg [2 :0] ram_w_a_data_awsize ;
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wire ram_w_a_data_push ;
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wire ram_w_a_full ;
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wire ram_w_a_pop ;
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wire ram_w_a_push ;
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wire [BUS_WIDTH+14-1 :0] ram_w_a_push_data ;
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reg [BUS_WIDTH+14-1 :0] ram_w_a_queue_datas ;
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wire [BUS_WIDTH-1 :0] ram_w_a_queue_datas_awaddr ;
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wire [1 :0] ram_w_a_queue_datas_awburst;
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wire [4 :0] ram_w_a_queue_datas_awid ;
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wire [3 :0] ram_w_a_queue_datas_awlen ;
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wire [2 :0] ram_w_a_queue_datas_awsize ;
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wire ram_w_a_queue_empty ;
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wire ram_w_a_queue_full ;
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wire ram_w_a_queue_pop ;
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wire ram_w_a_queue_push ;
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reg ram_w_a_queue_valid ;
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reg ram_w_a_valid ;
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wire [BUS_WIDTH-1 :0] ram_w_addr ;
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wire ram_w_allow_out ;
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reg [4 :0] ram_w_b_data ;
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wire ram_w_b_data_push ;
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wire ram_w_b_full ;
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wire ram_w_b_pop ;
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wire ram_w_b_push ;
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reg [4 :0] ram_w_b_queue_datas ;
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wire ram_w_b_queue_empty ;
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wire ram_w_b_queue_full ;
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wire ram_w_b_queue_pop ;
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wire ram_w_b_queue_push ;
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reg ram_w_b_queue_valid ;
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reg ram_w_b_valid ;
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wire ram_w_en ;
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wire ram_w_go ;
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wire [DATA_WIDTH/8-1 :0] ram_w_strb ;
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reg [DATA_WIDTH-1 :0] ram_w_wdata ;
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reg ram_w_wlast ;
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reg [DATA_WIDTH/8-1 :0] ram_w_wstrb ;
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reg ram_w_wvalid ;
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assign m_arready = !ram_r_a_full;
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assign m_awready = !ram_w_a_full;
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assign m_bid = ram_w_b_data;
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assign m_bresp = 2'h0;
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assign m_bvalid = ram_w_b_valid;
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assign m_rdata = ram_rdata ;
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assign m_rid = ram_r_rid ;
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assign m_rlast = ram_r_rlast ;
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assign m_rresp = 2'h0;
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assign m_rvalid = ram_r_rvalid;
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assign m_wready = ram_w_allow_out || !ram_w_wvalid;
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assign ram_r_a_data = {ram_r_a_data_arburst,ram_r_a_data_arsize,ram_r_a_data_arlen,ram_r_a_data_araddr,ram_r_a_data_arid};
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assign ram_r_a_data_araddr_fixed = ram_r_a_data_araddr;
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assign ram_r_a_data_araddr_incr [ADDR_INCR_BASE-1:0] = ram_r_a_data_araddr[ADDR_INCR_BASE-1:0];
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assign ram_r_a_data_araddr_incr [BUS_WIDTH-1 :ADDR_INCR_BASE ] = ram_r_a_data_araddr[BUS_WIDTH-1:ADDR_INCR_BASE] + {{BUS_WIDTH-ADDR_INCR_BASE-1{1'b0}},1'b1};
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assign ram_r_a_data_araddr_next = {BUS_WIDTH{ram_r_a_data_arburst_fixed}} & ram_r_a_data_araddr_fixed
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| {BUS_WIDTH{ram_r_a_data_arburst_incr }} & ram_r_a_data_araddr_incr
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| {BUS_WIDTH{ram_r_a_data_arburst_wrap }} & ram_r_a_data_araddr_wrap ;
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assign ram_r_a_data_araddr_update = ram_r_en && !ram_r_a_data_arlen_last;
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assign ram_r_a_data_araddr_wrap [ADDR_INCR_BASE-1 :0] = ram_r_a_data_araddr[ADDR_INCR_BASE-1 :0];
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assign ram_r_a_data_araddr_wrap [BUS_WIDTH-1:ADDR_INCR_BASE+4] = ram_r_a_data_araddr[BUS_WIDTH-1:ADDR_INCR_BASE+4];
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assign ram_r_a_data_araddr_wrap [ADDR_INCR_BASE+3 :ADDR_INCR_BASE] = ram_r_a_data_araddr[ADDR_INCR_BASE+3:ADDR_INCR_BASE] & ~ram_r_a_data_arlen | ram_r_a_data_arlen & ram_r_a_data_araddr[ADDR_INCR_BASE+3:ADDR_INCR_BASE] + 4'h1;
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assign ram_r_a_data_arburst_fixed = ram_r_a_data_arburst == 2'h0;
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assign ram_r_a_data_arburst_incr = ram_r_a_data_arburst == 2'h1;
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assign ram_r_a_data_arburst_wrap = ram_r_a_data_arburst == 2'h2;
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assign ram_r_a_data_arlen_last = ram_r_a_data_arlen == ram_r_rcur;
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assign ram_r_a_data_push = ram_r_a_push && (ram_r_a_pop || !ram_r_a_valid);
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assign ram_r_a_full = ram_r_a_queue_full;
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assign ram_r_a_pop = ram_r_en && ram_r_a_data_arlen_last;
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assign ram_r_a_push = m_arvalid && !ram_r_a_full ;
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//assign ram_r_a_push_data = {m_arburst,m_arsize ,m_arlen,m_araddr,m_arid};
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assign ram_r_a_push_data = {m_araddr,m_arburst,m_arsize,m_arlen,m_arid};
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assign ram_r_a_queue_datas_araddr = ram_r_a_queue_datas[BUS_WIDTH-1+14:14];
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assign ram_r_a_queue_datas_arburst = ram_r_a_queue_datas[13 :12];
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assign ram_r_a_queue_datas_arid = ram_r_a_queue_datas[4 : 0];
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assign ram_r_a_queue_datas_arlen = ram_r_a_queue_datas[8 : 5];
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assign ram_r_a_queue_datas_arsize = ram_r_a_queue_datas[11 : 9];
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assign ram_r_a_queue_empty = !ram_r_a_queue_valid;
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assign ram_r_a_queue_full = ram_r_a_queue_valid;
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assign ram_r_a_queue_pop = ram_r_a_pop && !ram_r_a_queue_empty;
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assign ram_r_a_queue_push = ram_r_a_push && ram_r_a_valid && !ram_r_a_pop && !ram_r_a_queue_full;
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assign ram_r_addr = ram_r_a_data_araddr;
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assign ram_r_allow_out = m_rready || !m_rvalid;
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assign ram_r_data = ram_rdata;
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assign ram_r_en = ram_r_a_valid && ram_r_allow_out;
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assign ram_r_rcur_reset = !aresetn || ram_r_a_pop;
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assign ram_w_a_data = {ram_w_a_data_awaddr,ram_w_a_data_awburst,ram_w_a_data_awsize ,ram_w_a_data_awlen,ram_w_a_data_awid};
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assign ram_w_a_data_awaddr_fixed = ram_w_a_data_awaddr;
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assign ram_w_a_data_awaddr_incr [ADDR_INCR_BASE-1 :0] = ram_w_a_data_awaddr[ADDR_INCR_BASE-1:0];
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assign ram_w_a_data_awaddr_incr [BUS_WIDTH-1:ADDR_INCR_BASE] = ram_w_a_data_awaddr[BUS_WIDTH-1:ADDR_INCR_BASE] + {{BUS_WIDTH-ADDR_INCR_BASE-1{1'b0}},1'b1};
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assign ram_w_a_data_awaddr_next = {BUS_WIDTH{ram_w_a_data_awburst_fixed}} & ram_w_a_data_awaddr_fixed
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| {BUS_WIDTH{ram_w_a_data_awburst_incr }} & ram_w_a_data_awaddr_incr
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| {BUS_WIDTH{ram_w_a_data_awburst_wrap }} & ram_w_a_data_awaddr_wrap ;
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assign ram_w_a_data_awaddr_update = ram_w_en && !ram_w_wlast;
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assign ram_w_a_data_awaddr_wrap [ADDR_INCR_BASE-1 :0] = ram_w_a_data_awaddr[ADDR_INCR_BASE-1 :0];
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assign ram_w_a_data_awaddr_wrap [BUS_WIDTH-1:ADDR_INCR_BASE+4] = ram_w_a_data_awaddr[BUS_WIDTH-1:ADDR_INCR_BASE+4];
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assign ram_w_a_data_awaddr_wrap [ADDR_INCR_BASE+3:ADDR_INCR_BASE] = ram_w_a_data_awaddr[ADDR_INCR_BASE+3:ADDR_INCR_BASE] & ~ram_w_a_data_awlen | ram_w_a_data_awlen & ram_w_a_data_awaddr[ADDR_INCR_BASE+3:ADDR_INCR_BASE] + 4'h1;
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assign ram_w_a_data_awburst_fixed = ram_w_a_data_awburst == 2'h0;
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assign ram_w_a_data_awburst_incr = ram_w_a_data_awburst == 2'h1;
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assign ram_w_a_data_awburst_wrap = ram_w_a_data_awburst == 2'h2;
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assign ram_w_a_data_push = ram_w_a_push && (ram_w_a_pop || !ram_w_a_valid);
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assign ram_w_a_full = ram_w_a_queue_full;
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assign ram_w_a_pop = ram_w_en && ram_w_wlast ;
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assign ram_w_a_push = m_awvalid && !ram_w_a_full;
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assign ram_w_a_push_data = {m_awaddr,m_awburst,m_awsize ,m_awlen,m_awid};
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assign ram_w_a_queue_datas_awaddr = ram_w_a_queue_datas[BUS_WIDTH-1+14:14];
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assign ram_w_a_queue_datas_awburst = ram_w_a_queue_datas[13 :12];
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assign ram_w_a_queue_datas_awid = ram_w_a_queue_datas[4 : 0];
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assign ram_w_a_queue_datas_awlen = ram_w_a_queue_datas[8 : 5];
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assign ram_w_a_queue_datas_awsize = ram_w_a_queue_datas[11 : 9];
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assign ram_w_a_queue_empty = !ram_w_a_queue_valid;
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assign ram_w_a_queue_full = ram_w_a_queue_valid;
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assign ram_w_a_queue_pop = ram_w_a_pop && !ram_w_a_queue_empty;
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assign ram_w_a_queue_push = ram_w_a_push && ram_w_a_valid && !ram_w_a_pop && !ram_w_a_queue_full;
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assign ram_w_addr = ram_w_a_data_awaddr;
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assign ram_w_allow_out = ram_w_a_valid && !ram_w_b_full;
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assign ram_w_b_data_push = ram_w_b_push && (ram_w_b_pop || !ram_w_b_valid);
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assign ram_w_b_full = ram_w_b_queue_full;
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assign ram_w_b_pop = m_bready && ram_w_b_valid;
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assign ram_w_b_push = ram_w_a_pop ;
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assign ram_w_b_queue_empty = !ram_w_b_queue_valid;
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assign ram_w_b_queue_full = ram_w_b_queue_valid;
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assign ram_w_b_queue_pop = ram_w_b_pop && !ram_w_b_queue_empty;
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assign ram_w_b_queue_push = ram_w_b_push && ram_w_b_valid && !ram_w_b_pop && !ram_w_b_queue_full;
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assign ram_w_en = ram_w_wvalid && ram_w_allow_out && aresetn;
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assign ram_w_go = m_wvalid && m_wready;
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assign ram_w_strb = ram_w_wstrb;
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assign ram_raddr = ram_r_addr ;
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assign ram_ren = ram_r_en ;
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assign ram_waddr = ram_w_addr ;
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assign ram_wdata = ram_w_wdata;
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assign ram_wen = ram_w_strb & {DATA_WIDTH/8{ram_w_en}};
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always@(posedge aclk)
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begin
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if(ram_r_rcur_reset)
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begin
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ram_r_rcur<=4'h0;
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end
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else
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if(ram_r_en)
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begin
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ram_r_rcur<=ram_r_rcur + 4'h1;
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end
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end
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always@(posedge aclk)
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begin
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if(ram_r_en)
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begin
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ram_r_rid<=ram_r_a_data_arid;
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end
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end
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always@(posedge aclk)
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begin
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if(ram_r_en)
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begin
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ram_r_rlast<=ram_r_a_data_arlen_last;
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end
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end
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always@(posedge aclk)
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begin
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if(!aresetn)
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begin
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ram_r_rvalid<=1'h0;
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end
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else
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if(ram_r_en)
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begin
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ram_r_rvalid<=1'h1;
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end
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else
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if(m_rready)
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begin
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ram_r_rvalid<=1'h0;
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end
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end
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always@(posedge aclk)
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begin
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if(!aresetn)
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begin
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ram_r_a_valid<=1'h0;
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end
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else
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if(ram_r_a_push)
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begin
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ram_r_a_valid<=1'h1;
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end
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else
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if(ram_r_a_pop)
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begin
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ram_r_a_valid<=ram_r_a_queue_valid;
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end
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end
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always@(posedge aclk)
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begin
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if(!aresetn)
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begin
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ram_r_a_queue_valid<=1'h0;
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end
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else
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if(ram_r_a_queue_push)
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begin
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ram_r_a_queue_valid<=1'h1;
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end
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else
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if(ram_r_a_queue_pop)
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begin
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ram_r_a_queue_valid<=1'h0;
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end
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end
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always@(posedge aclk)
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begin
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if(ram_r_a_queue_push)
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begin
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ram_r_a_queue_datas<=ram_r_a_push_data;
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end
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end
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always@(posedge aclk)
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begin
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if(ram_r_a_data_push)
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begin
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ram_r_a_data_arburst<=m_arburst;
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ram_r_a_data_arid <=m_arid ;
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ram_r_a_data_arlen <=m_arlen ;
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ram_r_a_data_arsize <=m_arsize ;
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end
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else
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if(ram_r_a_pop)
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begin
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ram_r_a_data_arburst<=ram_r_a_queue_datas_arburst;
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ram_r_a_data_arid <=ram_r_a_queue_datas_arid ;
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ram_r_a_data_arlen <=ram_r_a_queue_datas_arlen ;
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ram_r_a_data_arsize <=ram_r_a_queue_datas_arsize ;
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end
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|
end
|
|
always@(posedge aclk)
|
|
begin
|
|
if(ram_r_a_data_push)
|
|
begin
|
|
ram_r_a_data_araddr<=m_araddr;
|
|
end
|
|
else
|
|
if(ram_r_a_pop)
|
|
begin
|
|
ram_r_a_data_araddr<=ram_r_a_queue_datas_araddr;
|
|
end
|
|
else
|
|
begin
|
|
if(ram_r_a_data_araddr_update)
|
|
begin
|
|
ram_r_a_data_araddr<=ram_r_a_data_araddr_next;
|
|
end
|
|
end
|
|
end
|
|
always@(posedge aclk)
|
|
begin
|
|
if(ram_w_go)
|
|
begin
|
|
ram_w_wdata<=m_wdata;
|
|
ram_w_wlast<=m_wlast;
|
|
ram_w_wstrb<=m_wstrb;
|
|
end
|
|
end
|
|
always@(posedge aclk)
|
|
begin
|
|
if(!aresetn)
|
|
begin
|
|
ram_w_wvalid<=1'h0;
|
|
end
|
|
else
|
|
if(ram_w_go)
|
|
begin
|
|
ram_w_wvalid<=1'h1;
|
|
end
|
|
else
|
|
if(ram_w_en)
|
|
begin
|
|
ram_w_wvalid<=1'h0;
|
|
end
|
|
end
|
|
always@(posedge aclk)
|
|
begin
|
|
if(!aresetn)
|
|
begin
|
|
ram_w_a_valid<=1'h0;
|
|
end
|
|
else
|
|
if(ram_w_a_push)
|
|
begin
|
|
ram_w_a_valid<=1'h1;
|
|
end
|
|
else
|
|
if(ram_w_a_pop)
|
|
begin
|
|
ram_w_a_valid<=ram_w_a_queue_valid;
|
|
end
|
|
end
|
|
always@(posedge aclk)
|
|
begin
|
|
if(!aresetn)
|
|
begin
|
|
ram_w_a_queue_valid<=1'h0;
|
|
end
|
|
else
|
|
if(ram_w_a_queue_push)
|
|
begin
|
|
ram_w_a_queue_valid<=1'h1;
|
|
end
|
|
else
|
|
if(ram_w_a_queue_pop)
|
|
begin
|
|
ram_w_a_queue_valid<=1'h0;
|
|
end
|
|
end
|
|
always@(posedge aclk)
|
|
begin
|
|
if(ram_w_a_queue_push)
|
|
begin
|
|
ram_w_a_queue_datas<=ram_w_a_push_data;
|
|
end
|
|
end
|
|
always@(posedge aclk)
|
|
begin
|
|
if(ram_w_a_data_push)
|
|
begin
|
|
ram_w_a_data_awburst<=m_awburst;
|
|
ram_w_a_data_awid <=m_awid ;
|
|
ram_w_a_data_awlen <=m_awlen ;
|
|
ram_w_a_data_awsize <=m_awsize ;
|
|
end
|
|
else
|
|
if(ram_w_a_pop)
|
|
begin
|
|
ram_w_a_data_awburst<=ram_w_a_queue_datas_awburst;
|
|
ram_w_a_data_awid <=ram_w_a_queue_datas_awid ;
|
|
ram_w_a_data_awlen <=ram_w_a_queue_datas_awlen ;
|
|
ram_w_a_data_awsize <=ram_w_a_queue_datas_awsize ;
|
|
end
|
|
end
|
|
always@(posedge aclk)
|
|
begin
|
|
if(ram_w_a_data_push)
|
|
begin
|
|
ram_w_a_data_awaddr<=m_awaddr;
|
|
end
|
|
else
|
|
if(ram_w_a_pop)
|
|
begin
|
|
ram_w_a_data_awaddr<=ram_w_a_queue_datas_awaddr;
|
|
end
|
|
else
|
|
begin
|
|
if(ram_w_a_data_awaddr_update)
|
|
begin
|
|
ram_w_a_data_awaddr<=ram_w_a_data_awaddr_next;
|
|
end
|
|
end
|
|
end
|
|
always@(posedge aclk)
|
|
begin
|
|
if(!aresetn)
|
|
begin
|
|
ram_w_b_valid<=1'h0;
|
|
end
|
|
else
|
|
if(ram_w_b_push)
|
|
begin
|
|
ram_w_b_valid<=1'h1;
|
|
end
|
|
else
|
|
if(ram_w_b_pop)
|
|
begin
|
|
ram_w_b_valid<=ram_w_b_queue_valid;
|
|
end
|
|
end
|
|
always@(posedge aclk)
|
|
begin
|
|
if(!aresetn)
|
|
begin
|
|
ram_w_b_queue_valid<=1'h0;
|
|
end
|
|
else
|
|
if(ram_w_b_queue_push)
|
|
begin
|
|
ram_w_b_queue_valid<=1'h1;
|
|
end
|
|
else
|
|
if(ram_w_b_queue_pop)
|
|
begin
|
|
ram_w_b_queue_valid<=1'h0;
|
|
end
|
|
end
|
|
always@(posedge aclk)
|
|
begin
|
|
if(ram_w_b_queue_push)
|
|
begin
|
|
ram_w_b_queue_datas<=ram_w_a_data_awid;
|
|
end
|
|
end
|
|
always@(posedge aclk)
|
|
begin
|
|
if(ram_w_b_data_push)
|
|
begin
|
|
ram_w_b_data<=ram_w_a_data_awid;
|
|
end
|
|
else
|
|
if(ram_w_b_pop)
|
|
begin
|
|
ram_w_b_data<=ram_w_b_queue_datas;
|
|
end
|
|
end
|
|
endmodule // soc_axi_sram_bridge
|