108 lines
3.4 KiB
Verilog
108 lines
3.4 KiB
Verilog
/*------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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Copyright (c) 2016, Loongson Technology Corporation Limited.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation and/or
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other materials provided with the distribution.
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3. Neither the name of Loongson Technology Corporation Limited nor the names of
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its contributors may be used to endorse or promote products derived from this
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software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
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TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--------------------------------------------------------------------------------
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------------------------------------------------------------------------------*/
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`include "uart_defines.h"
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module UART_TOP(
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PCLK, PRST_,
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PSEL, PENABLE, PADDR, PWRITE,
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PWDATA, URT_PRDATA,
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INT, clk_carrier,
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TXD_i, TXD_o, TXD_oe,
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RXD_i, RXD_o, RXD_oe,
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RTS, CTS, DSR,
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DCD, DTR, RI
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);
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input PCLK, PRST_;
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input PSEL, PENABLE, PWRITE;
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input [7:0] PADDR;
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input [7:0] PWDATA;
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output [7:0] URT_PRDATA;
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output INT;
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input clk_carrier;
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input TXD_i;
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output TXD_o;
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output TXD_oe;
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input RXD_i;
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output RXD_o;
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output RXD_oe;
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output RTS;
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input CTS, DSR, DCD;
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output DTR;
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input RI;
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wire prst = !PRST_;
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wire we = PSEL & PENABLE & PWRITE;
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wire re = PSEL & PENABLE & !PWRITE;
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wire rx_en;
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wire tx2rx_en;
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wire isomode;
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assign TXD_oe = isomode&&(rx_en||tx2rx_en) ? 1'b1:1'b0;
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assign RXD_oe =~isomode;
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uart_regs regs(
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.clk (PCLK ),
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.rst (prst ),
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.clk_carrier (clk_carrier),
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.addr (PADDR[2:0] ),
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.dat_i (PWDATA ),
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.dat_o (URT_PRDATA ),
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.we (we ),
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.re (re ),
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.modem_inputs({ CTS, DSR, RI, DCD } ),
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.rts_pad_o (RTS ),
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.dtr_pad_o (DTR ),
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.stx_pad_o (TXD_o ),
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.TXD_i (TXD_i ),
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.srx_pad_i (RXD_i ),
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.RXD_o (RXD_o ),
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.int_o ( INT ),
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.tx2rx_en (tx2rx_en ),
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.rx_en (rx_en ),
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.usart_mode (isomode )
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);
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endmodule
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