120 lines
4.8 KiB
C
120 lines
4.8 KiB
C
/*------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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Copyright (c) 2016, Loongson Technology Corporation Limited.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation and/or
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other materials provided with the distribution.
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3. Neither the name of Loongson Technology Corporation Limited nor the names of
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its contributors may be used to endorse or promote products derived from this
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software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
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TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--------------------------------------------------------------------------------
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------------------------------------------------------------------------------*/
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`define UART_ADDR_WIDTH 3
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`define UART_DATA_WIDTH 8
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// Register addresses
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`define UART_REG_RB `UART_ADDR_WIDTH'd0 // receiver buffer
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`define UART_REG_TR `UART_ADDR_WIDTH'd0 // transmitter
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`define UART_REG_IE `UART_ADDR_WIDTH'd1 // Interrupt enable
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`define UART_REG_II `UART_ADDR_WIDTH'd2 // Interrupt identification
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`define UART_REG_FC `UART_ADDR_WIDTH'd2 // FIFO control
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`define UART_REG_LC `UART_ADDR_WIDTH'd3 // Line Control
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`define UART_REG_MC `UART_ADDR_WIDTH'd4 // Modem control
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`define UART_REG_LS `UART_ADDR_WIDTH'd5 // Line status
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`define UART_REG_MS `UART_ADDR_WIDTH'd6 // Modem status
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`define UART_REG_SR `UART_ADDR_WIDTH'd7 // Scratch register
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`define UART_REG_DL1 `UART_ADDR_WIDTH'd0 // Divisor latch bytes (1-2)
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`define UART_REG_DL2 `UART_ADDR_WIDTH'd1
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// Interrupt Enable register bits
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`define UART_IE_RDA 0 // Received Data available interrupt
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`define UART_IE_THRE 1 // Transmitter Holding Register empty interrupt
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`define UART_IE_RLS 2 // Receiver Line Status Interrupt
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`define UART_IE_MS 3 // Modem Status Interrupt
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// Interrupt Identification register bits
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`define UART_II_IP 0 // Interrupt pending when 0
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`define UART_II_II 3:1 // Interrupt identification
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// Interrupt identification values for bits 3:1
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`define UART_II_RLS 3'b011 // Receiver Line Status
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`define UART_II_RDA 3'b010 // Receiver Data available
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`define UART_II_TI 3'b110 // Timeout Indication
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`define UART_II_THRE 3'b001 // Transmitter Holding Register empty
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`define UART_II_MS 3'b000 // Modem Status
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// FIFO Control Register bits
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`define UART_FC_TL 1:0 // Trigger level
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// FIFO trigger level values
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`define UART_FC_1 2'b00
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`define UART_FC_4 2'b01
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`define UART_FC_8 2'b10
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`define UART_FC_14 2'b11
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// Line Control register bits
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`define UART_LC_BITS 1:0 // bits in character
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`define UART_LC_SB 2 // stop bits
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`define UART_LC_PE 3 // parity enable
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`define UART_LC_EP 4 // even parity
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`define UART_LC_SP 5 // stick parity
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`define UART_LC_BC 6 // Break control
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`define UART_LC_DL 7 // Divisor Latch access bit
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// Modem Control register bits
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`define UART_MC_DTR 0
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`define UART_MC_RTS 1
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`define UART_MC_OUT1 2
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`define UART_MC_OUT2 3
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`define UART_MC_LB 4 // Loopback mode
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// Line Status Register bits
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`define UART_LS_DR 0 // Data ready
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`define UART_LS_OE 1 // Overrun Error
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`define UART_LS_PE 2 // Parity Error
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`define UART_LS_FE 3 // Framing Error
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`define UART_LS_BI 4 // Break interrupt
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`define UART_LS_TFE 5 // Transmit FIFO is empty
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`define UART_LS_TE 6 // Transmitter Empty indicator
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`define UART_LS_EI 7 // Error indicator
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// Modem Status Register bits
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`define UART_MS_DCTS 0 // Delta signals
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`define UART_MS_DDSR 1
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`define UART_MS_TERI 2
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`define UART_MS_DDCD 3
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`define UART_MS_CCTS 4 // Complement signals
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`define UART_MS_CDSR 5
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`define UART_MS_CRI 6
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`define UART_MS_CDCD 7
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// FIFO parameter defines
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`define UART_FIFO_WIDTH 8
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`define UART_FIFO_DEPTH 16
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`define UART_FIFO_POINTER_W 4
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`define UART_FIFO_COUNTER_W 5
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`define UART_FIFO_REC_WIDTH 11
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