77 lines
2.8 KiB
Verilog
77 lines
2.8 KiB
Verilog
/*------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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Copyright (c) 2016, Loongson Technology Corporation Limited.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation and/or
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other materials provided with the distribution.
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3. Neither the name of Loongson Technology Corporation Limited nor the names of
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its contributors may be used to endorse or promote products derived from this
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software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
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TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--------------------------------------------------------------------------------
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------------------------------------------------------------------------------*/
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module uart_sync_flops
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(
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rst_i,
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clk_i,
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stage1_rst_i,
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stage1_clk_en_i,
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async_dat_i,
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sync_dat_o
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);
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parameter Tp = 1;
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parameter width = 1;
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parameter init_value = 1'b0;
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input rst_i;
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input clk_i;
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input stage1_rst_i;
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input stage1_clk_en_i;
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input [width-1:0] async_dat_i;
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output [width-1:0] sync_dat_o;
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reg [width-1:0] sync_dat_o;
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reg [width-1:0] flop_0;
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always @ (posedge clk_i)
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begin
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if (rst_i)
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flop_0 <= {width{init_value}};
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else
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flop_0 <= async_dat_i;
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end
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always @ (posedge clk_i)
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begin
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if (rst_i)
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sync_dat_o <= {width{init_value}};
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else if (stage1_rst_i)
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sync_dat_o <= {width{init_value}};
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else if (stage1_clk_en_i)
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sync_dat_o <= flop_0;
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end
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endmodule
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