53 lines
1.7 KiB
Verilog
53 lines
1.7 KiB
Verilog
`include "mycpu.h"
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`include "csr.h"
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`ifdef HAS_LACC
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module lacc_core(
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input clk,
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input reset,
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input lacc_flush,
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input lacc_req_valid,
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input [`LACC_OP_WIDTH-1: 0] lacc_req_command,
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input [6: 0] lacc_req_imm,
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input [31: 0] lacc_req_rj,
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input [31: 0] lacc_req_rk,
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output lacc_rsp_valid,
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output [31: 0] lacc_rsp_rdat,
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// wreq will also send valid sign
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output lacc_data_valid,
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input lacc_data_ready,
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output [31: 0] lacc_data_addr,
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output lacc_data_read,
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output [31: 0] lacc_data_wdata,
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output [1: 0] lacc_data_size,
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input lacc_drsp_valid,
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input [31: 0] lacc_drsp_rdata
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);
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lacc_demo demo(
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.clk(clk),
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.reset(reset),
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.lacc_flush (lacc_flush),
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.lacc_req_valid (lacc_req_valid),
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.lacc_req_command(lacc_req_command),
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.lacc_req_imm (lacc_req_imm),
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.lacc_req_rj (lacc_req_rj),
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.lacc_req_rk (lacc_req_rk),
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.lacc_rsp_valid (lacc_rsp_valid),
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.lacc_rsp_rdat (lacc_rsp_rdat),
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.lacc_data_valid(lacc_data_valid),
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.lacc_data_ready(lacc_data_ready),
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.lacc_data_addr (lacc_data_addr),
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.lacc_data_read (lacc_data_read),
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.lacc_data_wdata(lacc_data_wdata),
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.lacc_data_size (lacc_data_size),
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.lacc_drsp_valid(lacc_drsp_valid),
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.lacc_drsp_rdata(lacc_drsp_rdata)
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);
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endmodule
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`endif |