675 lines
33 KiB
Verilog
675 lines
33 KiB
Verilog
/*------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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Copyright (c) 2016, Loongson Technology Corporation Limited.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation and/or
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other materials provided with the distribution.
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3. Neither the name of Loongson Technology Corporation Limited nor the names of
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its contributors may be used to endorse or promote products derived from this
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software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
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TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--------------------------------------------------------------------------------
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------------------------------------------------------------------------------*/
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`include "config.h"
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module axi2apb_bridge(
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clk,
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rst_n,
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axi_s_awid,
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axi_s_awaddr,
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axi_s_awlen,
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axi_s_awsize,
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axi_s_awburst,
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axi_s_awlock,
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axi_s_awcache,
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axi_s_awprot,
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axi_s_awvalid,
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axi_s_awready,
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axi_s_wid,
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axi_s_wdata,
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axi_s_wstrb,
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axi_s_wlast,
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axi_s_wvalid,
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axi_s_wready,
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axi_s_bid,
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axi_s_bresp,
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axi_s_bvalid,
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axi_s_bready,
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axi_s_arid,
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axi_s_araddr,
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axi_s_arlen,
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axi_s_arsize,
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axi_s_arburst,
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axi_s_arlock,
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axi_s_arcache,
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axi_s_arprot,
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axi_s_arvalid,
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axi_s_arready,
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axi_s_rid,
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axi_s_rdata,
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axi_s_rresp,
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axi_s_rlast,
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axi_s_rvalid,
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axi_s_rready,
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apb_valid_cpu,
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cpu_grant,
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apb_word_trans,
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apb_high_24b_rd,
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apb_high_24b_wr,
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apb_clk,
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apb_reset_n,
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reg_psel,
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reg_enable,
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reg_rw,
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reg_addr,
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reg_datai,
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reg_ready_1,
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reg_datao
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);
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parameter L_ADDR_APB = 20;
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input clk;
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input rst_n;
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input [`LID :0] axi_s_awid;
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input [`Lawaddr -1 :0] axi_s_awaddr;
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input [`Lawlen -1 :0] axi_s_awlen;
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input [`Lawsize -1 :0] axi_s_awsize;
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input [`Lawburst -1 :0] axi_s_awburst;
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input [`Lawlock -1 :0] axi_s_awlock;
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input [`Lawcache -1 :0] axi_s_awcache;
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input [`Lawprot -1 :0] axi_s_awprot;
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input axi_s_awvalid;
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output axi_s_awready;
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input [`LID :0] axi_s_wid;
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input [`Lwdata -1 :0] axi_s_wdata;
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input [`Lwstrb -1 :0] axi_s_wstrb;
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input axi_s_wlast;
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input axi_s_wvalid;
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output axi_s_wready;
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output [`LID :0] axi_s_bid;
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output [`Lbresp -1 :0] axi_s_bresp;
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output axi_s_bvalid;
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input axi_s_bready;
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input [`LID :0] axi_s_arid;
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input [`Laraddr -1 :0] axi_s_araddr;
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input [`Larlen -1 :0] axi_s_arlen;
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input [`Larsize -1 :0] axi_s_arsize;
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input [`Larburst -1 :0] axi_s_arburst;
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input [`Larlock -1 :0] axi_s_arlock;
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input [`Larcache -1 :0] axi_s_arcache;
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input [`Larprot -1 :0] axi_s_arprot;
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input axi_s_arvalid;
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output axi_s_arready;
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output [`LID :0] axi_s_rid;
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output [`Lrdata -1 :0] axi_s_rdata;
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output [`Lrresp -1 :0] axi_s_rresp;
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output axi_s_rlast;
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output axi_s_rvalid;
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input axi_s_rready;
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input apb_word_trans;
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input cpu_grant;
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output apb_valid_cpu;
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input [23:0] apb_high_24b_rd;
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output [23:0] apb_high_24b_wr;
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output apb_clk;
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output apb_reset_n;
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output reg_psel;
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output reg_enable;
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output reg_rw;
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output[L_ADDR_APB-1:0] reg_addr;
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output[7:0] reg_datai;
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input [7:0] reg_datao;
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input reg_ready_1;
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wire csr_rw_send_axi_rsp_done;
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wire reg_ready;
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parameter CSR_RW_SM_IDLE = 4'b0001,
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CSR_RW_SM_GET_AXI_ADDR = 4'b0010,
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CSR_RW_SM_SEND_AXI_RSP = 4'b1000;
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reg reg_psel;
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reg reg_enable;
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reg axi_s_sel_rd;
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reg axi_s_sel_wr;
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reg[3:0] csr_rw_sm;
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reg[3:0] csr_rw_sm_nxt;
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reg[L_ADDR_APB-1:0] axi_s_req_addr;
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reg[`LID:0] axi_s_w_id;
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reg[`LID:0] axi_s_r_id;
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reg[23:0] apb_high_24b_wr;
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assign apb_clk = clk;
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assign apb_reset_n = rst_n;
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assign reg_rw = axi_s_sel_wr;
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assign reg_addr = axi_s_req_addr;
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assign reg_ready = reg_enable & reg_ready_1;
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assign apb_valid_cpu = axi_s_sel_wr | axi_s_sel_rd | axi_s_awvalid | axi_s_arvalid;
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reg axi_s_rlast;
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reg axi_s_rvalid;
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reg axi_s_wready;
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reg axi_s_awready;
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reg axi_s_arready;
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reg [3:0]axi_s_rstrb;
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reg [3:0]apb_s_wstrb;
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reg [31:0]reg_datai_32;
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reg [31:0]reg_datao_32;
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reg [2:0] rd_count;
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reg [2:0] apb_rd_size;
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reg [2:0] apb_wr_size;
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reg [7:0] reg_datai;
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reg axi_s_bvalid;
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always@(posedge clk)
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begin
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if(!rst_n)
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begin
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reg_datai_32 <= 32'h0;
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reg_datao_32 <= 32'h0;
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axi_s_req_addr <= 20'h0;
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apb_s_wstrb <= 4'b0;
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axi_s_rstrb <= 4'b0;
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axi_s_wready <= 1'b0;
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reg_enable <= 1'b0;
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reg_psel <= 1'b0;
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rd_count <= 3'b0;
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apb_rd_size <= 3'b0;
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apb_wr_size <= 3'b0;
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axi_s_rlast <= 1'b0;
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axi_s_rvalid <= 1'b0;
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reg_datai <= 8'b0;
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axi_s_awready <= 1'b0;
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axi_s_arready <= 1'b0;
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axi_s_bvalid <= 1'b0;
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axi_s_sel_wr <= 1'b0;
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axi_s_sel_rd <= 1'b0;
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axi_s_w_id <= 'h0;
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axi_s_r_id <= 'h0;
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apb_high_24b_wr <= 24'h0;
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end
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else begin
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if(axi_s_awvalid & ~axi_s_bvalid & ~axi_s_sel_rd & (csr_rw_sm == CSR_RW_SM_IDLE) &cpu_grant) begin
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axi_s_req_addr <= axi_s_awaddr[L_ADDR_APB-1:0];
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axi_s_awready <= 1'b1;
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axi_s_sel_wr <= 1'b1;
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apb_wr_size <= axi_s_awsize;
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end
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else if(axi_s_sel_wr) begin
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axi_s_awready <= 1'b0;
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if(axi_s_wvalid && ~axi_s_wready) begin
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`ifdef AXI128
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axi_s_req_addr <= (axi_s_wstrb[15:0]==16'h0002)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h1):
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(axi_s_wstrb[15:0]==16'h0004)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h2):
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(axi_s_wstrb[15:0]==16'h0008)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h3):
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(axi_s_wstrb[15:0]==16'h0010)&&(axi_s_req_addr[ 2]==1'h0)? (axi_s_req_addr + 4'h4):
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(axi_s_wstrb[15:0]==16'h0020)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h5):
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(axi_s_wstrb[15:0]==16'h0040)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h6):
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(axi_s_wstrb[15:0]==16'h0080)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h7):
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(axi_s_wstrb[15:0]==16'h0100)&&(axi_s_req_addr[ 3]==1'h0)? (axi_s_req_addr + 4'h8):
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(axi_s_wstrb[15:0]==16'h0200)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h9):
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(axi_s_wstrb[15:0]==16'h0400)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'ha):
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(axi_s_wstrb[15:0]==16'h0800)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'hb):
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(axi_s_wstrb[15:0]==16'h1000)&&(axi_s_req_addr[ 2]==1'h0)? (axi_s_req_addr + 4'hc):
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(axi_s_wstrb[15:0]==16'h2000)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'hd):
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(axi_s_wstrb[15:0]==16'h4000)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'he):
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(axi_s_wstrb[15:0]==16'h8000)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'hf):
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(axi_s_wstrb[15:0]==16'h0006)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h1):
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(axi_s_wstrb[15:0]==16'h000c)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h2):
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(axi_s_wstrb[15:0]==16'h0018)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h3):
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(axi_s_wstrb[15:0]==16'h0030)&&(axi_s_req_addr[ 2]==1'h0)? (axi_s_req_addr + 4'h4):
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(axi_s_wstrb[15:0]==16'h0060)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h5):
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(axi_s_wstrb[15:0]==16'h00c0)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h6):
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(axi_s_wstrb[15:0]==16'h0180)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h7):
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(axi_s_wstrb[15:0]==16'h0300)&&(axi_s_req_addr[ 3]==1'h0)? (axi_s_req_addr + 4'h8):
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(axi_s_wstrb[15:0]==16'h0600)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h9):
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(axi_s_wstrb[15:0]==16'h0c00)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'ha):
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(axi_s_wstrb[15:0]==16'h1800)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'hb):
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(axi_s_wstrb[15:0]==16'h3000)&&(axi_s_req_addr[ 2]==1'h0)? (axi_s_req_addr + 4'hc):
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(axi_s_wstrb[15:0]==16'h6000)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'hd):
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(axi_s_wstrb[15:0]==16'hc000)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'he):
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(axi_s_wstrb[15:0]==16'h001e)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h1):
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(axi_s_wstrb[15:0]==16'h003c)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h2):
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(axi_s_wstrb[15:0]==16'h0078)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h3):
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(axi_s_wstrb[15:0]==16'h00f0)&&(axi_s_req_addr[ 2]==1'h0)? (axi_s_req_addr + 4'h4):
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(axi_s_wstrb[15:0]==16'h01e0)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h5):
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(axi_s_wstrb[15:0]==16'h03c0)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h6):
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(axi_s_wstrb[15:0]==16'h0780)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h7):
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(axi_s_wstrb[15:0]==16'h0f00)&&(axi_s_req_addr[ 3]==1'h0)? (axi_s_req_addr + 4'h8):
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(axi_s_wstrb[15:0]==16'h1e00)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h9):
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(axi_s_wstrb[15:0]==16'h3c00)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'ha):
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(axi_s_wstrb[15:0]==16'h7800)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'hb):
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(axi_s_wstrb[15:0]==16'hf000)&&(axi_s_req_addr[ 2]==1'h0)? (axi_s_req_addr + 4'hc):
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(axi_s_wstrb[15:0]==16'h01fe)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h1):
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(axi_s_wstrb[15:0]==16'h03fc)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h2):
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(axi_s_wstrb[15:0]==16'h07f8)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h3):
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(axi_s_wstrb[15:0]==16'h0ff0)&&(axi_s_req_addr[ 2]==1'h0)? (axi_s_req_addr + 4'h4):
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(axi_s_wstrb[15:0]==16'h1fe0)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h5):
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(axi_s_wstrb[15:0]==16'h3fc0)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h6):
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(axi_s_wstrb[15:0]==16'h7f80)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h7):
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(axi_s_wstrb[15:0]==16'hff00)&&(axi_s_req_addr[ 3]==1'h0)? (axi_s_req_addr + 4'h8): axi_s_req_addr ;
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`elsif AXI64
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axi_s_req_addr <= (axi_s_wstrb[7:0]==8'h02)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h1):
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(axi_s_wstrb[7:0]==8'h04)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h2):
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(axi_s_wstrb[7:0]==8'h08)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h3):
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(axi_s_wstrb[7:0]==8'h10)&&(axi_s_req_addr[ 2]==1'h0)? (axi_s_req_addr + 2'h4):
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(axi_s_wstrb[7:0]==8'h20)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h5):
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(axi_s_wstrb[7:0]==8'h40)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h6):
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(axi_s_wstrb[7:0]==8'h80)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h7):
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(axi_s_wstrb[7:0]==8'h06)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h1):
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(axi_s_wstrb[7:0]==8'h0c)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h2):
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(axi_s_wstrb[7:0]==8'h18)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h3):
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(axi_s_wstrb[7:0]==8'h30)&&(axi_s_req_addr[ 2]==1'h0)? (axi_s_req_addr + 2'h4):
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(axi_s_wstrb[7:0]==8'h60)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h5):
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(axi_s_wstrb[7:0]==8'hc0)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h6):
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(axi_s_wstrb[7:0]==8'h1e)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h1):
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(axi_s_wstrb[7:0]==8'h3c)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h2):
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(axi_s_wstrb[7:0]==8'h78)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h3):
|
|
(axi_s_wstrb[7:0]==8'hf0)&&(axi_s_req_addr[ 2]==1'h0)? (axi_s_req_addr + 2'h4): axi_s_req_addr ;
|
|
`else
|
|
axi_s_req_addr <= (axi_s_wstrb[3:0]==4'h2)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h1):
|
|
(axi_s_wstrb[3:0]==4'h4)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h2):
|
|
(axi_s_wstrb[3:0]==4'h8)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h3):
|
|
(axi_s_wstrb[3:0]==4'h6)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h1):
|
|
(axi_s_wstrb[3:0]==4'hc)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h2): axi_s_req_addr ;
|
|
`endif
|
|
|
|
axi_s_wready <= 1'b1;
|
|
reg_psel <= 1'b0;
|
|
reg_enable <= 1'b0;
|
|
axi_s_w_id <= axi_s_wid;
|
|
`ifdef AXI128
|
|
case({axi_s_req_addr[3:0]})
|
|
4'b0000: begin apb_s_wstrb <= axi_s_wstrb[ 3: 0]; reg_datai_32 <=axi_s_wdata[ 31: 0]; end
|
|
4'b0001: begin apb_s_wstrb <= axi_s_wstrb[ 4: 1]; reg_datai_32 <=axi_s_wdata[ 39: 8]; end
|
|
4'b0010: begin apb_s_wstrb <= axi_s_wstrb[ 5: 2]; reg_datai_32 <=axi_s_wdata[ 47: 16]; end
|
|
4'b0011: begin apb_s_wstrb <= axi_s_wstrb[ 6: 3]; reg_datai_32 <=axi_s_wdata[ 55: 24]; end
|
|
4'b0100: begin apb_s_wstrb <= axi_s_wstrb[ 7: 4]; reg_datai_32 <=axi_s_wdata[ 63: 32]; end
|
|
4'b0101: begin apb_s_wstrb <= axi_s_wstrb[ 8: 5]; reg_datai_32 <=axi_s_wdata[ 71: 40]; end
|
|
4'b0110: begin apb_s_wstrb <= axi_s_wstrb[ 9: 6]; reg_datai_32 <=axi_s_wdata[ 79: 48]; end
|
|
4'b0111: begin apb_s_wstrb <= axi_s_wstrb[10: 7]; reg_datai_32 <=axi_s_wdata[ 87: 56]; end
|
|
4'b1000: begin apb_s_wstrb <= axi_s_wstrb[11: 8]; reg_datai_32 <=axi_s_wdata[ 95: 64]; end
|
|
4'b1001: begin apb_s_wstrb <= axi_s_wstrb[12: 9]; reg_datai_32 <=axi_s_wdata[103: 72]; end
|
|
4'b1010: begin apb_s_wstrb <= axi_s_wstrb[13:10]; reg_datai_32 <=axi_s_wdata[111: 80]; end
|
|
4'b1011: begin apb_s_wstrb <= axi_s_wstrb[14:11]; reg_datai_32 <=axi_s_wdata[119: 88]; end
|
|
4'b1100: begin apb_s_wstrb <= axi_s_wstrb[15:12]; reg_datai_32 <=axi_s_wdata[127: 96]; end
|
|
4'b1101: begin apb_s_wstrb <= {1'b0, axi_s_wstrb[15:13]}; reg_datai_32 <={ 8'b0, axi_s_wdata[127:104]}; end
|
|
4'b1110: begin apb_s_wstrb <= {2'b0, axi_s_wstrb[15:14]}; reg_datai_32 <={16'b0, axi_s_wdata[127:112]}; end
|
|
4'b1111: begin apb_s_wstrb <= {3'b0, axi_s_wstrb[ 15]}; reg_datai_32 <={24'b0, axi_s_wdata[127:120]}; end
|
|
default: begin apb_s_wstrb <= 4'b0; reg_datai_32 <=32'h0; end
|
|
endcase
|
|
`elsif AXI64
|
|
case({axi_s_req_addr[2:0]})
|
|
3'b000: begin apb_s_wstrb <= axi_s_wstrb[3:0]; reg_datai_32 <=axi_s_wdata[31: 0]; end
|
|
3'b001: begin apb_s_wstrb <= axi_s_wstrb[4:1]; reg_datai_32 <=axi_s_wdata[39: 8]; end
|
|
3'b010: begin apb_s_wstrb <= axi_s_wstrb[5:2]; reg_datai_32 <=axi_s_wdata[47:16]; end
|
|
3'b011: begin apb_s_wstrb <= axi_s_wstrb[6:3]; reg_datai_32 <=axi_s_wdata[55:24]; end
|
|
3'b100: begin apb_s_wstrb <= axi_s_wstrb[7:4]; reg_datai_32 <=axi_s_wdata[63:32]; end
|
|
3'b101: begin apb_s_wstrb <= {1'b0, axi_s_wstrb[7:5]}; reg_datai_32 <={8 'b0, axi_s_wdata[63:40]}; end
|
|
3'b110: begin apb_s_wstrb <= {2'b0, axi_s_wstrb[7:6]}; reg_datai_32 <={16'b0, axi_s_wdata[63:48]}; end
|
|
3'b111: begin apb_s_wstrb <= {3'b0, axi_s_wstrb[ 7]}; reg_datai_32 <={24'b0, axi_s_wdata[63:56]}; end
|
|
default: begin apb_s_wstrb <= 4'b0; reg_datai_32 <=32'h0; end
|
|
endcase
|
|
`else
|
|
case({axi_s_req_addr[1:0]})
|
|
2'b00: begin apb_s_wstrb <= axi_s_wstrb[3:0]; reg_datai_32 <=axi_s_wdata[31:0]; end
|
|
2'b01: begin apb_s_wstrb <= {1'b0,axi_s_wstrb[3:1]}; reg_datai_32 <={8'h0,axi_s_wdata[31:8]}; end
|
|
2'b10: begin apb_s_wstrb <= {2'b0,axi_s_wstrb[3:2]}; reg_datai_32 <={16'b0,axi_s_wdata[31:16]}; end
|
|
2'b11: begin apb_s_wstrb <= {3'b0,axi_s_wstrb[3]}; reg_datai_32 <={24'b0,axi_s_wdata[31:24]}; end
|
|
default: begin apb_s_wstrb <= 4'b0; reg_datai_32 <=32'h0; end
|
|
endcase
|
|
`endif
|
|
end
|
|
else if((~reg_psel) && (apb_s_wstrb!=4'h0) ) begin
|
|
reg_psel <= 1'b1;
|
|
reg_enable <= 1'b0;
|
|
reg_datai <= (apb_s_wstrb == 4'h1) ? reg_datai_32[7:0]:
|
|
(apb_s_wstrb == 4'h2) ? reg_datai_32[15:8]:
|
|
(apb_s_wstrb == 4'h6) ? reg_datai_32[15:8]:
|
|
(apb_s_wstrb == 4'h4) ? reg_datai_32[23:16]:
|
|
(apb_s_wstrb == 4'h8) ? reg_datai_32[31:24]: reg_datai_32[7:0];
|
|
apb_high_24b_wr <= reg_datai_32[31:8];
|
|
if(axi_s_bready) axi_s_bvalid <= 1'b0;
|
|
end
|
|
else if(apb_word_trans & apb_s_wstrb==4'hf ) begin
|
|
if(~reg_ready)begin
|
|
reg_psel <= 1'b1;
|
|
reg_enable <= 1'b1;
|
|
end
|
|
else begin
|
|
reg_psel <= 1'b0;
|
|
reg_enable <= 1'b0;
|
|
axi_s_sel_wr <= 1'b0;
|
|
axi_s_bvalid <= 1'b1;
|
|
apb_s_wstrb <= 4'b0;
|
|
end
|
|
reg_datai <= reg_datai_32[7:0];
|
|
apb_high_24b_wr <= reg_datai_32[31:8];
|
|
axi_s_wready <= 1'b0;
|
|
end
|
|
else if(apb_s_wstrb[0]) begin
|
|
if(~reg_ready)begin
|
|
reg_psel <= 1'b1;
|
|
reg_enable <= 1'b1;
|
|
reg_datai <= reg_datai_32[7:0];
|
|
end
|
|
else begin
|
|
if(apb_s_wstrb[3:1] ==3'b0)
|
|
begin
|
|
reg_psel <= 1'b0;
|
|
axi_s_sel_wr<= 1'b0;
|
|
axi_s_bvalid <= 1'b1;
|
|
end
|
|
else
|
|
reg_psel <= 1'b1;
|
|
reg_enable <= 1'b0;
|
|
apb_s_wstrb[0] <= 1'b0;
|
|
axi_s_req_addr <= axi_s_req_addr +1'b1;
|
|
reg_datai <= reg_datai_32[15:8];
|
|
end
|
|
axi_s_wready <= 1'b0;
|
|
end
|
|
else if (apb_s_wstrb[1]) begin
|
|
if(~reg_ready)begin
|
|
reg_psel <= 1'b1;
|
|
reg_enable <= 1'b1;
|
|
end
|
|
else begin
|
|
if(apb_s_wstrb[3:2] ==2'b0)
|
|
begin
|
|
reg_psel <= 1'b0;
|
|
axi_s_sel_wr <= 1'b0;
|
|
axi_s_bvalid <= 1'b1;
|
|
end
|
|
else
|
|
reg_psel <= 1'b1;
|
|
reg_enable <= 1'b0;
|
|
apb_s_wstrb[1] <= 1'b0;
|
|
axi_s_req_addr <= axi_s_req_addr +1'b1;
|
|
reg_datai <= reg_datai_32[23:16];
|
|
end
|
|
axi_s_wready <= 1'b0;
|
|
end
|
|
else if (apb_s_wstrb[2]) begin
|
|
if(~reg_ready)begin
|
|
reg_psel <= 1'b1;
|
|
reg_enable <= 1'b1;
|
|
end
|
|
else begin
|
|
if(apb_s_wstrb[3] ==1'b0)
|
|
begin
|
|
reg_psel <= 1'b0;
|
|
axi_s_sel_wr <= 1'b0;
|
|
axi_s_bvalid <= 1'b1;
|
|
end
|
|
else
|
|
reg_psel <= 1'b1;
|
|
reg_enable <= 1'b0;
|
|
apb_s_wstrb[2] <= 1'b0;
|
|
axi_s_req_addr <= axi_s_req_addr +1'b1;
|
|
reg_datai <= reg_datai_32[31:24];
|
|
end
|
|
axi_s_wready <= 1'b0;
|
|
end
|
|
else if (apb_s_wstrb[3]) begin
|
|
if(~reg_ready)begin
|
|
reg_psel <= 1'b1;
|
|
reg_enable <= 1'b1;
|
|
end
|
|
else begin
|
|
reg_psel <= 1'b0;
|
|
reg_enable <= 1'b0;
|
|
axi_s_sel_wr <= 1'b0;
|
|
axi_s_bvalid <= 1'b1;
|
|
apb_s_wstrb[3] <= 1'b0;
|
|
end
|
|
axi_s_wready <= 1'b0;
|
|
end
|
|
else begin
|
|
reg_psel <= 1'b0;
|
|
reg_enable <= 1'b0;
|
|
reg_datai <= 8'h0;
|
|
apb_s_wstrb <= 4'h0;
|
|
axi_s_wready <= 1'b0;
|
|
if(csr_rw_sm == CSR_RW_SM_IDLE) axi_s_sel_wr <= 1'b0;
|
|
end
|
|
end
|
|
else if(axi_s_arvalid & ~axi_s_arready & ~axi_s_bvalid & (csr_rw_sm == CSR_RW_SM_IDLE)&cpu_grant)
|
|
begin
|
|
reg_enable <= 1'b0;
|
|
reg_psel <= 1'b1;
|
|
axi_s_arready <= 1'b1;
|
|
axi_s_sel_rd <= 1'b1;
|
|
axi_s_r_id <= axi_s_arid;
|
|
apb_rd_size <= axi_s_arsize;
|
|
axi_s_req_addr <= axi_s_araddr[L_ADDR_APB-1:0];
|
|
axi_s_rstrb <= axi_s_araddr[3:0];
|
|
if(axi_s_arsize==3'b010)
|
|
rd_count<= 3'h4;
|
|
else if(axi_s_arsize==3'b01)
|
|
rd_count<= 3'h2;
|
|
else if(axi_s_arsize==3'b0)
|
|
rd_count<= 3'h1;
|
|
end
|
|
else if(axi_s_sel_rd)
|
|
begin
|
|
axi_s_arready <= 1'b0;
|
|
if(apb_word_trans)
|
|
begin
|
|
if(reg_ready)
|
|
begin
|
|
reg_psel <= rd_count==3'b10;
|
|
reg_enable <= 1'b0;
|
|
rd_count <= rd_count-3'b1;
|
|
axi_s_rlast <= apb_rd_size==3'h2|rd_count==2'b1;
|
|
axi_s_rvalid <= apb_rd_size==3'h2|rd_count==2'b1;
|
|
axi_s_sel_rd <= rd_count==3'b10;
|
|
reg_datao_32 <= {apb_high_24b_rd,reg_datao};
|
|
end
|
|
else begin
|
|
reg_psel <= 1'b1;
|
|
reg_enable <= 1'b1;
|
|
end
|
|
end
|
|
else if(rd_count==3'h4)
|
|
begin
|
|
if(reg_ready)
|
|
begin
|
|
reg_psel <= 1'b1;
|
|
reg_enable <= 1'b0;
|
|
rd_count <= rd_count-3'h1;
|
|
reg_datao_32[7:0] <= reg_datao;
|
|
axi_s_req_addr <= axi_s_req_addr +1'b1;
|
|
end
|
|
else begin
|
|
reg_psel <= 1'b1;
|
|
reg_enable <= 1'b1;
|
|
end
|
|
end
|
|
else if(rd_count==3'h3)
|
|
begin
|
|
if(reg_ready)
|
|
begin
|
|
reg_psel <= 1'b1;
|
|
reg_enable <= 1'b0;
|
|
rd_count <= rd_count-3'h1;
|
|
reg_datao_32[15:8] <= reg_datao;
|
|
axi_s_req_addr <= axi_s_req_addr +1'b1;
|
|
end
|
|
else begin
|
|
reg_psel <= 1'b1;
|
|
reg_enable <= 1'b1;
|
|
end
|
|
end
|
|
else if(rd_count==3'h2)
|
|
begin
|
|
if(reg_ready)
|
|
begin
|
|
reg_psel <= 1'b1;
|
|
reg_enable <= 1'b0;
|
|
rd_count <= rd_count-3'h1;
|
|
axi_s_req_addr <= axi_s_req_addr +1'b1;
|
|
if(apb_rd_size==3'h2 )
|
|
reg_datao_32[23:16] <= reg_datao;
|
|
else if(apb_rd_size==3'h1)
|
|
reg_datao_32[7:0] <= reg_datao;
|
|
end
|
|
else begin
|
|
reg_psel <= 1'b1;
|
|
reg_enable <= 1'b1;
|
|
end
|
|
end
|
|
else if(rd_count==3'h1)
|
|
begin
|
|
if(reg_ready)
|
|
begin
|
|
reg_psel <= 1'b0;
|
|
reg_enable <= 1'b0;
|
|
axi_s_rlast <= 1'b1;
|
|
axi_s_rvalid <= 1'b1;
|
|
axi_s_sel_rd <= 1'b0;
|
|
if(apb_rd_size==3'h2 )
|
|
reg_datao_32[31:24] <= reg_datao;
|
|
else if(apb_rd_size==3'h1)
|
|
reg_datao_32[15:8] <= reg_datao;
|
|
else if(apb_rd_size==3'h0)
|
|
reg_datao_32[7:0] <= reg_datao;
|
|
end
|
|
else begin
|
|
reg_psel <= 1'b1;
|
|
reg_enable <= 1'b1;
|
|
end
|
|
end// end if(rd_count)
|
|
else begin
|
|
axi_s_arready <= 1'b0;
|
|
axi_s_rlast <= 1'b1;
|
|
axi_s_rvalid <= 1'b1;
|
|
reg_psel <= 1'b0;
|
|
reg_enable <= 1'b0;
|
|
if(axi_s_rvalid && axi_s_rready)
|
|
begin
|
|
reg_datao_32 <= 32'h0;
|
|
axi_s_rlast <= 1'b0;
|
|
axi_s_rvalid <= 1'b0;
|
|
end
|
|
if(csr_rw_sm == CSR_RW_SM_IDLE) axi_s_sel_rd <= 1'b0;
|
|
if(axi_s_bready) axi_s_bvalid <= 1'b0;
|
|
end
|
|
end//end if(axi_s_sel_rd)
|
|
else begin
|
|
reg_psel <= 1'b0;
|
|
reg_enable <= 1'b0;
|
|
axi_s_sel_wr <= 1'b0;
|
|
axi_s_sel_rd <= 1'b0;
|
|
axi_s_wready <= 1'b0;
|
|
axi_s_arready <= 1'b0;
|
|
axi_s_req_addr <= 32'h0;
|
|
reg_datai_32 <= 32'h0;
|
|
if(axi_s_bready) axi_s_bvalid <= 1'b0;
|
|
if(axi_s_rvalid && axi_s_rready)
|
|
begin
|
|
reg_datao_32 <= 32'h0;
|
|
axi_s_rlast <= 1'b0;
|
|
axi_s_rvalid <= 1'b0;
|
|
end
|
|
end
|
|
end//end if(rst_n)
|
|
end//end always
|
|
|
|
assign csr_rw_send_axi_rsp_done = csr_rw_sm == CSR_RW_SM_SEND_AXI_RSP && axi_s_rlast && axi_s_rready || axi_s_bvalid && axi_s_bready;
|
|
|
|
assign axi_s_bid = axi_s_w_id;
|
|
assign axi_s_rid = axi_s_r_id;
|
|
assign axi_s_bresp = 2'b00;
|
|
assign axi_s_rresp = 2'b00;
|
|
`ifdef AXI128
|
|
assign axi_s_rdata= ( axi_s_rstrb == 4'h0) ? {96'b0, reg_datao_32 } :
|
|
( axi_s_rstrb == 4'h1) ? {88'b0, reg_datao_32, 8'b0 } :
|
|
( axi_s_rstrb == 4'h2) ? {80'b0, reg_datao_32, 16'b0 } :
|
|
( axi_s_rstrb == 4'h3) ? {72'b0, reg_datao_32, 24'b0 } :
|
|
( axi_s_rstrb == 4'h4) ? {64'b0, reg_datao_32, 32'b0 } :
|
|
( axi_s_rstrb == 4'h5) ? {56'b0, reg_datao_32, 40'b0 } :
|
|
( axi_s_rstrb == 4'h6) ? {48'b0, reg_datao_32, 48'b0 } :
|
|
( axi_s_rstrb == 4'h7) ? {40'b0, reg_datao_32, 56'b0 } :
|
|
( axi_s_rstrb == 4'h8) ? {32'b0, reg_datao_32, 64'b0 } :
|
|
( axi_s_rstrb == 4'h9) ? {24'b0, reg_datao_32, 72'b0 } :
|
|
( axi_s_rstrb == 4'ha) ? {16'b0, reg_datao_32, 80'b0 } :
|
|
( axi_s_rstrb == 4'hb) ? { 8'b0, reg_datao_32, 88'b0 } :
|
|
( axi_s_rstrb == 4'hc) ? {reg_datao_32, 96'b0 } :
|
|
( axi_s_rstrb == 4'hd) ? {reg_datao_32[23:0], 104'b0 } :
|
|
( axi_s_rstrb == 4'he) ? {reg_datao_32[15:0], 112'b0 } :
|
|
( axi_s_rstrb == 4'hf) ? {reg_datao_32[ 7:0], 120'b0 } : 128'h0;
|
|
|
|
`elsif AXI64
|
|
assign axi_s_rdata= ( axi_s_rstrb[2:0] == 3'h0) ? {32'b0, reg_datao_32 } :
|
|
( axi_s_rstrb[2:0] == 3'h1) ? {24'b0, reg_datao_32, 8'b0 } :
|
|
( axi_s_rstrb[2:0] == 3'h2) ? {16'b0, reg_datao_32, 16'b0 } :
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( axi_s_rstrb[2:0] == 3'h3) ? { 8'b0, reg_datao_32, 24'b0 } :
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( axi_s_rstrb[2:0] == 3'h4) ? {reg_datao_32, 32'b0 } :
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( axi_s_rstrb[2:0] == 3'h5) ? {reg_datao_32[23:0], 40'b0 } :
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( axi_s_rstrb[2:0] == 3'h6) ? {reg_datao_32[15:0], 48'b0 } :
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( axi_s_rstrb[2:0] == 3'h7) ? {reg_datao_32[ 7:0], 56'b0 } : 64'h0;
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`else
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assign axi_s_rdata= ( axi_s_rstrb[1:0] == 2'h0) ? { reg_datao_32 } :
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( axi_s_rstrb[1:0] == 2'h1) ? {reg_datao_32[23:0], 8'h0} :
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( axi_s_rstrb[1:0] == 2'h2) ? {reg_datao_32[15:0],16'h0} :
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( axi_s_rstrb[1:0] == 2'h3) ? {reg_datao_32[7:0], 24'h0} : 32'h0;
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`endif
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always@(csr_rw_sm or axi_s_awvalid or axi_s_arvalid or axi_s_sel_rd or axi_s_sel_wr or
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axi_s_wready or csr_rw_send_axi_rsp_done or cpu_grant) begin
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case(csr_rw_sm)
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CSR_RW_SM_IDLE:
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if((axi_s_awvalid || axi_s_arvalid)&&~(axi_s_sel_wr||axi_s_sel_rd)&cpu_grant)
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csr_rw_sm_nxt = CSR_RW_SM_GET_AXI_ADDR;
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else
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csr_rw_sm_nxt = CSR_RW_SM_IDLE;
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CSR_RW_SM_GET_AXI_ADDR:
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if(axi_s_sel_wr)
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csr_rw_sm_nxt = CSR_RW_SM_SEND_AXI_RSP;
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else if(axi_s_sel_rd)
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csr_rw_sm_nxt = CSR_RW_SM_SEND_AXI_RSP;
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else
|
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csr_rw_sm_nxt = CSR_RW_SM_GET_AXI_ADDR;
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CSR_RW_SM_SEND_AXI_RSP:
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if(csr_rw_send_axi_rsp_done)
|
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csr_rw_sm_nxt = CSR_RW_SM_IDLE;
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else
|
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csr_rw_sm_nxt = CSR_RW_SM_SEND_AXI_RSP;
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default:
|
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csr_rw_sm_nxt = CSR_RW_SM_IDLE;
|
|
endcase
|
|
end
|
|
|
|
always@(posedge clk) begin
|
|
if(!rst_n)
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csr_rw_sm <= CSR_RW_SM_IDLE;
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|
else
|
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csr_rw_sm <= csr_rw_sm_nxt;
|
|
end
|
|
|
|
endmodule
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