xilinx.com xci unknown 1.0 clk_pll false 100000000 false 100000000 false 100000000 false 100000000 100000000 0 0.000 100000000 0 0.000 100000000 0 0.000 1 LEVEL_HIGH 100000000 0 0.000 0 0 100000000 0 0.000 1 0 0 0 1 100000000 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0.000 AXI4LITE READ_WRITE 0 0 0 0 0 0 MMCM cddcdone cddcreq 0000 0000 clkfb_in_n clkfb_in clkfb_in_p SINGLE clkfb_out_n clkfb_out clkfb_out_p clkfb_stopped 200.0 100.0 0000 0000 32.979 0000 0000 50.000 BUFG 50.0 false 32.979 0.000 50.000 33.000 0.000 1 0000 0000 100.000 BUFG 50.0 false 50.000 0.000 50.000 50.000 0.000 1 1 0000 0000 100.000 BUFG 50.000 false 100.000 0.000 50.000 100.000 0.000 1 0 0000 0000 100.000 BUFG 50.000 false 100.000 0.000 50.000 100.000 0.000 1 0 0000 0000 100.000 BUFG 50.000 false 100.000 0.000 50.000 100.000 0.000 1 0 0000 0000 100.000 BUFG 50.000 false 100.000 0.000 50.000 100.000 0.000 1 0 BUFG 50.000 false 100.000 0.000 50.000 100.000 0.000 1 0 VCO clk_in_sel cpu_clk sys_clk clk_out3 clk_out4 clk_out5 clk_out6 clk_out7 CLK_VALID NA daddr dclk den din 0000 1 0.66 0.33 0.33 0.33 0.33 0.33 dout drdy dwe 0 0 0 0 0 0 0 0 FDBK_AUTO 0000 0000 0 Input Clock Freq (MHz) Input Jitter (UI) __primary__________50.000____________0.010 no_secondary_input_clock input_clk_stopped 0 Units_MHz No_Jitter locked 0000 0000 0000 false false false false false false false false OPTIMIZED 31.000 0.000 FALSE 20.000 10.0 47.000 0.500 0.000 FALSE 31 0.500 0.000 FALSE 1 0.500 0.000 FALSE 1 0.500 0.000 FALSE FALSE 1 0.500 0.000 FALSE 1 0.500 0.000 FALSE 1 0.500 0.000 FALSE FALSE ZHOLD 1 None 0.010 0.010 FALSE 2 Output Output Phase Duty Cycle Pk-to-Pk Phase Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) _cpu_clk____32.979______0.000______50.0______130.093____123.600 _sys_clk____50.000______0.000______50.0______122.035____123.600 no_CLK_OUT3_output no_CLK_OUT4_output no_CLK_OUT5_output no_CLK_OUT6_output no_CLK_OUT7_output 0 0 WAVEFORM UNKNOWN false false false false false OPTIMIZED 1 0.000 1.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 CLKFBOUT SYSTEM_SYNCHRONOUS 1 No notes 0.010 power_down 0000 1 clk_in1 PLL AUTO 50.000 0.010 10.000 Single_ended_clock_capable_pin psclk psdone psen psincdec 100.0 1 resetn 100.000 0.010 10.000 clk_in2 Single_ended_clock_capable_pin CENTER_HIGH 4000 0.004 STATUS 11 32 100.0 100.0 100.0 100.0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0 0 0 clk_pll MMCM false empty cddcdone cddcreq clkfb_in_n clkfb_in clkfb_in_p SINGLE clkfb_out_n clkfb_out clkfb_out_p clkfb_stopped 200.0 0.010 100.0 0.010 BUFG 130.093 false 123.600 50.000 33.000 0.000 1 true BUFG 122.035 false 123.600 50.000 50.000 0.000 1 true BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false 600.000 Custom Custom clk_in_sel cpu_clk false sys_clk false clk_out3 false clk_out4 false clk_out5 false clk_out6 false clk_out7 false CLK_VALID auto clk_pll daddr dclk den Custom Custom din dout drdy dwe false false false false false false false false false FDBK_AUTO input_clk_stopped frequency Enable_AXI Units_MHz Units_UI UI No_Jitter locked OPTIMIZED 31 0.000 false 20.000 10.0 47 0.500 0.000 false 31 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false false ZHOLD 1 None 0.010 0.010 false 2 false false WAVEFORM false UNKNOWN OPTIMIZED 4 0.000 10.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 CLKFBOUT SYSTEM_SYNCHRONOUS 1 None 0.010 power_down 1 clk_in1 PLL mmcm_adv 50.000 0.010 10.000 Single_ended_clock_capable_pin psclk psdone psen psincdec 100.0 REL_PRIMARY Custom resetn ACTIVE_LOW 100.000 0.010 10.000 clk_in2 Single_ended_clock_capable_pin CENTER_HIGH 250 0.004 STATUS empty 100.0 100.0 100.0 100.0 false false false false false false false true false false true false false false true false true false false false artix7 xc7a200t fbg676 VERILOG MIXED -1 TRUE TRUE IP_Flow 2 TRUE ../../../fpga/project/ipgen/clk_pll ../../../fpga/project/ipgen/clk_pll 2018.3 OUT_OF_CONTEXT