From c4a34f7b3888b0b2cdc5674b247ef7cb74020fa6 Mon Sep 17 00:00:00 2001 From: FallenSigh Date: Mon, 13 Apr 2026 17:10:32 +0800 Subject: [PATCH] feat(top): integrate snix_axil_cdma_mux into top --- rtl/soc_top.v | 184 +++++++++++++++++++++----------------------------- 1 file changed, 77 insertions(+), 107 deletions(-) diff --git a/rtl/soc_top.v b/rtl/soc_top.v index 1ca0d03..91abc5d 100644 --- a/rtl/soc_top.v +++ b/rtl/soc_top.v @@ -1475,43 +1475,6 @@ fft_controller u_fft_controller( .fft_finish (fft_finish ) ); -// assign dma_m_arid = 4'b0 ; -// assign dma_m_araddr = 32'h0; -// assign dma_m_arlen = 8'b0 ; -// assign dma_m_arsize = 3'b0 ; -// assign dma_m_arburst = 2'b0; -// assign dma_m_arlock = 1'b0; -// assign dma_m_arcache = 4'b0; -// assign dma_m_arprot = 3'b0; -// assign dma_m_arvalid = 1'b0; -// assign dma_m_rready = 1'b1; -// assign dma_m_awid = 4'b0; -// assign dma_m_awaddr = 32'b0; -// assign dma_m_awlen = 8'b0; -// assign dma_m_awsize = 3'b0; -// assign dma_m_awburst = 2'b0; -// assign dma_m_awlock = 1'b0; -// assign dma_m_awcache = 4'b0; -// assign dma_m_awprot = 3'b0; -// assign dma_m_awvalid = 1'b0; -// assign dma_m_wid = 4'b0; -// assign dma_m_wdata = 32'b0; -// assign dma_m_wstrb = 4'b0; -// assign dma_m_wlast = 1'b0; -// assign dma_m_wvalid = 1'b0; -// assign dma_m_bready = 1'b1; -// assign dma_s_arready = 1'b1; -// assign dma_s_rid = 5'b0; -// assign dma_s_rdata = 32'b0; -// assign dma_s_rresp = 2'b0; -// assign dma_s_rlast = 1'b0; -// assign dma_s_rvalid = 1'b0; -// assign dma_s_awready = 1'b1; -// assign dma_s_wready = 1'b1; -// assign dma_s_bid = 5'b0; -// assign dma_s_bresp = 2'b0; -// assign dma_s_bvalid = 1'b0; - wire [31:0] cdma_s_awaddr; wire [2:0] cdma_s_awprot; wire cdma_s_awvalid; @@ -1600,78 +1563,85 @@ u_axi_axil_adapter( .m_axil_rready(cdma_s_rready) ); -snix_axi_cdma #( - .ADDR_WIDTH (32 ), - .DATA_WIDTH (32 ), - .AXIL_ADDR_WIDTH (32 ), - .AXIL_DATA_WIDTH (32 ), - .ID_WIDTH (4 ), - .USER_WIDTH (1 )) -u_snix_axi_cdma( - .clk (sys_clk ), - .rst_n (sys_resetn ), - .s_axil_awaddr (cdma_s_awaddr ), - .s_axil_awvalid (cdma_s_awvalid ), - .s_axil_awready (cdma_s_awready ), - .s_axil_wdata (cdma_s_wdata ), - .s_axil_wstrb (cdma_s_wstrb ), - .s_axil_wvalid (cdma_s_wvalid ), - .s_axil_wready (cdma_s_wready ), - .s_axil_bresp (cdma_s_bresp ), - .s_axil_bvalid (cdma_s_bvalid ), - .s_axil_bready (cdma_s_bready ), - .s_axil_araddr (cdma_s_araddr ), - .s_axil_arvalid (cdma_s_arvalid ), - .s_axil_arready (cdma_s_arready ), - .s_axil_rdata (cdma_s_rdata ), - .s_axil_rresp (cdma_s_rresp ), - .s_axil_rvalid (cdma_s_rvalid ), - .s_axil_rready (cdma_s_rready ), +// 8 通道 DMA +snix_axil_cdma_mux #( + .ADDR_WIDTH (32), + .DATA_WIDTH (32), // 适配你的 32-bit 总线 + .AXIL_ADDR_WIDTH (32), + .AXIL_DATA_WIDTH (32), + .ID_WIDTH (4), // 匹配 Crossbar 的 Master ID 宽度 + .USER_WIDTH (1), + .PORTS (8), + .FIFO_DEPTH (64) // 8 个独立通道 +) u_snix_axil_cdma_mux_8ch ( + .clk (sys_clk), + .rst_n (sys_resetn), // 低电平复位 - .mm2mm_awid (dma_m_awid ), - .mm2mm_awaddr (dma_m_awaddr ), - .mm2mm_awlen (dma_m_awlen ), - .mm2mm_awsize (dma_m_awsize ), - .mm2mm_awburst (dma_m_awburst ), - .mm2mm_awlock (dma_m_awlock ), - .mm2mm_awcache (dma_m_awcache ), - .mm2mm_awprot (dma_m_awprot ), - .mm2mm_awqos ( ), - .mm2mm_awuser ( ), - .mm2mm_awvalid (dma_m_awvalid ), - .mm2mm_awready (dma_m_awready ), - .mm2mm_wdata (dma_m_wdata ), - .mm2mm_wstrb (dma_m_wstrb ), - .mm2mm_wlast (dma_m_wlast ), - .mm2mm_wuser ( ), - .mm2mm_wvalid (dma_m_wvalid ), - .mm2mm_wready (dma_m_wready ), - .mm2mm_bid (dma_m_bid ), - .mm2mm_bresp (dma_m_bresp ), - .mm2mm_buser (1'b0), - .mm2mm_bvalid (dma_m_bvalid ), - .mm2mm_bready (dma_m_bready ), - .mm2mm_arid (dma_m_arid ), - .mm2mm_araddr (dma_m_araddr ), - .mm2mm_arlen (dma_m_arlen ), - .mm2mm_arsize (dma_m_arsize ), - .mm2mm_arburst (dma_m_arburst ), - .mm2mm_arlock (dma_m_arlock ), - .mm2mm_arcache (dma_m_arcache ), - .mm2mm_arprot (dma_m_arprot ), - .mm2mm_arqos ( ), - .mm2mm_aruser ( ), - .mm2mm_arvalid (dma_m_arvalid ), - .mm2mm_arready (dma_m_arready ), - .mm2mm_rid (dma_m_rid ), - .mm2mm_rdata (dma_m_rdata ), - .mm2mm_rresp (dma_m_rresp ), - .mm2mm_rlast (dma_m_rlast ), - .mm2mm_ruser (1'b0), - .mm2mm_rvalid (dma_m_rvalid ), - .mm2mm_rready (dma_m_rready ), + // AXI-Lite 从机接口 (接 CPU 发来的配置请求) + .s_axil_awaddr (cdma_s_awaddr), + .s_axil_awvalid (cdma_s_awvalid), + .s_axil_awready (cdma_s_awready), + .s_axil_wdata (cdma_s_wdata), + .s_axil_wstrb (cdma_s_wstrb), + .s_axil_wvalid (cdma_s_wvalid), + .s_axil_wready (cdma_s_wready), + .s_axil_bresp (cdma_s_bresp), + .s_axil_bvalid (cdma_s_bvalid), + .s_axil_bready (cdma_s_bready), + .s_axil_araddr (cdma_s_araddr), + .s_axil_arvalid (cdma_s_arvalid), + .s_axil_arready (cdma_s_arready), + .s_axil_rdata (cdma_s_rdata), + .s_axil_rresp (cdma_s_rresp), + .s_axil_rvalid (cdma_s_rvalid), + .s_axil_rready (cdma_s_rready), - .dma_finish (dma_finish) + // AXI4 主机接口 (接 Crossbar 去搬运数据) + .mm2mm_awid (dma_m_awid), + .mm2mm_awaddr (dma_m_awaddr), + .mm2mm_awlen (dma_m_awlen), + .mm2mm_awsize (dma_m_awsize), + .mm2mm_awburst (dma_m_awburst), + .mm2mm_awlock (dma_m_awlock), + .mm2mm_awcache (dma_m_awcache), + .mm2mm_awprot (dma_m_awprot), + .mm2mm_awqos (), // 悬空即可 + .mm2mm_awuser (), // 悬空即可 + .mm2mm_awvalid (dma_m_awvalid), + .mm2mm_awready (dma_m_awready), + .mm2mm_wdata (dma_m_wdata), + .mm2mm_wstrb (dma_m_wstrb), + .mm2mm_wlast (dma_m_wlast), + .mm2mm_wuser (), // 悬空即可 + .mm2mm_wvalid (dma_m_wvalid), + .mm2mm_wready (dma_m_wready), + .mm2mm_bid (dma_m_bid), + .mm2mm_bresp (dma_m_bresp), + .mm2mm_buser (1'b0), + .mm2mm_bvalid (dma_m_bvalid), + .mm2mm_bready (dma_m_bready), + .mm2mm_arid (dma_m_arid), + .mm2mm_araddr (dma_m_araddr), + .mm2mm_arlen (dma_m_arlen), + .mm2mm_arsize (dma_m_arsize), + .mm2mm_arburst (dma_m_arburst), + .mm2mm_arlock (dma_m_arlock), + .mm2mm_arcache (dma_m_arcache), + .mm2mm_arprot (dma_m_arprot), + .mm2mm_arqos (), // 悬空即可 + .mm2mm_aruser (), // 悬空即可 + .mm2mm_arvalid (dma_m_arvalid), + .mm2mm_arready (dma_m_arready), + .mm2mm_rid (dma_m_rid), + .mm2mm_rdata (dma_m_rdata), + .mm2mm_rresp (dma_m_rresp), + .mm2mm_rlast (dma_m_rlast), + .mm2mm_ruser (1'b0), + .mm2mm_rvalid (dma_m_rvalid), + .mm2mm_rready (dma_m_rready), + + // 全局中断输出 + .dma_finish (dma_finish) ); endmodule