feat(confreg): add interrupt control

rtl/ip/confreg/confreg.v

@@ -351,6 +351,68 @@ end
 
 //-------------------------------{int_ctrl}begin----------------------------//
 //add your code
+wire [31:0] int_in;
+wire [31:0] int_out;
+
+wire write_int_en   = w_enter & (buf_addr[15:0] == (`CONFREG_INT_ADDR + 16'h0));
+wire write_int_edge = w_enter & (buf_addr[15:0] == (`CONFREG_INT_ADDR + 16'h4));
+wire write_int_pol  = w_enter & (buf_addr[15:0] == (`CONFREG_INT_ADDR + 16'h8));
+wire write_int_clr  = w_enter & (buf_addr[15:0] == (`CONFREG_INT_ADDR + 16'hc));
+wire write_int_set  = w_enter & (buf_addr[15:0] == (`CONFREG_INT_ADDR + 16'h10));
+
+always @(posedge aclk) begin
+    if (!aresetn) begin
+        confreg_int_en   <= 32'h0;
+        confreg_int_edge <= 32'h0;
+        confreg_int_pol  <= 32'h0;
+    end else begin
+        if (write_int_en)   confreg_int_en   <= s_wdata;
+        if (write_int_edge) confreg_int_edge <= s_wdata;
+        if (write_int_pol)  confreg_int_pol  <= s_wdata;
+    end
+end
+
+always @(posedge aclk) begin
+    if (!aresetn) begin
+        confreg_int_clr <= 32'h0;
+        confreg_int_set <= 32'h0;
+    end else begin
+        confreg_int_clr <= write_int_clr ? s_wdata : 32'h0;
+        confreg_int_set <= write_int_set ? s_wdata : 32'h0;
+    end
+end
+
+assign int_in = {27'b0, timer_int, touch_btn_data};
+
+int_ctrl u_int_ctrl (
+    .clk       (aclk),
+    .resetn    (aresetn),
+    .int_en    (confreg_int_en),
+    .int_edge  (confreg_int_edge),
+    .int_pol   (confreg_int_pol),
+    .int_in    (int_in),
+    .int_clr   (confreg_int_clr),
+    .int_set   (confreg_int_set),
+    .int_out   (int_out)
+);
+
+assign confreg_int_state = int_out;
+
+// int_out 进行或操作，再经过延迟打拍处理
+reg int_out_or_q1;
+reg int_out_or_q2;
+
+always @(posedge aclk) begin
+    if (!aresetn) begin
+        int_out_or_q1 <= 1'b0;
+        int_out_or_q2 <= 1'b0;
+    end else begin
+        int_out_or_q1 <= |int_out;         
+        int_out_or_q2 <= int_out_or_q1;     
+    end
+end
+
+assign confreg_int = int_out_or_q2;
 
 //--------------------------------{int_ctrl}end-----------------------------//