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sim/mycpu_tb.v
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230
sim/mycpu_tb.v
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/*------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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Copyright (c) 2016, Loongson Technology Corporation Limited.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation and/or
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other materials provided with the distribution.
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3. Neither the name of Loongson Technology Corporation Limited nor the names of
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its contributors may be used to endorse or promote products derived from this
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software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
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TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--------------------------------------------------------------------------------
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------------------------------------------------------------------------------*/
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`timescale 1ns / 1ps
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`include "config.h"
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// `define FFT_OUTPUT_TXT
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`define UART_PSEL u_soc_top.u_axi_uart_controller.uart0.PSEL
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`define UART_PENBLE u_soc_top.u_axi_uart_controller.uart0.PENABLE
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`define UART_PWRITE u_soc_top.u_axi_uart_controller.uart0.PWRITE
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`define UART_WADDR u_soc_top.u_axi_uart_controller.uart0.PADDR[7:0]
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`define UART_WDATA u_soc_top.u_axi_uart_controller.uart0.PWDATA[7:0]
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`define END_PC 32'h1c000200
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module tb_top( );
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reg reset;
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reg clk;
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reg [3:0] touch_btn;
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reg [31:0] dip_sw;
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wire UART_RX;
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wire UART_TX;
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wire [2:0] video_red;
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wire [2:0] video_green;
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wire [1:0] video_blue;
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wire video_hsync;
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wire video_vsync;
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wire video_clk;
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wire video_de;
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wire [15:0] leds;
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wire [7:0] dpy0;
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wire [7:0] dpy1;
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wire [19:0] base_ram_addr;
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wire [ 3:0] base_ram_be_n;
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wire base_ram_ce_n;
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wire base_ram_oe_n;
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wire base_ram_we_n;
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wire [19:0] ext_ram_addr;
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wire [ 3:0] ext_ram_be_n;
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wire ext_ram_ce_n;
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wire ext_ram_oe_n;
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wire ext_ram_we_n;
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wire [31:0] base_ram_data;
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wire [31:0] ext_ram_data;
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//产生时钟与复位信号
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initial begin
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clk = 1'b0;
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reset = 1'b1;
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dip_sw = 32'h0;
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#2000;
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reset = 1'b0;
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end
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always #10 clk=~clk;
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//产生按键信号
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initial begin
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touch_btn = 4'h0;
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dip_sw = 32'h0000_abcd;
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#3000000;
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#100000
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touch_btn = 4'b0001;
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#50
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touch_btn = 4'b0000;
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#100000
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touch_btn = 4'b0010;
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#50
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touch_btn = 4'b0000;
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#100000
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touch_btn = 4'b0100;
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#50
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touch_btn = 4'b0000;
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#100000
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touch_btn = 4'b1000;
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#50
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touch_btn = 4'b0000;
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end
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soc_top #(.SIMULATION(1'b1)) u_soc_top (
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.clk ( clk ),
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.reset ( reset ),
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.touch_btn ( touch_btn ),
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.dip_sw ( dip_sw ),
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.video_red ( video_red ),
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.video_green ( video_green ),
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.video_blue ( video_blue ),
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.video_hsync ( video_hsync ),
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.video_vsync ( video_vsync ),
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.video_clk ( video_clk ),
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.video_de ( video_de ),
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.leds ( leds ),
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.dpy0 ( dpy0 ),
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.dpy1 ( dpy1 ),
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.base_ram_addr ( base_ram_addr ),
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.base_ram_be_n ( base_ram_be_n ),
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.base_ram_ce_n ( base_ram_ce_n ),
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.base_ram_oe_n ( base_ram_oe_n ),
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.base_ram_we_n ( base_ram_we_n ),
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.ext_ram_addr ( ext_ram_addr ),
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.ext_ram_be_n ( ext_ram_be_n ),
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.ext_ram_ce_n ( ext_ram_ce_n ),
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.ext_ram_oe_n ( ext_ram_oe_n ),
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.ext_ram_we_n ( ext_ram_we_n ),
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.base_ram_data ( base_ram_data ),
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.ext_ram_data ( ext_ram_data ),
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.UART_RX ( UART_RX ),
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.UART_TX ( UART_TX )
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);
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sram_sp #(
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.AW ( 18 ),
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.Init_File(`SRAM_Init_File))
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base_sram_sp (
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.ram_addr ( base_ram_addr ),
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.ram_be_n ( base_ram_be_n ),
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.ram_ce_n ( base_ram_ce_n ),
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.ram_oe_n ( base_ram_oe_n ),
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.ram_we_n ( base_ram_we_n ),
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.ram_data ( base_ram_data )
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);
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sram_sp #(
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.AW ( 18 ),
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.Init_File(`SRAM_Init_File))
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ext_sram_sp (
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.ram_addr ( ext_ram_addr ),
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.ram_be_n ( ext_ram_be_n ),
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.ram_ce_n ( ext_ram_ce_n ),
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.ram_oe_n ( ext_ram_oe_n ),
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.ram_we_n ( ext_ram_we_n ),
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.ram_data ( ext_ram_data )
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);
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//模拟串口打印
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wire uart_display;
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wire [7:0] uart_data;
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wire uart_wen;
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assign uart_wen = (`UART_PSEL == 1'b1) && (`UART_PENBLE == 1'b1) && (`UART_PWRITE == 1'b1);
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assign uart_display = (uart_wen == 1'b1) && (`UART_WADDR == 8'h0);
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assign uart_data = `UART_WDATA;
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always @(posedge clk)
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begin
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if(uart_display)
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begin
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if(uart_data==8'hff)
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begin
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;//$finish;
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end
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else
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begin
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$write("%c",uart_data);
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end
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end
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end
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//仿真结束
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wire [31:0] debug_wb_pc;
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assign debug_wb_pc = u_soc_top.debug_wb_pc;
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wire test_end = debug_wb_pc==`END_PC;
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always @(posedge u_soc_top.cpu_clk)
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begin
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if (!u_soc_top.cpu_resetn) begin
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end
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else if(test_end) begin
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$display("==============================================================");
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$display("Test end!");
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$finish;
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end
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end
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//FFT测试结果输出
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`ifdef FFT_OUTPUT_TXT
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integer fft_output_re;
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integer fft_output_im;
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initial begin
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fft_output_re = $fopen("../../../../../../python/fft512_output_re.txt", "w");
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fft_output_im = $fopen("../../../../../../python/fft512_output_im.txt", "w");
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forever begin
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@(posedge u_soc_top.u_axi_fft_top.u_axi_fft_wrap.aclk);
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if(u_soc_top.u_axi_fft_top.u_axi_fft_wrap.valid_out) begin
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$fwrite(fft_output_re, "%04h\n", u_soc_top.u_axi_fft_top.u_axi_fft_wrap.y_re);
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$fwrite(fft_output_im, "%04h\n", u_soc_top.u_axi_fft_top.u_axi_fft_wrap.y_im);
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end
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end
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end
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`endif
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endmodule
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52
sim/sram.v
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52
sim/sram.v
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`timescale 1ns/100ps
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module sram_sp #(
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parameter AW = 16,
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parameter Init_File = "none"
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)
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(
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inout [31:0] ram_data, //BaseRAM数据，低8位与CPLD串口控制器共享
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input [19:0] ram_addr, //BaseRAM地址
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input [ 3:0] ram_be_n, //BaseRAM字节使能，低有效。如果不使用字节使能，请保持为0
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input ram_ce_n, //BaseRAM片选，低有效
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input ram_oe_n, //BaseRAM读使能，低有效
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input ram_we_n //BaseRAM写使能，低有效
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);
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localparam AWT = ((1<<(AW-0))-1);
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reg [31:0] BRAM [AWT:0];
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initial begin
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if(Init_File != "none") begin
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$readmemb(Init_File,BRAM);
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end
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end
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reg [AW-1:0] addr_q1;
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wire [3:0] write_enable;
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assign write_enable[3:0] = (~ram_be_n) & {4{(~ram_ce_n) & (~ram_we_n)}};
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always@(posedge write_enable[0]) begin
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#10;
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if(~ram_be_n[0]) BRAM[ram_addr][7:0] <= ram_data[7:0];
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end
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always@(posedge write_enable[1]) begin
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#10;
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if(~ram_be_n[1]) BRAM[ram_addr][15:8] <= ram_data[15:8];
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end
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always@(posedge write_enable[2]) begin
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#10;
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if(~ram_be_n[2]) BRAM[ram_addr][23:16] <= ram_data[23:16];
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end
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always@(posedge write_enable[3]) begin
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#10;
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if(~ram_be_n[3]) BRAM[ram_addr][31:24] <= ram_data[31:24];
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end
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wire [31:0] RDATA = BRAM[ram_addr];
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assign ram_data = ((~ram_ce_n) & (~ram_oe_n)) ? RDATA : 32'hzzzzzzzz;
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endmodule
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