fallensigh/ciciec2026_loongson
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FallenSigh
2026-04-12 22:20:18 +08:00
commit 190c2edbb2
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sdk/software/examples/dhrystone/Makefile Normal file
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TARGET = dhrystone
CFLAGS += -O3 -g -G8 -DTIME -DNumber_Of_Runs=1
#根据SIMU宏选择串口波特率,0：FPGA上板；1：仿真
CFLAGS += -DSIMU=0
C_SRCS := $(wildcard ./*.c )
INCLUDES := -I.
OBJDIR = obj
COMMON_DIR = ../../bsp
GCC_DIR=../../../toolchains/loongson-gnu-toolchain-8.3-x86_64-loongarch32r-linux-gnusf-v2.0
PICOLIBC_DIR=../../../toolchains/picolibc
include ../../bsp/common.mk