initial commit
This commit is contained in:
103
sdk/software/bsp/env/convert.c
vendored
Normal file
103
sdk/software/bsp/env/convert.c
vendored
Normal file
@@ -0,0 +1,103 @@
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
|
||||
void binary_out(FILE* out,unsigned char* mem)
|
||||
{
|
||||
char tmp;
|
||||
unsigned char num[8];
|
||||
int i;
|
||||
int j;
|
||||
|
||||
num[0] = 1;
|
||||
num[1] = 2;
|
||||
num[2] = 4;
|
||||
num[3] = 8;
|
||||
num[4] = 16;
|
||||
num[5] = 32;
|
||||
num[6] = 64;
|
||||
num[7] = 128;
|
||||
for(i=3;i>=0;i--)
|
||||
{
|
||||
for(j=7;j>=0;j--)
|
||||
{
|
||||
if( (mem[i] & num[j] ) != 0)
|
||||
tmp = '1';
|
||||
else
|
||||
tmp = '0';
|
||||
fprintf(out,"%c",tmp);
|
||||
}
|
||||
}
|
||||
fprintf(out,"\n");
|
||||
return;
|
||||
}
|
||||
|
||||
int main(int argc, char** argv)
|
||||
{
|
||||
FILE *in;
|
||||
FILE *out;
|
||||
|
||||
if(argc < 3){
|
||||
fprintf(stderr, "Usage: convert main.bin directory\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
char str_bin[256];
|
||||
char str_coe[256], str_mif[256], str_vlog[256];
|
||||
strncpy(str_bin, argv[2], 256);
|
||||
strncpy(str_coe, argv[2], 256);
|
||||
strncpy(str_mif, argv[2], 256);
|
||||
strncpy(str_vlog,argv[2], 256);
|
||||
strncat(str_bin, argv[1], 255);
|
||||
strncat(str_coe, "axi_ram.coe", 255);
|
||||
strncat(str_mif, "axi_ram.mif", 255);
|
||||
strncat(str_vlog,"rom.vlog" , 255);
|
||||
//printf("%s\n%s\n%s\n%s\n%s\n%s\n", str_bin, str_data, str_inst_coe, str_inst_mif, str_data_coe, str_data_mif);
|
||||
|
||||
int i,j,k;
|
||||
unsigned char mem[32];
|
||||
|
||||
in = fopen(str_bin, "rb");
|
||||
out = fopen(str_coe,"w");
|
||||
|
||||
fprintf(out, "memory_initialization_radix = 16;\n");
|
||||
fprintf(out, "memory_initialization_vector =\n");
|
||||
while(!feof(in)) {
|
||||
if(fread(mem,1,4,in)!=4) {
|
||||
fprintf(out, "%02x%02x%02x%02x\n", mem[3], mem[2], mem[1], mem[0]);
|
||||
break;
|
||||
}
|
||||
fprintf(out, "%02x%02x%02x%02x\n", mem[3], mem[2], mem[1],mem[0]);
|
||||
}
|
||||
fclose(in);
|
||||
fclose(out);
|
||||
|
||||
in = fopen(str_bin, "rb");
|
||||
out = fopen(str_mif,"w");
|
||||
|
||||
while(!feof(in)) {
|
||||
if(fread(mem,1,4,in)!=4) {
|
||||
binary_out(out,mem);
|
||||
break;
|
||||
}
|
||||
binary_out(out,mem);
|
||||
}
|
||||
fclose(in);
|
||||
fclose(out);
|
||||
|
||||
in = fopen(str_bin, "rb");
|
||||
out = fopen(str_vlog,"w");
|
||||
|
||||
fprintf(out,"@1c000000\n");
|
||||
while(!feof(in)) {
|
||||
if (fread(mem,1,1,in) != 1) {
|
||||
fprintf(out,"%02x\n", mem[0]);
|
||||
break;
|
||||
}
|
||||
fprintf(out,"%02x\n", mem[0]);
|
||||
}
|
||||
fclose(in);
|
||||
fclose(out);
|
||||
|
||||
return 0;
|
||||
}
|
||||
182
sdk/software/bsp/env/script.lds
vendored
Normal file
182
sdk/software/bsp/env/script.lds
vendored
Normal file
@@ -0,0 +1,182 @@
|
||||
OUTPUT_ARCH(loongarch)
|
||||
ENTRY(_start)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
isram (rwxai) : ORIGIN = 0x1c000000, LENGTH = 512K
|
||||
dsram (rwxai) : ORIGIN = 0x1c080000, LENGTH = 512K
|
||||
}
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 64K;
|
||||
.init :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.init)))
|
||||
} >isram AT>isram
|
||||
.ilalign :
|
||||
{
|
||||
. = ALIGN(16);
|
||||
PROVIDE( _isram_lma = . );
|
||||
} >isram AT>isram
|
||||
.ialign :
|
||||
{
|
||||
PROVIDE( _isram = . );
|
||||
} >isram AT>isram
|
||||
.text :
|
||||
{
|
||||
_ftext = . ;
|
||||
*(.text.unlikely .text.unlikely.*)
|
||||
*(.text.startup .text.startup.*)
|
||||
*(.text .text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
|
||||
/* section information for finsh shell */
|
||||
. = ALIGN(4);
|
||||
__fsymtab_start = .;
|
||||
KEEP(*(FSymTab))
|
||||
__fsymtab_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__vsymtab_start = .;
|
||||
KEEP(*(VSymTab))
|
||||
__vsymtab_end = .;
|
||||
|
||||
/* section information for utest */
|
||||
. = ALIGN(4);
|
||||
__rt_utest_tc_tab_start = .;
|
||||
KEEP(*(UtestTcTab))
|
||||
__rt_utest_tc_tab_end = .;
|
||||
|
||||
/* section information for at server */
|
||||
. = ALIGN(4);
|
||||
__rtatcmdtab_start = .;
|
||||
KEEP(*(RtAtCmdTab))
|
||||
__rtatcmdtab_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
/* section information for initial. */
|
||||
. = ALIGN(4);
|
||||
__rt_init_start = .;
|
||||
KEEP(*(SORT(.rti_fn*)))
|
||||
__rt_init_end = .;
|
||||
|
||||
} >isram AT>isram
|
||||
.fini :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.fini)))
|
||||
} >isram AT>isram
|
||||
. = ALIGN(16);
|
||||
PROVIDE (__etext = .);
|
||||
PROVIDE (_etext = .);
|
||||
PROVIDE (etext = .);
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >isram AT>isram
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >isram AT>isram
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >isram AT>isram
|
||||
.ctors :
|
||||
{
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
} >isram AT>isram
|
||||
.dtors :
|
||||
{
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
} >isram AT>isram
|
||||
|
||||
. = ALIGN(16);
|
||||
.ex_table_base :
|
||||
{
|
||||
_ex_table_base_start = .;
|
||||
. = 0x500;
|
||||
_ex_table_base_end = .;
|
||||
} >isram AT>isram
|
||||
|
||||
. = ALIGN(16);
|
||||
PROVIDE( _eisram = . );
|
||||
|
||||
.lalign :
|
||||
{
|
||||
. = ALIGN(16);
|
||||
PROVIDE( _data_lma = . );
|
||||
} >isram AT>isram
|
||||
.dalign :
|
||||
{
|
||||
. = ALIGN(16);
|
||||
PROVIDE( _data = . );
|
||||
} >dsram AT>isram
|
||||
.data :
|
||||
{
|
||||
*(.rdata)
|
||||
*(.rodata .rodata.*)
|
||||
rodata_end = .;
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
. = ALIGN(16);
|
||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
||||
*(.sdata .sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
. = ALIGN(16);
|
||||
*(.srodata.cst16)
|
||||
*(.srodata.cst8)
|
||||
*(.srodata.cst4)
|
||||
*(.srodata.cst2)
|
||||
*(.srodata .srodata.*)
|
||||
} >dsram AT>isram
|
||||
. = ALIGN(16);
|
||||
PROVIDE( _edata = . );
|
||||
PROVIDE( edata = . );
|
||||
PROVIDE( _fbss = . );
|
||||
.bss :
|
||||
{
|
||||
PROVIDE( __bss_start = . );
|
||||
*(.sbss*)
|
||||
*(.sbss.*)
|
||||
*(.dynsbss)
|
||||
*(.scommon)
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.dynbss)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(16);
|
||||
} >dsram AT>dsram
|
||||
. = ALIGN(16);
|
||||
PROVIDE( _end = . );
|
||||
PROVIDE( end = . );
|
||||
PROVIDE (__heap_start = _end);
|
||||
.stack ORIGIN(dsram) + LENGTH(dsram) - __stack_size :
|
||||
{
|
||||
PROVIDE( _heap_end = . );
|
||||
PROVIDE (__heap_end = _heap_end);
|
||||
PROVIDE (__heap_size = __heap_end - __heap_start);
|
||||
. = __stack_size;
|
||||
PROVIDE( _stack = . );
|
||||
} >dsram AT>dsram
|
||||
}
|
||||
182
sdk/software/bsp/env/start.S
vendored
Normal file
182
sdk/software/bsp/env/start.S
vendored
Normal file
@@ -0,0 +1,182 @@
|
||||
#include "regdef.h"
|
||||
#include "uart_print.h"
|
||||
#include "handler.h"
|
||||
|
||||
.extern UART_BASE
|
||||
|
||||
.section .init
|
||||
.globl _start
|
||||
.type _start,@function
|
||||
|
||||
_start:
|
||||
|
||||
##init regs
|
||||
addi.w $r1,zero,0x0; addi.w $r2,zero,0x0; addi.w $r3,zero,0x0; addi.w $r4,zero,0x0;
|
||||
addi.w $r5,zero,0x0; addi.w $r6,zero,0x0; addi.w $r7,zero,0x0; addi.w $r8,zero,0x0;
|
||||
addi.w $r9,zero,0x0; addi.w $r10,zero,0x0; addi.w $r11,zero,0x0; addi.w $r12,zero,0x0;
|
||||
addi.w $r13,zero,0x0; addi.w $r14,zero,0x0; addi.w $r15,zero,0x0; addi.w $r16,zero,0x0;
|
||||
addi.w $r17,zero,0x0; addi.w $r18,zero,0x0; addi.w $r19,zero,0x0; addi.w $r20,zero,0x0;
|
||||
addi.w $r21,zero,0x0; addi.w $r22,zero,0x0; addi.w $r23,zero,0x0; addi.w $r24,zero,0x0;
|
||||
addi.w $r25,zero,0x0; addi.w $r26,zero,0x0; addi.w $r27,zero,0x0; addi.w $r28,zero,0x0;
|
||||
addi.w $r29,zero,0x0; addi.w $r30,zero,0x0; addi.w $r31,zero,0x0;
|
||||
|
||||
#if has_cache==1
|
||||
# invalid the old inst in icache and old data in dcache by index
|
||||
li.w t0,0x0
|
||||
#li.w t2,0x100
|
||||
li.w t2, cache_index_depth
|
||||
1:
|
||||
#slli.w t1, t0, 0x4
|
||||
slli.w t1, t0, cache_offset_width
|
||||
#if cache_way==1
|
||||
cacop 0x00, t1, 0x0
|
||||
cacop 0x01, t1, 0x0
|
||||
#elif cache_way==2
|
||||
cacop 0x00, t1, 0x0
|
||||
cacop 0x00, t1, 0x1
|
||||
cacop 0x01, t1, 0x0
|
||||
cacop 0x01, t1, 0x1
|
||||
#elif cache_way==4
|
||||
cacop 0x00, t1, 0x0
|
||||
cacop 0x00, t1, 0x1
|
||||
cacop 0x00, t1, 0x2
|
||||
cacop 0x00, t1, 0x3
|
||||
cacop 0x01, t1, 0x0
|
||||
cacop 0x01, t1, 0x1
|
||||
cacop 0x01, t1, 0x2
|
||||
cacop 0x01, t1, 0x3
|
||||
#endif
|
||||
addi.w t0, t0, 0x1
|
||||
bne t0, t2, 1b
|
||||
#else
|
||||
/* disable cache */
|
||||
li.w $r12,0x1
|
||||
csrwr $r12,0x101
|
||||
#endif
|
||||
|
||||
/* open da mode */
|
||||
li.w $r12,0x8
|
||||
li.w $r13,0x18
|
||||
csrxchg $r12,$r13,0x0
|
||||
|
||||
/* init dmw */
|
||||
csrwr $r0,0x180
|
||||
csrwr $r0,0x181
|
||||
li.w $r12,0x09
|
||||
csrwr $r12,0x180
|
||||
li.w $r12,0xa0000009
|
||||
csrwr $r12,0x181
|
||||
|
||||
/* open pg mode */
|
||||
li.w $r12,0x10
|
||||
li.w $r13,0x18
|
||||
csrxchg $r12,$r13,0x0
|
||||
|
||||
/* load data section */
|
||||
la.local t0, _data_lma
|
||||
la.local t1, _data
|
||||
la.local t2, _edata
|
||||
bgeu t1, t2, 2f
|
||||
1:
|
||||
ld.w t3, t0, 0
|
||||
st.w t3, t1, 0
|
||||
addi.w t0, t0, 4
|
||||
addi.w t1, t1, 4
|
||||
bltu t1, t2, 1b
|
||||
2:
|
||||
|
||||
/* clear bss section */
|
||||
la.local t0, __bss_start
|
||||
la.local t1, _end
|
||||
bgeu t0, t1, 2f
|
||||
1:
|
||||
st.w $r0, t0, 0
|
||||
addi.w t0, t0, 4
|
||||
bltu t0, t1, 1b
|
||||
2:
|
||||
|
||||
/* enable cache */
|
||||
#if has_cache==1
|
||||
li.w $r12,0x19
|
||||
csrwr $r12,0x180
|
||||
#else
|
||||
|
||||
#endif
|
||||
|
||||
/* init UART */
|
||||
la.local t0, UART_BASE
|
||||
ld.w t1, t0, 0
|
||||
#WRITE(li.wne,OFS_FIFO,FIFO_ENABLE|FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER_0);
|
||||
li.w t2, 0x07
|
||||
st.b t2, t1, 2
|
||||
#WRITE(li.wne,OFS_LINE_CONTROL, 0x80);
|
||||
li.w t2, 0x80
|
||||
st.b t2, t1, 3
|
||||
#WRITE(li.wne,OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
|
||||
li.w t2, 0x00
|
||||
st.b t2, t1, 1
|
||||
#WRITE(li.wne,OFS_DIVISOR_LSB, divisor & 0xff);
|
||||
li.w t3, 0xbf20f500
|
||||
ld.w t3, t3, 0
|
||||
li.w t2, 0x1b
|
||||
beq zero, t3, 1f
|
||||
li.w t2, 0x1
|
||||
1:
|
||||
st.b t2, t1, 0
|
||||
#WRITE(li.wne,OFS_DATA_FORMAT, data | parity | stop);
|
||||
li.w t2, 0x3
|
||||
st.b t2, t1, 3
|
||||
#WRITE(li.wne,OFS_MODEM_CONTROL,0);
|
||||
li.w t2, 0x0
|
||||
st.b t2, t1, 4
|
||||
|
||||
/* init exception */
|
||||
#ifdef RTThread
|
||||
la.local t0, rtthread_irq_entry
|
||||
#else
|
||||
la.local t0, trap_handler
|
||||
#endif
|
||||
csrwr t0, csr_eentry
|
||||
|
||||
#clear int
|
||||
li.w t1, 0x1
|
||||
csrwr t1, csr_ticlr
|
||||
|
||||
#enable int
|
||||
li.w t1, 0x4
|
||||
#ifdef RTThread
|
||||
csrxchg zero, t1, csr_crmd
|
||||
#else
|
||||
csrxchg t1, t1, csr_crmd
|
||||
#endif
|
||||
csrwr zero, csr_prmd
|
||||
li.w t1, 0x1fff
|
||||
csrwr zero, csr_ecfg
|
||||
csrwr t1, csr_ecfg
|
||||
|
||||
|
||||
la.local sp, _stack
|
||||
|
||||
/* argc = argv = 0 */
|
||||
li.w a0, 0
|
||||
li.w a1, 0
|
||||
|
||||
#ifdef RTThread
|
||||
bl entry
|
||||
#else
|
||||
bl main
|
||||
#endif
|
||||
|
||||
/*tail exit*/
|
||||
bl _myexit
|
||||
1:
|
||||
b 1b
|
||||
|
||||
.globl _myexit
|
||||
.org 0x200
|
||||
_myexit:
|
||||
1:
|
||||
b 1b
|
||||
|
||||
|
||||
|
||||
188
sdk/software/bsp/env/trap_handler.S
vendored
Normal file
188
sdk/software/bsp/env/trap_handler.S
vendored
Normal file
@@ -0,0 +1,188 @@
|
||||
#include "regdef.h"
|
||||
|
||||
.macro TRAP_ENTRY_SETJMP
|
||||
addi.w sp, sp, -124
|
||||
|
||||
st.w ra, sp, 120
|
||||
st.w tp, sp, 116
|
||||
st.w sp, sp, 112
|
||||
st.w a0, sp, 108
|
||||
st.w a1, sp, 104
|
||||
st.w a2, sp, 100
|
||||
st.w a3, sp, 96
|
||||
st.w a4, sp, 92
|
||||
st.w a5, sp, 88
|
||||
st.w a6, sp, 84
|
||||
st.w a7, sp, 80
|
||||
st.w t0, sp, 76
|
||||
st.w t1, sp, 72
|
||||
st.w t2, sp, 68
|
||||
st.w t3, sp, 64
|
||||
st.w t4, sp, 60
|
||||
st.w t5, sp, 56
|
||||
st.w t6, sp, 52
|
||||
st.w t7, sp, 48
|
||||
st.w t8, sp, 44
|
||||
st.w $r21, sp,40
|
||||
st.w fp, sp, 36
|
||||
st.w s0, sp, 32
|
||||
st.w s1, sp, 28
|
||||
st.w s2, sp, 24
|
||||
st.w s3, sp, 20
|
||||
st.w s4, sp, 16
|
||||
st.w s5, sp, 12
|
||||
st.w s6, sp, 8
|
||||
st.w s7, sp, 4
|
||||
st.w s8, sp, 0
|
||||
|
||||
.endm
|
||||
|
||||
.macro TRAP_EXIT_LONGJMP
|
||||
|
||||
ld.w ra, sp, 120
|
||||
ld.w tp, sp, 116
|
||||
ld.w sp, sp, 112
|
||||
ld.w a0, sp, 108
|
||||
ld.w a1, sp, 104
|
||||
ld.w a2, sp, 100
|
||||
ld.w a3, sp, 96
|
||||
ld.w a4, sp, 92
|
||||
ld.w a5, sp, 88
|
||||
ld.w a6, sp, 84
|
||||
ld.w a7, sp, 80
|
||||
ld.w t0, sp, 76
|
||||
ld.w t1, sp, 72
|
||||
ld.w t2, sp, 68
|
||||
ld.w t3, sp, 64
|
||||
ld.w t4, sp, 60
|
||||
ld.w t5, sp, 56
|
||||
ld.w t6, sp, 52
|
||||
ld.w t7, sp, 48
|
||||
ld.w t8, sp, 44
|
||||
ld.w $r21, sp,40
|
||||
ld.w fp, sp, 36
|
||||
ld.w s0, sp, 32
|
||||
ld.w s1, sp, 28
|
||||
ld.w s2, sp, 24
|
||||
ld.w s3, sp, 20
|
||||
ld.w s4, sp, 16
|
||||
ld.w s5, sp, 12
|
||||
ld.w s6, sp, 8
|
||||
ld.w s7, sp, 4
|
||||
ld.w s8, sp, 0
|
||||
|
||||
addi.w sp, sp, 124
|
||||
|
||||
ertn
|
||||
|
||||
.endm
|
||||
|
||||
.section .text
|
||||
.align 6
|
||||
.global trap_handler
|
||||
.weak trap_handler
|
||||
trap_handler:
|
||||
|
||||
TRAP_ENTRY_SETJMP
|
||||
|
||||
csrrd a0, csr_estat
|
||||
csrrd a1, csr_era
|
||||
|
||||
srli.w t0, a0, 16
|
||||
bne zero, t0, is_exceptions
|
||||
andi t0, a0, 0x3FC
|
||||
srli.w t1, t0, 2
|
||||
|
||||
# 根据中断号跳转到相应的处理程序 priority
|
||||
move t2, t1
|
||||
andi t2, t2, 0x1
|
||||
li.w t8, 0x1
|
||||
beq t2, t8, handle_hwi0
|
||||
|
||||
move t2, t1
|
||||
andi t2, t2, 0x2
|
||||
li.w t8, 0x2
|
||||
beq t2, t8, handle_hwi1
|
||||
|
||||
move t2, t1
|
||||
andi t2, t2, 0x4
|
||||
li.w t8, 0x4
|
||||
beq t2, t8, handle_hwi2
|
||||
|
||||
move t2, t1
|
||||
andi t2, t2, 0x8
|
||||
li.w t8, 0x8
|
||||
beq t2, t8, handle_hwi3
|
||||
|
||||
move t2, t1
|
||||
andi t2, t2, 0x10
|
||||
li.w t8, 0x10
|
||||
beq t2, t8, handle_hwi4
|
||||
|
||||
move t2, t1
|
||||
andi t2, t2, 0x20
|
||||
li.w t8, 0x20
|
||||
beq t2, t8, handle_hwi5
|
||||
|
||||
move t2, t1
|
||||
andi t2, t2, 0x40
|
||||
li.w t8, 0x40
|
||||
beq t2, t8, handle_hwi6
|
||||
|
||||
move t2, t1
|
||||
andi t2, t2, 0x80
|
||||
li.w t8, 0x80
|
||||
beq t2, t8, handle_hwi7
|
||||
|
||||
b trap_jump_exit
|
||||
|
||||
is_exceptions:
|
||||
addi.w t8, a1, 4
|
||||
csrwr t8, csr_era
|
||||
1:
|
||||
b 1b
|
||||
|
||||
trap_jump_exit:
|
||||
TRAP_EXIT_LONGJMP
|
||||
|
||||
|
||||
# HWI0 处理程序
|
||||
handle_hwi0:
|
||||
|
||||
bl HWI0_IntrHandler
|
||||
|
||||
b trap_jump_exit
|
||||
|
||||
# HWI1 处理程序
|
||||
handle_hwi1:
|
||||
b trap_jump_exit
|
||||
|
||||
# HWI2 处理程序
|
||||
handle_hwi2:
|
||||
b trap_jump_exit
|
||||
|
||||
# HWI3 处理程序
|
||||
handle_hwi3:
|
||||
b trap_jump_exit
|
||||
|
||||
# HWI4 处理程序
|
||||
handle_hwi4:
|
||||
b trap_jump_exit
|
||||
|
||||
# HWI5 处理程序
|
||||
handle_hwi5:
|
||||
b trap_jump_exit
|
||||
|
||||
# HWI6 处理程序
|
||||
handle_hwi6:
|
||||
b trap_jump_exit
|
||||
|
||||
# HWI7 处理程序
|
||||
handle_hwi7:
|
||||
b trap_jump_exit
|
||||
|
||||
|
||||
.weak HWI0_IntrHandler
|
||||
HWI0_IntrHandler:
|
||||
1:
|
||||
b 1b
|
||||
Reference in New Issue
Block a user