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rtl/ip/ram_wrap/axi_wrap_ram_dp.v Normal file
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/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
module axi_wrap_ram_dp #(
parameter Init_File = "none"
)
(
input aclk,
input aresetn,
//ar
input [4 :0] axi_arid ,
input [31:0] axi_araddr ,
input [7 :0] axi_arlen ,
input [2 :0] axi_arsize ,
input [1 :0] axi_arburst,
input [1 :0] axi_arlock ,
input [3 :0] axi_arcache,
input [2 :0] axi_arprot ,
input axi_arvalid,
output axi_arready,
//r
output [4 :0] axi_rid ,
output [31:0] axi_rdata ,
output [1 :0] axi_rresp ,
output axi_rlast ,
output axi_rvalid ,
input axi_rready ,
//aw
input [4 :0] axi_awid ,
input [31:0] axi_awaddr ,
input [7 :0] axi_awlen ,
input [2 :0] axi_awsize ,
input [1 :0] axi_awburst,
input [1 :0] axi_awlock ,
input [3 :0] axi_awcache,
input [2 :0] axi_awprot ,
input axi_awvalid,
output axi_awready,
//w
input [31:0] axi_wdata ,
input [3 :0] axi_wstrb ,
input axi_wlast ,
input axi_wvalid ,
output axi_wready ,
//b
output [4 :0] axi_bid ,
output [1 :0] axi_bresp ,
output axi_bvalid ,
input axi_bready
);
//ram axi
//ar
wire [4 :0] ram_arid ;
wire [31:0] ram_araddr ;
wire [7 :0] ram_arlen ;
wire [2 :0] ram_arsize ;
wire [1 :0] ram_arburst;
wire [1 :0] ram_arlock ;
wire [3 :0] ram_arcache;
wire [2 :0] ram_arprot ;
wire ram_arvalid;
wire ram_arready;
//r
wire [4 :0] ram_rid ;
wire [31:0] ram_rdata ;
wire [1 :0] ram_rresp ;
wire ram_rlast ;
wire ram_rvalid ;
wire ram_rready ;
//aw
wire [4 :0] ram_awid ;
wire [31:0] ram_awaddr ;
wire [7 :0] ram_awlen ;
wire [2 :0] ram_awsize ;
wire [1 :0] ram_awburst;
wire [1 :0] ram_awlock ;
wire [3 :0] ram_awcache;
wire [2 :0] ram_awprot ;
wire ram_awvalid;
wire ram_awready;
//w
wire [31:0] ram_wdata ;
wire [3 :0] ram_wstrb ;
wire ram_wlast ;
wire ram_wvalid ;
wire ram_wready ;
//b
wire [4 :0] ram_bid ;
wire [1 :0] ram_bresp ;
wire ram_bvalid ;
wire ram_bready ;
//sram signal
wire [31:0] fpga_sram_raddr;
wire [31:0] fpga_sram_rdata;
wire fpga_sram_ren;
wire [31:0] fpga_sram_waddr;
wire [31:0] fpga_sram_wdata;
wire [3:0] fpga_sram_wen;
//ar
assign ram_arid = axi_arid ;
assign ram_araddr = axi_araddr ;
assign ram_arlen = axi_arlen ;
assign ram_arsize = axi_arsize ;
assign ram_arburst = axi_arburst;
assign ram_arlock = axi_arlock ;
assign ram_arcache = axi_arcache;
assign ram_arprot = axi_arprot ;
assign ram_arvalid = axi_arvalid;
assign axi_arready = ram_arready;
//r
assign axi_rid = axi_rvalid ? ram_rid : 5'd0 ;
assign axi_rdata = axi_rvalid ? ram_rdata : 32'd0 ;
assign axi_rresp = axi_rvalid ? ram_rresp : 2'd0 ;
assign axi_rlast = axi_rvalid ? ram_rlast : 1'd0 ;
assign axi_rvalid = ram_rvalid;
assign ram_rready = axi_rready;
//aw
assign ram_awid = axi_awid ;
assign ram_awaddr = axi_awaddr ;
assign ram_awlen = axi_awlen ;
assign ram_awsize = axi_awsize ;
assign ram_awburst = axi_awburst;
assign ram_awlock = axi_awlock ;
assign ram_awcache = axi_awcache;
assign ram_awprot = axi_awprot ;
assign ram_awvalid = axi_awvalid;
assign axi_awready = ram_awready;
//w
assign ram_wdata = axi_wdata ;
assign ram_wstrb = axi_wstrb ;
assign ram_wlast = axi_wlast ;
assign ram_wvalid = axi_wvalid ;
assign axi_wready = ram_wready ;
//b
assign axi_bid = axi_bvalid ? ram_bid : 5'd0 ;
assign axi_bresp = axi_bvalid ? ram_bresp : 2'd0 ;
assign axi_bvalid = ram_bvalid ;
assign ram_bready = axi_bready ;
axi2sram_dp #(
.BUS_WIDTH ( 32 ),
.DATA_WIDTH ( 32 ),
.CPU_WIDTH ( 32 ))
u_axi2sram_dp (
.aclk ( aclk ),
.aresetn ( aresetn ),
.m_araddr ( ram_araddr ),
.m_arburst ( ram_arburst ),
.m_arcache ( 4'h0 ),
.m_arid ( ram_arid ),
.m_arlen ( ram_arlen ),
.m_arlock ( 2'h0 ),
.m_arprot ( 3'h0 ),
.m_arsize ( ram_arsize ),
.m_arvalid ( ram_arvalid ),
.m_arready ( ram_arready ),
.m_rready ( ram_rready ),
.m_rdata ( ram_rdata ),
.m_rid ( ram_rid ),
.m_rlast ( ram_rlast ),
.m_rresp ( ram_rresp ),
.m_rvalid ( ram_rvalid ),
.m_awaddr ( ram_awaddr ),
.m_awburst ( ram_awburst ),
.m_awcache ( 4'h0 ),
.m_awid ( ram_awid ),
.m_awlen ( ram_awlen ),
.m_awlock ( 2'h0 ),
.m_awprot ( 3'h0 ),
.m_awsize ( ram_awsize ),
.m_awvalid ( ram_awvalid ),
.m_awready ( ram_awready ),
.m_wdata ( ram_wdata ),
.m_wlast ( ram_wlast ),
.m_wstrb ( ram_wstrb ),
.m_wvalid ( ram_wvalid ),
.m_wready ( ram_wready ),
.m_bready ( ram_bready ),
.m_bid ( ram_bid ),
.m_bresp ( ram_bresp ),
.m_bvalid ( ram_bvalid ),
.ram_raddr ( fpga_sram_raddr ),
.ram_ren ( fpga_sram_ren ),
.ram_waddr ( fpga_sram_waddr ),
.ram_wdata ( fpga_sram_wdata ),
.ram_wen ( fpga_sram_wen ),
.ram_rdata ( fpga_sram_rdata )
);
//1MByte SRAM
fpga_sram_dp #(
.AW ( 18 ),
.Init_File (Init_File)
)u_fpga_sram (
.CLK ( aclk ),
.ram_raddr ( fpga_sram_raddr[19:2] ),
.ram_ren ( fpga_sram_ren ),
.ram_rdata ( fpga_sram_rdata ),
.ram_waddr ( fpga_sram_waddr[19:2] ),
.ram_wdata ( fpga_sram_wdata ),
.ram_wen ( fpga_sram_wen )
);
endmodule

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/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
module axi_wrap_ram_sp #(
parameter Init_File = "none"
)
(
input aclk,
input aresetn,
//ar
input [4 :0] axi_arid ,
input [31:0] axi_araddr ,
input [7 :0] axi_arlen ,
input [2 :0] axi_arsize ,
input [1 :0] axi_arburst,
input [1 :0] axi_arlock ,
input [3 :0] axi_arcache,
input [2 :0] axi_arprot ,
input axi_arvalid,
output axi_arready,
//r
output [4 :0] axi_rid ,
output [31:0] axi_rdata ,
output [1 :0] axi_rresp ,
output axi_rlast ,
output axi_rvalid ,
input axi_rready ,
//aw
input [4 :0] axi_awid ,
input [31:0] axi_awaddr ,
input [7 :0] axi_awlen ,
input [2 :0] axi_awsize ,
input [1 :0] axi_awburst,
input [1 :0] axi_awlock ,
input [3 :0] axi_awcache,
input [2 :0] axi_awprot ,
input axi_awvalid,
output axi_awready,
//w
input [31:0] axi_wdata ,
input [3 :0] axi_wstrb ,
input axi_wlast ,
input axi_wvalid ,
output axi_wready ,
//b
output [4 :0] axi_bid ,
output [1 :0] axi_bresp ,
output axi_bvalid ,
input axi_bready
);
//ram axi
//ar
wire [4 :0] ram_arid ;
wire [31:0] ram_araddr ;
wire [7 :0] ram_arlen ;
wire [2 :0] ram_arsize ;
wire [1 :0] ram_arburst;
wire [1 :0] ram_arlock ;
wire [3 :0] ram_arcache;
wire [2 :0] ram_arprot ;
wire ram_arvalid;
wire ram_arready;
//r
wire [4 :0] ram_rid ;
wire [31:0] ram_rdata ;
wire [1 :0] ram_rresp ;
wire ram_rlast ;
wire ram_rvalid ;
wire ram_rready ;
//aw
wire [4 :0] ram_awid ;
wire [31:0] ram_awaddr ;
wire [7 :0] ram_awlen ;
wire [2 :0] ram_awsize ;
wire [1 :0] ram_awburst;
wire [1 :0] ram_awlock ;
wire [3 :0] ram_awcache;
wire [2 :0] ram_awprot ;
wire ram_awvalid;
wire ram_awready;
//w
wire [31:0] ram_wdata ;
wire [3 :0] ram_wstrb ;
wire ram_wlast ;
wire ram_wvalid ;
wire ram_wready ;
//b
wire [4 :0] ram_bid ;
wire [1 :0] ram_bresp ;
wire ram_bvalid ;
wire ram_bready ;
//sram signal
wire [31:0] fpga_sram_addr;
wire fpga_sram_cs;
wire fpga_sram_we;
wire [3:0] fpga_sram_be;
wire [31:0] fpga_sram_wdata;
wire [31:0] fpga_sram_rdata;
//ar
assign ram_arid = axi_arid ;
assign ram_araddr = axi_araddr ;
assign ram_arlen = axi_arlen ;
assign ram_arsize = axi_arsize ;
assign ram_arburst = axi_arburst;
assign ram_arlock = axi_arlock ;
assign ram_arcache = axi_arcache;
assign ram_arprot = axi_arprot ;
assign ram_arvalid = axi_arvalid;
assign axi_arready = ram_arready;
//r
assign axi_rid = axi_rvalid ? ram_rid : 5'd0 ;
assign axi_rdata = axi_rvalid ? ram_rdata : 32'd0 ;
assign axi_rresp = axi_rvalid ? ram_rresp : 2'd0 ;
assign axi_rlast = axi_rvalid ? ram_rlast : 1'd0 ;
assign axi_rvalid = ram_rvalid;
assign ram_rready = axi_rready;
//aw
assign ram_awid = axi_awid ;
assign ram_awaddr = axi_awaddr ;
assign ram_awlen = axi_awlen ;
assign ram_awsize = axi_awsize ;
assign ram_awburst = axi_awburst;
assign ram_awlock = axi_awlock ;
assign ram_awcache = axi_awcache;
assign ram_awprot = axi_awprot ;
assign ram_awvalid = axi_awvalid;
assign axi_awready = ram_awready;
//w
assign ram_wdata = axi_wdata ;
assign ram_wstrb = axi_wstrb ;
assign ram_wlast = axi_wlast ;
assign ram_wvalid = axi_wvalid ;
assign axi_wready = ram_wready ;
//b
assign axi_bid = axi_bvalid ? ram_bid : 5'd0 ;
assign axi_bresp = axi_bvalid ? ram_bresp : 2'd0 ;
assign axi_bvalid = ram_bvalid ;
assign ram_bready = axi_bready ;
axi2sram_sp #(
.AXI_ID_WIDTH ( 5 ),
.AXI_ADDR_WIDTH ( 32 ),
.AXI_DATA_WIDTH ( 32 ))
u_axi_sram_sp (
.clk ( aclk ),
.resetn ( aresetn ),
.s_araddr ( ram_araddr ),
.s_arburst ( ram_arburst ),
.s_arcache ( ram_arcache ),
.s_arid ( ram_arid ),
.s_arlen ( ram_arlen ),
.s_arlock ( ram_arlock ),
.s_arprot ( ram_arprot ),
.s_arsize ( ram_arsize ),
.s_arvalid ( ram_arvalid ),
.s_awaddr ( ram_awaddr ),
.s_awburst ( ram_awburst ),
.s_awcache ( ram_awcache ),
.s_awid ( ram_awid ),
.s_awlen ( ram_awlen ),
.s_awlock ( ram_awlock ),
.s_awprot ( ram_awprot ),
.s_awsize ( ram_awsize ),
.s_awvalid ( ram_awvalid ),
.s_bready ( ram_bready ),
.s_rready ( ram_rready ),
.s_wdata ( ram_wdata ),
.s_wlast ( ram_wlast ),
.s_wstrb ( ram_wstrb ),
.s_wvalid ( ram_wvalid ),
.s_arready ( ram_arready ),
.s_awready ( ram_awready ),
.s_bid ( ram_bid ),
.s_bresp ( ram_bresp ),
.s_bvalid ( ram_bvalid ),
.s_rdata ( ram_rdata ),
.s_rid ( ram_rid ),
.s_rlast ( ram_rlast ),
.s_rresp ( ram_rresp ),
.s_rvalid ( ram_rvalid ),
.s_wready ( ram_wready ),
.req_o ( fpga_sram_cs ),
.we_o ( fpga_sram_we ),
.addr_o ( fpga_sram_addr ),
.be_o ( fpga_sram_be ),
.data_o ( fpga_sram_wdata ),
.data_i ( fpga_sram_rdata )
);
wire [3:0] fpga_sram_wren = {4{fpga_sram_we}} & fpga_sram_be;
//1MByte SRAM
fpga_sram_sp #(
.AW ( 18 ),
.Init_File (Init_File)
)u_fpga_sram (
.CLK ( aclk ),
.ADDR ( fpga_sram_addr[19:2] ),
.WDATA ( fpga_sram_wdata ),
.WREN ( fpga_sram_wren ),
.CS ( fpga_sram_cs ),
.RDATA ( fpga_sram_rdata )
);
endmodule

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rtl/ip/ram_wrap/axi_wrap_ram_sp_external.v Normal file
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/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
module axi_wrap_ram_sp_external (
input aclk,
input aresetn,
//ar
input [4 :0] axi_arid ,
input [31:0] axi_araddr ,
input [7 :0] axi_arlen ,
input [2 :0] axi_arsize ,
input [1 :0] axi_arburst,
input axi_arlock ,
input [3 :0] axi_arcache,
input [2 :0] axi_arprot ,
input axi_arvalid,
output axi_arready,
//r
output [4 :0] axi_rid ,
output [31:0] axi_rdata ,
output [1 :0] axi_rresp ,
output axi_rlast ,
output axi_rvalid ,
input axi_rready ,
//aw
input [4 :0] axi_awid ,
input [31:0] axi_awaddr ,
input [7 :0] axi_awlen ,
input [2 :0] axi_awsize ,
input [1 :0] axi_awburst,
input axi_awlock ,
input [3 :0] axi_awcache,
input [2 :0] axi_awprot ,
input axi_awvalid,
output axi_awready,
//w
input [31:0] axi_wdata ,
input [3 :0] axi_wstrb ,
input axi_wlast ,
input axi_wvalid ,
output axi_wready ,
//b
output [4 :0] axi_bid ,
output [1 :0] axi_bresp ,
output axi_bvalid ,
input axi_bready ,
//BaseRAM信号
inout [31:0] base_ram_data, //BaseRAM数据，低8位与CPLD串口控制器共享
output [19:0] base_ram_addr, //BaseRAM地址
output [ 3:0] base_ram_be_n, //BaseRAM字节使能，低有效。如果不使用字节使能，请保持为0
output base_ram_ce_n, //BaseRAM片选，低有效
output base_ram_oe_n, //BaseRAM读使能，低有效
output base_ram_we_n, //BaseRAM写使能，低有效
//ExtRAM信号
inout [31:0] ext_ram_data, //ExtRAM数据
output [19:0] ext_ram_addr, //ExtRAM地址
output [ 3:0] ext_ram_be_n, //ExtRAM字节使能，低有效。如果不使用字节使能，请保持为0
output ext_ram_ce_n, //ExtRAM片选，低有效
output ext_ram_oe_n, //ExtRAM读使能，低有效
output ext_ram_we_n //ExtRAM写使能，低有效
);
//ram axi
//ar
wire [4 :0] ram_arid ;
wire [31:0] ram_araddr ;
wire [7 :0] ram_arlen ;
wire [2 :0] ram_arsize ;
wire [1 :0] ram_arburst;
wire ram_arlock ;
wire [3 :0] ram_arcache;
wire [2 :0] ram_arprot ;
wire ram_arvalid;
wire ram_arready;
//r
wire [4 :0] ram_rid ;
wire [31:0] ram_rdata ;
wire [1 :0] ram_rresp ;
wire ram_rlast ;
wire ram_rvalid ;
wire ram_rready ;
//aw
wire [4 :0] ram_awid ;
wire [31:0] ram_awaddr ;
wire [7 :0] ram_awlen ;
wire [2 :0] ram_awsize ;
wire [1 :0] ram_awburst;
wire ram_awlock ;
wire [3 :0] ram_awcache;
wire [2 :0] ram_awprot ;
wire ram_awvalid;
wire ram_awready;
//w
wire [31:0] ram_wdata ;
wire [3 :0] ram_wstrb ;
wire ram_wlast ;
wire ram_wvalid ;
wire ram_wready ;
//b
wire [4 :0] ram_bid ;
wire [1 :0] ram_bresp ;
wire ram_bvalid ;
wire ram_bready ;
//sram signal
wire [31:0] soc_sram_addr;
wire soc_sram_cs;
wire soc_sram_we;
wire [3:0] soc_sram_be;
wire [31:0] soc_sram_wdata;
wire [31:0] soc_sram_rdata;
//ar
assign ram_arid = axi_arid ;
assign ram_araddr = axi_araddr ;
assign ram_arlen = axi_arlen ;
assign ram_arsize = axi_arsize ;
assign ram_arburst = axi_arburst;
assign ram_arlock = axi_arlock ;
assign ram_arcache = axi_arcache;
assign ram_arprot = axi_arprot ;
assign ram_arvalid = axi_arvalid;
assign axi_arready = ram_arready;
//r
assign axi_rid = axi_rvalid ? ram_rid : 5'd0 ;
assign axi_rdata = axi_rvalid ? ram_rdata : 32'd0 ;
assign axi_rresp = axi_rvalid ? ram_rresp : 2'd0 ;
assign axi_rlast = axi_rvalid ? ram_rlast : 1'd0 ;
assign axi_rvalid = ram_rvalid;
assign ram_rready = axi_rready;
//aw
assign ram_awid = axi_awid ;
assign ram_awaddr = axi_awaddr ;
assign ram_awlen = axi_awlen ;
assign ram_awsize = axi_awsize ;
assign ram_awburst = axi_awburst;
assign ram_awlock = axi_awlock ;
assign ram_awcache = axi_awcache;
assign ram_awprot = axi_awprot ;
assign ram_awvalid = axi_awvalid;
assign axi_awready = ram_awready;
//w
assign ram_wdata = axi_wdata ;
assign ram_wstrb = axi_wstrb ;
assign ram_wlast = axi_wlast ;
assign ram_wvalid = axi_wvalid ;
assign axi_wready = ram_wready ;
//b
assign axi_bid = axi_bvalid ? ram_bid : 5'd0 ;
assign axi_bresp = axi_bvalid ? ram_bresp : 2'd0 ;
assign axi_bvalid = ram_bvalid ;
assign ram_bready = axi_bready ;
axi2sram_sp_external #(
.AXI_ID_WIDTH ( 5 ),
.AXI_ADDR_WIDTH ( 32 ),
.AXI_DATA_WIDTH ( 32 ))
u_axi_sram_sp (
.clk ( aclk ),
.resetn ( aresetn ),
.s_araddr ( ram_araddr ),
.s_arburst ( ram_arburst ),
.s_arcache ( ram_arcache ),
.s_arid ( ram_arid ),
.s_arlen ( ram_arlen ),
.s_arlock ( ram_arlock ),
.s_arprot ( ram_arprot ),
.s_arsize ( ram_arsize ),
.s_arvalid ( ram_arvalid ),
.s_awaddr ( ram_awaddr ),
.s_awburst ( ram_awburst ),
.s_awcache ( ram_awcache ),
.s_awid ( ram_awid ),
.s_awlen ( ram_awlen ),
.s_awlock ( ram_awlock ),
.s_awprot ( ram_awprot ),
.s_awsize ( ram_awsize ),
.s_awvalid ( ram_awvalid ),
.s_bready ( ram_bready ),
.s_rready ( ram_rready ),
.s_wdata ( ram_wdata ),
.s_wlast ( ram_wlast ),
.s_wstrb ( ram_wstrb ),
.s_wvalid ( ram_wvalid ),
.s_arready ( ram_arready ),
.s_awready ( ram_awready ),
.s_bid ( ram_bid ),
.s_bresp ( ram_bresp ),
.s_bvalid ( ram_bvalid ),
.s_rdata ( ram_rdata ),
.s_rid ( ram_rid ),
.s_rlast ( ram_rlast ),
.s_rresp ( ram_rresp ),
.s_rvalid ( ram_rvalid ),
.s_wready ( ram_wready ),
.req_o ( soc_sram_cs ),
.we_o ( soc_sram_we ),
.addr_o ( soc_sram_addr ),
.be_o ( soc_sram_be ),
.data_o ( soc_sram_wdata ),
.data_i ( soc_sram_rdata )
);
wire choose_sram = soc_sram_addr[22];//1:ExtRAM 0:BaseRAM
wire [3:0] be_out = soc_sram_we ? soc_sram_be : 4'b1111;
assign base_ram_addr = soc_sram_addr[21:2];
assign base_ram_be_n = choose_sram ? 4'b1111 : ~be_out;
assign base_ram_ce_n = ~(soc_sram_cs & (~choose_sram));
assign base_ram_oe_n = soc_sram_we | choose_sram;
assign base_ram_we_n = ~(soc_sram_we & (~choose_sram));
assign base_ram_data = ((~choose_sram) & soc_sram_cs & soc_sram_we) ? soc_sram_wdata : 32'hzzzzzzzz;
assign ext_ram_addr = soc_sram_addr[21:2];
assign ext_ram_be_n = choose_sram ? ~be_out : 4'b1111;
assign ext_ram_ce_n = choose_sram ? ~soc_sram_cs : 1'b1;
assign ext_ram_oe_n = choose_sram ? soc_sram_we : 1'b1;
assign ext_ram_we_n = choose_sram ? ~soc_sram_we : 1'b1;
assign ext_ram_data = ((choose_sram) & soc_sram_cs & soc_sram_we) ? soc_sram_wdata : 32'hzzzzzzzz;
assign soc_sram_rdata = choose_sram ? ext_ram_data : base_ram_data;
endmodule

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rtl/ip/ram_wrap/cache_sram.v Normal file
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`include "config.h"
module data_bank_sram (
input [ 7:0] addra ,
input clka ,
input [31:0] dina ,
output [31:0] douta ,
input ena ,
input [ 3:0] wea
);
`ifdef USE_CACHE
localparam V_STYLE = "block";
localparam P_STYLE = (V_STYLE == "ultra") ? "uram" :
(V_STYLE == "distributed") ? "select_ram" :
"block_ram";
(*ram_style = V_STYLE*) reg [31:0] mem_reg [255:0]/*synthesis syn_ramstyle=P_STYLE*/;
reg [31:0] output_buffer;
always @(posedge clka) begin
if (ena) begin
if (wea) begin
if (wea[0]) begin
mem_reg[addra][ 7: 0] <= dina[ 7: 0];
end
if (wea[1]) begin
mem_reg[addra][15: 8] <= dina[15: 8];
end
if (wea[2]) begin
mem_reg[addra][23:16] <= dina[23:16];
end
if (wea[3]) begin
mem_reg[addra][31:24] <= dina[31:24];
end
end
else begin
output_buffer <= mem_reg[addra];
end
end
end
assign douta = output_buffer;
`else
assign douta = 32'h0;
`endif
endmodule
module tagv_sram (
input [ 7:0] addra ,
input clka ,
input [20:0] dina ,
output [20:0] douta ,
input ena ,
input wea
);
`ifdef USE_CACHE
localparam V_STYLE = "block";
localparam P_STYLE = (V_STYLE == "ultra") ? "uram" :
(V_STYLE == "distributed") ? "select_ram" :
"block_ram";
(*ram_style = V_STYLE*) reg [20:0] mem_reg [255:0]/*synthesis syn_ramstyle=P_STYLE*/;
reg [20:0] output_buffer;
always @(posedge clka) begin
if (ena) begin
if (wea) begin
mem_reg[addra] <= dina;
end
else begin
output_buffer <= mem_reg[addra];
end
end
end
assign douta = output_buffer;
`else
assign douta = 21'h0;
`endif
endmodule

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rtl/ip/ram_wrap/fpga_sram_dp.v Normal file
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module fpga_sram_dp #(
parameter AW = 16,
parameter Init_File = "none"
)
(
input wire CLK,
input wire [AW-1:0] ram_raddr,
output wire [31 :0] ram_rdata,
input wire ram_ren ,
input wire [AW-1:0] ram_waddr,
input wire [31 :0] ram_wdata,
input wire [3 :0] ram_wen
);
localparam AWT = ((1<<(AW-0))-1);
localparam V_STYLE = "block";
localparam P_STYLE = (V_STYLE == "ultra") ? "uram" :
(V_STYLE == "distributed") ? "select_ram" :
"block_ram";
(*ram_style = V_STYLE*)reg [31:0] BRAM [AWT:0]/*synthesis syn_ramstyle=P_STYLE*/;
initial begin
if(Init_File != "none") begin
$readmemb(Init_File,BRAM);
end
end
reg [AW-1:0] addr_q1;
always@(posedge CLK) begin
if(ram_wen[0]) BRAM[ram_waddr][7:0] <= ram_wdata[7:0];
end
always@(posedge CLK) begin
if(ram_wen[1]) BRAM[ram_waddr][15:8] <= ram_wdata[15:8];
end
always@(posedge CLK) begin
if(ram_wen[2]) BRAM[ram_waddr][23:16] <= ram_wdata[23:16];
end
always@(posedge CLK) begin
if(ram_wen[3]) BRAM[ram_waddr][31:24] <= ram_wdata[31:24];
end
always @ (posedge CLK) begin
if(ram_ren)
addr_q1 <= ram_raddr;
end
assign ram_rdata = BRAM[addr_q1];
endmodule

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rtl/ip/ram_wrap/fpga_sram_sp.v Normal file
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module fpga_sram_sp #(
parameter AW = 16,
parameter Init_File = "none"
)
(
input wire CLK,
input wire [AW-1:0] ADDR,
input wire [31:0] WDATA,
input wire [3:0] WREN,
input wire CS,
output wire [31:0] RDATA
);
localparam AWT = ((1<<(AW-0))-1);
localparam V_STYLE = "block";
localparam P_STYLE = (V_STYLE == "ultra") ? "uram" :
(V_STYLE == "distributed") ? "select_ram" :
"block_ram";
(*ram_style = V_STYLE*)reg [31:0] BRAM [AWT:0]/*synthesis syn_ramstyle=P_STYLE*/;
initial begin
if(Init_File != "none") begin
$readmemb(Init_File,BRAM);
end
end
reg [AW-1:0] addr_q1;
wire [3:0] write_enable;
assign write_enable[3:0] = WREN[3:0] & {4{CS}};
always@(posedge CLK) begin
if(write_enable[0]) BRAM[ADDR][7:0] <= WDATA[7:0];
end
always@(posedge CLK) begin
if(write_enable[1]) BRAM[ADDR][15:8] <= WDATA[15:8];
end
always@(posedge CLK) begin
if(write_enable[2]) BRAM[ADDR][23:16] <= WDATA[23:16];
end
always@(posedge CLK) begin
if(write_enable[3]) BRAM[ADDR][31:24] <= WDATA[31:24];
end
always @ (posedge CLK) begin
if(CS && !(|WREN))
addr_q1 <= ADDR[AW-1:0];
end
assign RDATA = BRAM[addr_q1];
endmodule