35917 lines
3.3 MiB
35917 lines
3.3 MiB
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
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| Date : Sat Jul 11 09:34:17 2026
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| Host : fedora running 64-bit unknown
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| Command : report_timing -delay_type max -sort_by group -max_paths 100 -nworst 10 -path_type full -input_pins -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/timing_setup_paths.rpt
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| Design : soc_top
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| Device : 7a200t-fbg676
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| Speed File : -1 PRODUCTION 1.23 2018-06-13
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Timing Report
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Slack (MET) : 0.070ns (required time - arrival time)
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Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
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(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
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Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]/D
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(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
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Path Group: mlkem_clk
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Path Type: Setup (Max at Slow Process Corner)
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Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
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Data Path Delay: 13.035ns (logic 0.752ns (5.769%) route 12.283ns (94.231%))
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Logic Levels: 1 (MUXF7=1)
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Clock Path Skew: 0.135ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -1.847ns = ( 11.153 - 13.000 )
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Source Clock Delay (SCD): -2.480ns
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Clock Pessimism Removal (CPR): -0.498ns
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Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.172ns
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Phase Error (PE): 0.000ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock mlkem_clk rise edge)
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0.000 0.000 r
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clock source latency -6.275 -6.275
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propagated clock network latency
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3.796 -2.480
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SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
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SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q
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net (fo=1088, routed) 12.283 10.259 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2
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SLICE_X145Y37 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[732]_i_1/S
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SLICE_X145Y37 MUXF7 (Prop_muxf7_S_O) 0.296 10.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[732]_i_1/O
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net (fo=1, routed) 0.000 10.555 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[732]
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SLICE_X145Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]/D
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------------------------------------------------------------------- -------------------
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(clock mlkem_clk rise edge)
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13.000 13.000 r
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clock source latency -5.674 7.326
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propagated clock network latency
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3.828 11.153
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clock pessimism -0.498 10.655
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clock uncertainty -0.093 10.562
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SLICE_X145Y37 FDCE (Setup_fdce_C_D) 0.064 10.626 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]
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-------------------------------------------------------------------
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required time 10.626
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arrival time -10.555
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-------------------------------------------------------------------
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slack 0.070
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Slack (MET) : 0.070ns (required time - arrival time)
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Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
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(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
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Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]/D
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(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
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Path Group: mlkem_clk
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Path Type: Setup (Max at Slow Process Corner)
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Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
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Data Path Delay: 13.035ns (logic 0.752ns (5.769%) route 12.283ns (94.231%))
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Logic Levels: 1 (MUXF7=1)
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Clock Path Skew: 0.135ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -1.847ns = ( 11.153 - 13.000 )
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Source Clock Delay (SCD): -2.480ns
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Clock Pessimism Removal (CPR): -0.498ns
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Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.172ns
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Phase Error (PE): 0.000ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock mlkem_clk rise edge)
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0.000 0.000 r
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clock source latency -6.275 -6.275
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propagated clock network latency
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3.796 -2.480
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SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
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SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q
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net (fo=1088, routed) 12.283 10.259 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2
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SLICE_X145Y37 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[732]_i_1/S
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SLICE_X145Y37 MUXF7 (Prop_muxf7_S_O) 0.296 10.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[732]_i_1/O
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net (fo=1, routed) 0.000 10.555 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[732]
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SLICE_X145Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]/D
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------------------------------------------------------------------- -------------------
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(clock mlkem_clk rise edge)
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13.000 13.000 r
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clock source latency -5.674 7.326
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propagated clock network latency
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3.828 11.153
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clock pessimism -0.498 10.655
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clock uncertainty -0.093 10.562
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SLICE_X145Y37 FDCE (Setup_fdce_C_D) 0.064 10.626 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]
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-------------------------------------------------------------------
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required time 10.626
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arrival time -10.555
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-------------------------------------------------------------------
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slack 0.070
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Slack (MET) : 0.070ns (required time - arrival time)
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Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
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(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
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Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]/D
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(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
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Path Group: mlkem_clk
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Path Type: Setup (Max at Slow Process Corner)
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Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
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Data Path Delay: 13.035ns (logic 0.752ns (5.769%) route 12.283ns (94.231%))
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Logic Levels: 1 (MUXF7=1)
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Clock Path Skew: 0.135ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -1.847ns = ( 11.153 - 13.000 )
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Source Clock Delay (SCD): -2.480ns
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Clock Pessimism Removal (CPR): -0.498ns
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Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.172ns
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Phase Error (PE): 0.000ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock mlkem_clk rise edge)
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0.000 0.000 r
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clock source latency -6.275 -6.275
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propagated clock network latency
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3.796 -2.480
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SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
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SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q
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net (fo=1088, routed) 12.283 10.259 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2
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SLICE_X145Y37 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[732]_i_1/S
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SLICE_X145Y37 MUXF7 (Prop_muxf7_S_O) 0.296 10.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[732]_i_1/O
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net (fo=1, routed) 0.000 10.555 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[732]
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SLICE_X145Y37 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]/D
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------------------------------------------------------------------- -------------------
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(clock mlkem_clk rise edge)
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13.000 13.000 r
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clock source latency -5.674 7.326
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propagated clock network latency
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3.828 11.153
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clock pessimism -0.498 10.655
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clock uncertainty -0.093 10.562
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SLICE_X145Y37 FDCE (Setup_fdce_C_D) 0.064 10.626 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]
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-------------------------------------------------------------------
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required time 10.626
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arrival time -10.555
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-------------------------------------------------------------------
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slack 0.070
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Slack (MET) : 0.070ns (required time - arrival time)
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Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
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(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
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Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]/D
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(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
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Path Group: mlkem_clk
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Path Type: Setup (Max at Slow Process Corner)
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Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
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Data Path Delay: 13.035ns (logic 0.752ns (5.769%) route 12.283ns (94.231%))
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Logic Levels: 1 (MUXF7=1)
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Clock Path Skew: 0.135ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -1.847ns = ( 11.153 - 13.000 )
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Source Clock Delay (SCD): -2.480ns
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Clock Pessimism Removal (CPR): -0.498ns
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Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.172ns
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Phase Error (PE): 0.000ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock mlkem_clk rise edge)
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0.000 0.000 r
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clock source latency -6.275 -6.275
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propagated clock network latency
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3.796 -2.480
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SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
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SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q
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net (fo=1088, routed) 12.283 10.259 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2
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SLICE_X145Y37 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[732]_i_1/S
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SLICE_X145Y37 MUXF7 (Prop_muxf7_S_O) 0.296 10.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[732]_i_1/O
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net (fo=1, routed) 0.000 10.555 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[732]
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SLICE_X145Y37 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]/D
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------------------------------------------------------------------- -------------------
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(clock mlkem_clk rise edge)
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13.000 13.000 r
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clock source latency -5.674 7.326
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propagated clock network latency
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3.828 11.153
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clock pessimism -0.498 10.655
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clock uncertainty -0.093 10.562
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SLICE_X145Y37 FDCE (Setup_fdce_C_D) 0.064 10.626 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]
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-------------------------------------------------------------------
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required time 10.626
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arrival time -10.555
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-------------------------------------------------------------------
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slack 0.070
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Slack (MET) : 0.088ns (required time - arrival time)
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Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
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(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
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Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10]
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(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
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Path Group: mlkem_clk
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Path Type: Setup (Max at Slow Process Corner)
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Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
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Data Path Delay: 12.599ns (logic 3.356ns (26.636%) route 9.243ns (73.364%))
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Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
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Clock Path Skew: 0.021ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
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Source Clock Delay (SCD): -2.520ns
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Clock Pessimism Removal (CPR): -0.498ns
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Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.172ns
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Phase Error (PE): 0.000ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock mlkem_clk rise edge)
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0.000 0.000 r
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clock source latency -6.275 -6.275
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propagated clock network latency
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3.756 -2.520
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SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
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SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
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net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
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SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
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SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
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net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
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SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
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SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
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net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
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SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
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SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
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net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
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SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
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SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
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net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
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SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
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SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
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net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
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SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3]
|
|
net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0
|
|
SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI
|
|
SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.256 7.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2]
|
|
net (fo=2, routed) 0.792 7.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[10]
|
|
SLICE_X122Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/I1
|
|
SLICE_X122Y74 LUT6 (Prop_lut6_I1_O) 0.302 8.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/O
|
|
net (fo=1, routed) 0.624 8.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_12
|
|
SLICE_X135Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/I5
|
|
SLICE_X135Y73 LUT6 (Prop_lut6_I5_O) 0.124 8.974 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/O
|
|
net (fo=1, routed) 0.448 9.422 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0_n_0
|
|
SLICE_X139Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/I0
|
|
SLICE_X139Y72 LUT5 (Prop_lut5_I0_O) 0.124 9.546 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/O
|
|
net (fo=1, routed) 0.534 10.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.080
|
|
-------------------------------------------------------------------
|
|
slack 0.088
|
|
|
|
Slack (MET) : 0.088ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.599ns (logic 3.356ns (26.636%) route 9.243ns (73.364%))
|
|
Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3]
|
|
net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0
|
|
SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI
|
|
SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.256 7.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2]
|
|
net (fo=2, routed) 0.792 7.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[10]
|
|
SLICE_X122Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/I1
|
|
SLICE_X122Y74 LUT6 (Prop_lut6_I1_O) 0.302 8.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/O
|
|
net (fo=1, routed) 0.624 8.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_12
|
|
SLICE_X135Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/I5
|
|
SLICE_X135Y73 LUT6 (Prop_lut6_I5_O) 0.124 8.974 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/O
|
|
net (fo=1, routed) 0.448 9.422 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0_n_0
|
|
SLICE_X139Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/I0
|
|
SLICE_X139Y72 LUT5 (Prop_lut5_I0_O) 0.124 9.546 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/O
|
|
net (fo=1, routed) 0.534 10.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.080
|
|
-------------------------------------------------------------------
|
|
slack 0.088
|
|
|
|
Slack (MET) : 0.088ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.599ns (logic 3.356ns (26.636%) route 9.243ns (73.364%))
|
|
Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3]
|
|
net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0
|
|
SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI
|
|
SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.256 7.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2]
|
|
net (fo=2, routed) 0.792 7.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[10]
|
|
SLICE_X122Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/I1
|
|
SLICE_X122Y74 LUT6 (Prop_lut6_I1_O) 0.302 8.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/O
|
|
net (fo=1, routed) 0.624 8.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_12
|
|
SLICE_X135Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/I5
|
|
SLICE_X135Y73 LUT6 (Prop_lut6_I5_O) 0.124 8.974 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/O
|
|
net (fo=1, routed) 0.448 9.422 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0_n_0
|
|
SLICE_X139Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/I0
|
|
SLICE_X139Y72 LUT5 (Prop_lut5_I0_O) 0.124 9.546 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/O
|
|
net (fo=1, routed) 0.534 10.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.080
|
|
-------------------------------------------------------------------
|
|
slack 0.088
|
|
|
|
Slack (MET) : 0.088ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.599ns (logic 3.356ns (26.636%) route 9.243ns (73.364%))
|
|
Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3]
|
|
net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0
|
|
SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI
|
|
SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.256 7.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2]
|
|
net (fo=2, routed) 0.792 7.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[10]
|
|
SLICE_X122Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/I1
|
|
SLICE_X122Y74 LUT6 (Prop_lut6_I1_O) 0.302 8.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/O
|
|
net (fo=1, routed) 0.624 8.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_12
|
|
SLICE_X135Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/I5
|
|
SLICE_X135Y73 LUT6 (Prop_lut6_I5_O) 0.124 8.974 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/O
|
|
net (fo=1, routed) 0.448 9.422 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0_n_0
|
|
SLICE_X139Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/I0
|
|
SLICE_X139Y72 LUT5 (Prop_lut5_I0_O) 0.124 9.546 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/O
|
|
net (fo=1, routed) 0.534 10.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.080
|
|
-------------------------------------------------------------------
|
|
slack 0.088
|
|
|
|
Slack (MET) : 0.088ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.599ns (logic 3.356ns (26.636%) route 9.243ns (73.364%))
|
|
Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3]
|
|
net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0
|
|
SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI
|
|
SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.256 7.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2]
|
|
net (fo=2, routed) 0.792 7.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[10]
|
|
SLICE_X122Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/I1
|
|
SLICE_X122Y74 LUT6 (Prop_lut6_I1_O) 0.302 8.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/O
|
|
net (fo=1, routed) 0.624 8.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_12
|
|
SLICE_X135Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/I5
|
|
SLICE_X135Y73 LUT6 (Prop_lut6_I5_O) 0.124 8.974 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/O
|
|
net (fo=1, routed) 0.448 9.422 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0_n_0
|
|
SLICE_X139Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/I0
|
|
SLICE_X139Y72 LUT5 (Prop_lut5_I0_O) 0.124 9.546 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/O
|
|
net (fo=1, routed) 0.534 10.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.080
|
|
-------------------------------------------------------------------
|
|
slack 0.088
|
|
|
|
Slack (MET) : 0.088ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.599ns (logic 3.356ns (26.636%) route 9.243ns (73.364%))
|
|
Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3]
|
|
net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0
|
|
SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI
|
|
SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.256 7.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2]
|
|
net (fo=2, routed) 0.792 7.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[10]
|
|
SLICE_X122Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/I1
|
|
SLICE_X122Y74 LUT6 (Prop_lut6_I1_O) 0.302 8.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/O
|
|
net (fo=1, routed) 0.624 8.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_12
|
|
SLICE_X135Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/I5
|
|
SLICE_X135Y73 LUT6 (Prop_lut6_I5_O) 0.124 8.974 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/O
|
|
net (fo=1, routed) 0.448 9.422 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0_n_0
|
|
SLICE_X139Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/I0
|
|
SLICE_X139Y72 LUT5 (Prop_lut5_I0_O) 0.124 9.546 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/O
|
|
net (fo=1, routed) 0.534 10.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.080
|
|
-------------------------------------------------------------------
|
|
slack 0.088
|
|
|
|
Slack (MET) : 0.088ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.599ns (logic 3.356ns (26.636%) route 9.243ns (73.364%))
|
|
Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3]
|
|
net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0
|
|
SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI
|
|
SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.256 7.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2]
|
|
net (fo=2, routed) 0.792 7.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[10]
|
|
SLICE_X122Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/I1
|
|
SLICE_X122Y74 LUT6 (Prop_lut6_I1_O) 0.302 8.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/O
|
|
net (fo=1, routed) 0.624 8.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_12
|
|
SLICE_X135Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/I5
|
|
SLICE_X135Y73 LUT6 (Prop_lut6_I5_O) 0.124 8.974 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/O
|
|
net (fo=1, routed) 0.448 9.422 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0_n_0
|
|
SLICE_X139Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/I0
|
|
SLICE_X139Y72 LUT5 (Prop_lut5_I0_O) 0.124 9.546 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/O
|
|
net (fo=1, routed) 0.534 10.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.080
|
|
-------------------------------------------------------------------
|
|
slack 0.088
|
|
|
|
Slack (MET) : 0.088ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.599ns (logic 3.356ns (26.636%) route 9.243ns (73.364%))
|
|
Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3]
|
|
net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0
|
|
SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI
|
|
SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.256 7.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2]
|
|
net (fo=2, routed) 0.792 7.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[10]
|
|
SLICE_X122Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/I1
|
|
SLICE_X122Y74 LUT6 (Prop_lut6_I1_O) 0.302 8.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/O
|
|
net (fo=1, routed) 0.624 8.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_12
|
|
SLICE_X135Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/I5
|
|
SLICE_X135Y73 LUT6 (Prop_lut6_I5_O) 0.124 8.974 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/O
|
|
net (fo=1, routed) 0.448 9.422 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0_n_0
|
|
SLICE_X139Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/I0
|
|
SLICE_X139Y72 LUT5 (Prop_lut5_I0_O) 0.124 9.546 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/O
|
|
net (fo=1, routed) 0.534 10.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.080
|
|
-------------------------------------------------------------------
|
|
slack 0.088
|
|
|
|
Slack (MET) : 0.088ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.599ns (logic 3.356ns (26.636%) route 9.243ns (73.364%))
|
|
Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 6.867 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3]
|
|
net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0
|
|
SLICE_X106Y75 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI
|
|
SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.256 7.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2]
|
|
net (fo=2, routed) 0.792 7.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[10]
|
|
SLICE_X122Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/I1
|
|
SLICE_X122Y74 LUT6 (Prop_lut6_I1_O) 0.302 8.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/O
|
|
net (fo=1, routed) 0.624 8.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_12
|
|
SLICE_X135Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/I5
|
|
SLICE_X135Y73 LUT6 (Prop_lut6_I5_O) 0.124 8.974 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/O
|
|
net (fo=1, routed) 0.448 9.422 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0_n_0
|
|
SLICE_X139Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/I0
|
|
SLICE_X139Y72 LUT5 (Prop_lut5_I0_O) 0.124 9.546 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/O
|
|
net (fo=1, routed) 0.534 10.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.080
|
|
-------------------------------------------------------------------
|
|
slack 0.088
|
|
|
|
Slack (MET) : 0.088ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.599ns (logic 3.356ns (26.636%) route 9.243ns (73.364%))
|
|
Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 6.867 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3]
|
|
net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0
|
|
SLICE_X106Y75 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI
|
|
SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.256 7.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2]
|
|
net (fo=2, routed) 0.792 7.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[10]
|
|
SLICE_X122Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/I1
|
|
SLICE_X122Y74 LUT6 (Prop_lut6_I1_O) 0.302 8.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/O
|
|
net (fo=1, routed) 0.624 8.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_12
|
|
SLICE_X135Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/I5
|
|
SLICE_X135Y73 LUT6 (Prop_lut6_I5_O) 0.124 8.974 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/O
|
|
net (fo=1, routed) 0.448 9.422 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0_n_0
|
|
SLICE_X139Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/I0
|
|
SLICE_X139Y72 LUT5 (Prop_lut5_I0_O) 0.124 9.546 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/O
|
|
net (fo=1, routed) 0.534 10.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.080
|
|
-------------------------------------------------------------------
|
|
slack 0.088
|
|
|
|
Slack (MET) : 0.091ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.597ns (logic 3.064ns (24.324%) route 9.533ns (75.676%))
|
|
Logic Levels: 12 (CARRY4=1 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_O[3])
|
|
0.606 6.827 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/O[3]
|
|
net (fo=2, routed) 0.948 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[3]
|
|
SLICE_X127Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/I1
|
|
SLICE_X127Y75 LUT6 (Prop_lut6_I1_O) 0.306 8.081 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/O
|
|
net (fo=1, routed) 0.620 8.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_5
|
|
SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/I5
|
|
SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.825 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/O
|
|
net (fo=1, routed) 0.419 9.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0_n_0
|
|
SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/I0
|
|
SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.368 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/O
|
|
net (fo=1, routed) 0.709 10.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[3]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[3])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.077
|
|
-------------------------------------------------------------------
|
|
slack 0.091
|
|
|
|
Slack (MET) : 0.091ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.597ns (logic 3.064ns (24.324%) route 9.533ns (75.676%))
|
|
Logic Levels: 12 (CARRY4=1 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_O[3])
|
|
0.606 6.827 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/O[3]
|
|
net (fo=2, routed) 0.948 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[3]
|
|
SLICE_X127Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/I1
|
|
SLICE_X127Y75 LUT6 (Prop_lut6_I1_O) 0.306 8.081 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/O
|
|
net (fo=1, routed) 0.620 8.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_5
|
|
SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/I5
|
|
SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.825 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/O
|
|
net (fo=1, routed) 0.419 9.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0_n_0
|
|
SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/I0
|
|
SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.368 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/O
|
|
net (fo=1, routed) 0.709 10.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[3]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[3])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.077
|
|
-------------------------------------------------------------------
|
|
slack 0.091
|
|
|
|
Slack (MET) : 0.091ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.597ns (logic 3.064ns (24.324%) route 9.533ns (75.676%))
|
|
Logic Levels: 12 (CARRY4=1 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_O[3])
|
|
0.606 6.827 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/O[3]
|
|
net (fo=2, routed) 0.948 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[3]
|
|
SLICE_X127Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/I1
|
|
SLICE_X127Y75 LUT6 (Prop_lut6_I1_O) 0.306 8.081 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/O
|
|
net (fo=1, routed) 0.620 8.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_5
|
|
SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/I5
|
|
SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.825 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/O
|
|
net (fo=1, routed) 0.419 9.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0_n_0
|
|
SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/I0
|
|
SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.368 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/O
|
|
net (fo=1, routed) 0.709 10.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[3]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[3])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.077
|
|
-------------------------------------------------------------------
|
|
slack 0.091
|
|
|
|
Slack (MET) : 0.091ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.597ns (logic 3.064ns (24.324%) route 9.533ns (75.676%))
|
|
Logic Levels: 12 (CARRY4=1 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_O[3])
|
|
0.606 6.827 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/O[3]
|
|
net (fo=2, routed) 0.948 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[3]
|
|
SLICE_X127Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/I1
|
|
SLICE_X127Y75 LUT6 (Prop_lut6_I1_O) 0.306 8.081 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/O
|
|
net (fo=1, routed) 0.620 8.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_5
|
|
SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/I5
|
|
SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.825 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/O
|
|
net (fo=1, routed) 0.419 9.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0_n_0
|
|
SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/I0
|
|
SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.368 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/O
|
|
net (fo=1, routed) 0.709 10.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[3]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[3])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.077
|
|
-------------------------------------------------------------------
|
|
slack 0.091
|
|
|
|
Slack (MET) : 0.091ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.597ns (logic 3.064ns (24.324%) route 9.533ns (75.676%))
|
|
Logic Levels: 12 (CARRY4=1 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_O[3])
|
|
0.606 6.827 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/O[3]
|
|
net (fo=2, routed) 0.948 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[3]
|
|
SLICE_X127Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/I1
|
|
SLICE_X127Y75 LUT6 (Prop_lut6_I1_O) 0.306 8.081 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/O
|
|
net (fo=1, routed) 0.620 8.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_5
|
|
SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/I5
|
|
SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.825 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/O
|
|
net (fo=1, routed) 0.419 9.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0_n_0
|
|
SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/I0
|
|
SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.368 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/O
|
|
net (fo=1, routed) 0.709 10.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[3]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[3])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.077
|
|
-------------------------------------------------------------------
|
|
slack 0.091
|
|
|
|
Slack (MET) : 0.091ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.597ns (logic 3.064ns (24.324%) route 9.533ns (75.676%))
|
|
Logic Levels: 12 (CARRY4=1 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_O[3])
|
|
0.606 6.827 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/O[3]
|
|
net (fo=2, routed) 0.948 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[3]
|
|
SLICE_X127Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/I1
|
|
SLICE_X127Y75 LUT6 (Prop_lut6_I1_O) 0.306 8.081 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/O
|
|
net (fo=1, routed) 0.620 8.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_5
|
|
SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/I5
|
|
SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.825 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/O
|
|
net (fo=1, routed) 0.419 9.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0_n_0
|
|
SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/I0
|
|
SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.368 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/O
|
|
net (fo=1, routed) 0.709 10.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[3]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[3])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.077
|
|
-------------------------------------------------------------------
|
|
slack 0.091
|
|
|
|
Slack (MET) : 0.091ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.597ns (logic 3.064ns (24.324%) route 9.533ns (75.676%))
|
|
Logic Levels: 12 (CARRY4=1 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_O[3])
|
|
0.606 6.827 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/O[3]
|
|
net (fo=2, routed) 0.948 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[3]
|
|
SLICE_X127Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/I1
|
|
SLICE_X127Y75 LUT6 (Prop_lut6_I1_O) 0.306 8.081 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/O
|
|
net (fo=1, routed) 0.620 8.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_5
|
|
SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/I5
|
|
SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.825 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/O
|
|
net (fo=1, routed) 0.419 9.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0_n_0
|
|
SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/I0
|
|
SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.368 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/O
|
|
net (fo=1, routed) 0.709 10.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[3]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[3])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.077
|
|
-------------------------------------------------------------------
|
|
slack 0.091
|
|
|
|
Slack (MET) : 0.091ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.597ns (logic 3.064ns (24.324%) route 9.533ns (75.676%))
|
|
Logic Levels: 12 (CARRY4=1 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_O[3])
|
|
0.606 6.827 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/O[3]
|
|
net (fo=2, routed) 0.948 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[3]
|
|
SLICE_X127Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/I1
|
|
SLICE_X127Y75 LUT6 (Prop_lut6_I1_O) 0.306 8.081 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/O
|
|
net (fo=1, routed) 0.620 8.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_5
|
|
SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/I5
|
|
SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.825 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/O
|
|
net (fo=1, routed) 0.419 9.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0_n_0
|
|
SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/I0
|
|
SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.368 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/O
|
|
net (fo=1, routed) 0.709 10.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[3]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[3])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.077
|
|
-------------------------------------------------------------------
|
|
slack 0.091
|
|
|
|
Slack (MET) : 0.091ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.597ns (logic 3.064ns (24.324%) route 9.533ns (75.676%))
|
|
Logic Levels: 12 (CARRY4=1 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_O[3])
|
|
0.606 6.827 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/O[3]
|
|
net (fo=2, routed) 0.948 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[3]
|
|
SLICE_X127Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/I1
|
|
SLICE_X127Y75 LUT6 (Prop_lut6_I1_O) 0.306 8.081 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/O
|
|
net (fo=1, routed) 0.620 8.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_5
|
|
SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/I5
|
|
SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.825 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/O
|
|
net (fo=1, routed) 0.419 9.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0_n_0
|
|
SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/I0
|
|
SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.368 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/O
|
|
net (fo=1, routed) 0.709 10.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[3]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[3])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.077
|
|
-------------------------------------------------------------------
|
|
slack 0.091
|
|
|
|
Slack (MET) : 0.091ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.597ns (logic 3.064ns (24.324%) route 9.533ns (75.676%))
|
|
Logic Levels: 12 (CARRY4=1 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_O[3])
|
|
0.606 6.827 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/O[3]
|
|
net (fo=2, routed) 0.948 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[3]
|
|
SLICE_X127Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/I1
|
|
SLICE_X127Y75 LUT6 (Prop_lut6_I1_O) 0.306 8.081 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/O
|
|
net (fo=1, routed) 0.620 8.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_5
|
|
SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/I5
|
|
SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.825 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/O
|
|
net (fo=1, routed) 0.419 9.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0_n_0
|
|
SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/I0
|
|
SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.368 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/O
|
|
net (fo=1, routed) 0.709 10.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[3]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[3])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.077
|
|
-------------------------------------------------------------------
|
|
slack 0.091
|
|
|
|
Slack (MET) : 0.125ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[18]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.605ns (logic 5.201ns (33.326%) route 10.404ns (66.674%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4
|
|
SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=136, routed) 1.291 2.268 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA1
|
|
SLICE_X20Y79 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR1
|
|
SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.146 2.414 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O
|
|
net (fo=1, routed) 0.661 3.075 u_matmul_axi_slave/ep_rd_c1[18]
|
|
SLICE_X21Y79 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/I0
|
|
SLICE_X21Y79 LUT4 (Prop_lut4_I0_O) 0.328 3.403 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/O
|
|
net (fo=1, routed) 0.671 4.074 u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0_n_0
|
|
SLICE_X25Y79 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/I4
|
|
SLICE_X25Y79 LUT5 (Prop_lut5_I4_O) 0.124 4.198 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/O
|
|
net (fo=1, routed) 0.578 4.776 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[18]
|
|
SLICE_X29Y79 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/I5
|
|
SLICE_X29Y79 LUT6 (Prop_lut6_I5_O) 0.124 4.900 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/O
|
|
net (fo=3, routed) 0.632 5.532 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18]
|
|
SLICE_X29Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0
|
|
SLICE_X29Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.656 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O
|
|
net (fo=2, routed) 4.015 9.671 ext_ram_data_IOBUF[18]_inst/I
|
|
AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I
|
|
AB17 OBUFT (Prop_obuft_I_O) 3.527 13.197 r ext_ram_data_IOBUF[18]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.197 ext_ram_data[18]
|
|
AB17 r ext_ram_data[18] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -13.197
|
|
-------------------------------------------------------------------
|
|
slack 0.125
|
|
|
|
Slack (MET) : 0.125ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[18]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.605ns (logic 5.201ns (33.326%) route 10.404ns (66.674%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4
|
|
SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=136, routed) 1.291 2.268 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA1
|
|
SLICE_X20Y79 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR1
|
|
SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.146 2.414 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O
|
|
net (fo=1, routed) 0.661 3.075 u_matmul_axi_slave/ep_rd_c1[18]
|
|
SLICE_X21Y79 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/I0
|
|
SLICE_X21Y79 LUT4 (Prop_lut4_I0_O) 0.328 3.403 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/O
|
|
net (fo=1, routed) 0.671 4.074 u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0_n_0
|
|
SLICE_X25Y79 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/I4
|
|
SLICE_X25Y79 LUT5 (Prop_lut5_I4_O) 0.124 4.198 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/O
|
|
net (fo=1, routed) 0.578 4.776 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[18]
|
|
SLICE_X29Y79 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/I5
|
|
SLICE_X29Y79 LUT6 (Prop_lut6_I5_O) 0.124 4.900 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/O
|
|
net (fo=3, routed) 0.632 5.532 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18]
|
|
SLICE_X29Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0
|
|
SLICE_X29Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.656 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O
|
|
net (fo=2, routed) 4.015 9.671 ext_ram_data_IOBUF[18]_inst/I
|
|
AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I
|
|
AB17 OBUFT (Prop_obuft_I_O) 3.527 13.197 r ext_ram_data_IOBUF[18]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.197 ext_ram_data[18]
|
|
AB17 r ext_ram_data[18] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -13.197
|
|
-------------------------------------------------------------------
|
|
slack 0.125
|
|
|
|
Slack (MET) : 0.125ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[18]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.605ns (logic 5.201ns (33.326%) route 10.404ns (66.674%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4
|
|
SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=136, routed) 1.291 2.268 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA1
|
|
SLICE_X20Y79 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR1
|
|
SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.146 2.414 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O
|
|
net (fo=1, routed) 0.661 3.075 u_matmul_axi_slave/ep_rd_c1[18]
|
|
SLICE_X21Y79 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/I0
|
|
SLICE_X21Y79 LUT4 (Prop_lut4_I0_O) 0.328 3.403 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/O
|
|
net (fo=1, routed) 0.671 4.074 u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0_n_0
|
|
SLICE_X25Y79 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/I4
|
|
SLICE_X25Y79 LUT5 (Prop_lut5_I4_O) 0.124 4.198 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/O
|
|
net (fo=1, routed) 0.578 4.776 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[18]
|
|
SLICE_X29Y79 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/I5
|
|
SLICE_X29Y79 LUT6 (Prop_lut6_I5_O) 0.124 4.900 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/O
|
|
net (fo=3, routed) 0.632 5.532 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18]
|
|
SLICE_X29Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0
|
|
SLICE_X29Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.656 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O
|
|
net (fo=2, routed) 4.015 9.671 ext_ram_data_IOBUF[18]_inst/I
|
|
AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I
|
|
AB17 OBUFT (Prop_obuft_I_O) 3.527 13.197 r ext_ram_data_IOBUF[18]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.197 ext_ram_data[18]
|
|
AB17 r ext_ram_data[18] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -13.197
|
|
-------------------------------------------------------------------
|
|
slack 0.125
|
|
|
|
Slack (MET) : 0.125ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[18]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.605ns (logic 5.201ns (33.326%) route 10.404ns (66.674%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4
|
|
SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=136, routed) 1.291 2.268 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA1
|
|
SLICE_X20Y79 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR1
|
|
SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.146 2.414 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O
|
|
net (fo=1, routed) 0.661 3.075 u_matmul_axi_slave/ep_rd_c1[18]
|
|
SLICE_X21Y79 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/I0
|
|
SLICE_X21Y79 LUT4 (Prop_lut4_I0_O) 0.328 3.403 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/O
|
|
net (fo=1, routed) 0.671 4.074 u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0_n_0
|
|
SLICE_X25Y79 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/I4
|
|
SLICE_X25Y79 LUT5 (Prop_lut5_I4_O) 0.124 4.198 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/O
|
|
net (fo=1, routed) 0.578 4.776 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[18]
|
|
SLICE_X29Y79 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/I5
|
|
SLICE_X29Y79 LUT6 (Prop_lut6_I5_O) 0.124 4.900 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/O
|
|
net (fo=3, routed) 0.632 5.532 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18]
|
|
SLICE_X29Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0
|
|
SLICE_X29Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.656 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O
|
|
net (fo=2, routed) 4.015 9.671 ext_ram_data_IOBUF[18]_inst/I
|
|
AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I
|
|
AB17 OBUFT (Prop_obuft_I_O) 3.527 13.197 r ext_ram_data_IOBUF[18]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.197 ext_ram_data[18]
|
|
AB17 r ext_ram_data[18] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -13.197
|
|
-------------------------------------------------------------------
|
|
slack 0.125
|
|
|
|
Slack (MET) : 0.125ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[18]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.605ns (logic 5.201ns (33.326%) route 10.404ns (66.674%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4
|
|
SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=136, routed) 1.291 2.268 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA1
|
|
SLICE_X20Y79 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR1
|
|
SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.146 2.414 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O
|
|
net (fo=1, routed) 0.661 3.075 u_matmul_axi_slave/ep_rd_c1[18]
|
|
SLICE_X21Y79 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/I0
|
|
SLICE_X21Y79 LUT4 (Prop_lut4_I0_O) 0.328 3.403 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/O
|
|
net (fo=1, routed) 0.671 4.074 u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0_n_0
|
|
SLICE_X25Y79 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/I4
|
|
SLICE_X25Y79 LUT5 (Prop_lut5_I4_O) 0.124 4.198 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/O
|
|
net (fo=1, routed) 0.578 4.776 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[18]
|
|
SLICE_X29Y79 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/I5
|
|
SLICE_X29Y79 LUT6 (Prop_lut6_I5_O) 0.124 4.900 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/O
|
|
net (fo=3, routed) 0.632 5.532 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18]
|
|
SLICE_X29Y80 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0
|
|
SLICE_X29Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.656 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O
|
|
net (fo=2, routed) 4.015 9.671 ext_ram_data_IOBUF[18]_inst/I
|
|
AB17 f ext_ram_data_IOBUF[18]_inst/OBUFT/I
|
|
AB17 OBUFT (Prop_obuft_I_O) 3.527 13.197 f ext_ram_data_IOBUF[18]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.197 ext_ram_data[18]
|
|
AB17 f ext_ram_data[18] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -13.197
|
|
-------------------------------------------------------------------
|
|
slack 0.125
|
|
|
|
Slack (MET) : 0.125ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[18]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.605ns (logic 5.201ns (33.326%) route 10.404ns (66.674%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4
|
|
SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=136, routed) 1.291 2.268 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA1
|
|
SLICE_X20Y79 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR1
|
|
SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.146 2.414 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O
|
|
net (fo=1, routed) 0.661 3.075 u_matmul_axi_slave/ep_rd_c1[18]
|
|
SLICE_X21Y79 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/I0
|
|
SLICE_X21Y79 LUT4 (Prop_lut4_I0_O) 0.328 3.403 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/O
|
|
net (fo=1, routed) 0.671 4.074 u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0_n_0
|
|
SLICE_X25Y79 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/I4
|
|
SLICE_X25Y79 LUT5 (Prop_lut5_I4_O) 0.124 4.198 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/O
|
|
net (fo=1, routed) 0.578 4.776 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[18]
|
|
SLICE_X29Y79 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/I5
|
|
SLICE_X29Y79 LUT6 (Prop_lut6_I5_O) 0.124 4.900 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/O
|
|
net (fo=3, routed) 0.632 5.532 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18]
|
|
SLICE_X29Y80 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0
|
|
SLICE_X29Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.656 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O
|
|
net (fo=2, routed) 4.015 9.671 ext_ram_data_IOBUF[18]_inst/I
|
|
AB17 f ext_ram_data_IOBUF[18]_inst/OBUFT/I
|
|
AB17 OBUFT (Prop_obuft_I_O) 3.527 13.197 f ext_ram_data_IOBUF[18]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.197 ext_ram_data[18]
|
|
AB17 f ext_ram_data[18] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -13.197
|
|
-------------------------------------------------------------------
|
|
slack 0.125
|
|
|
|
Slack (MET) : 0.125ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[18]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.605ns (logic 5.201ns (33.326%) route 10.404ns (66.674%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4
|
|
SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=136, routed) 1.291 2.268 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA1
|
|
SLICE_X20Y79 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR1
|
|
SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.146 2.414 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O
|
|
net (fo=1, routed) 0.661 3.075 u_matmul_axi_slave/ep_rd_c1[18]
|
|
SLICE_X21Y79 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/I0
|
|
SLICE_X21Y79 LUT4 (Prop_lut4_I0_O) 0.328 3.403 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/O
|
|
net (fo=1, routed) 0.671 4.074 u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0_n_0
|
|
SLICE_X25Y79 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/I4
|
|
SLICE_X25Y79 LUT5 (Prop_lut5_I4_O) 0.124 4.198 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/O
|
|
net (fo=1, routed) 0.578 4.776 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[18]
|
|
SLICE_X29Y79 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/I5
|
|
SLICE_X29Y79 LUT6 (Prop_lut6_I5_O) 0.124 4.900 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/O
|
|
net (fo=3, routed) 0.632 5.532 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18]
|
|
SLICE_X29Y80 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0
|
|
SLICE_X29Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.656 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O
|
|
net (fo=2, routed) 4.015 9.671 ext_ram_data_IOBUF[18]_inst/I
|
|
AB17 f ext_ram_data_IOBUF[18]_inst/OBUFT/I
|
|
AB17 OBUFT (Prop_obuft_I_O) 3.527 13.197 f ext_ram_data_IOBUF[18]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.197 ext_ram_data[18]
|
|
AB17 f ext_ram_data[18] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -13.197
|
|
-------------------------------------------------------------------
|
|
slack 0.125
|
|
|
|
Slack (MET) : 0.125ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[18]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.605ns (logic 5.201ns (33.326%) route 10.404ns (66.674%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4
|
|
SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=136, routed) 1.291 2.268 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA1
|
|
SLICE_X20Y79 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR1
|
|
SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.146 2.414 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O
|
|
net (fo=1, routed) 0.661 3.075 u_matmul_axi_slave/ep_rd_c1[18]
|
|
SLICE_X21Y79 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/I0
|
|
SLICE_X21Y79 LUT4 (Prop_lut4_I0_O) 0.328 3.403 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/O
|
|
net (fo=1, routed) 0.671 4.074 u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0_n_0
|
|
SLICE_X25Y79 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/I4
|
|
SLICE_X25Y79 LUT5 (Prop_lut5_I4_O) 0.124 4.198 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/O
|
|
net (fo=1, routed) 0.578 4.776 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[18]
|
|
SLICE_X29Y79 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/I5
|
|
SLICE_X29Y79 LUT6 (Prop_lut6_I5_O) 0.124 4.900 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/O
|
|
net (fo=3, routed) 0.632 5.532 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18]
|
|
SLICE_X29Y80 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0
|
|
SLICE_X29Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.656 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O
|
|
net (fo=2, routed) 4.015 9.671 ext_ram_data_IOBUF[18]_inst/I
|
|
AB17 f ext_ram_data_IOBUF[18]_inst/OBUFT/I
|
|
AB17 OBUFT (Prop_obuft_I_O) 3.527 13.197 f ext_ram_data_IOBUF[18]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.197 ext_ram_data[18]
|
|
AB17 f ext_ram_data[18] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -13.197
|
|
-------------------------------------------------------------------
|
|
slack 0.125
|
|
|
|
Slack (MET) : 0.128ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 13.053ns (logic 0.752ns (5.761%) route 12.301ns (94.239%))
|
|
Logic Levels: 1 (MUXF7=1)
|
|
Clock Path Skew: 0.210ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 )
|
|
Source Clock Delay (SCD): -2.480ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.796 -2.480
|
|
SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
|
|
SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q
|
|
net (fo=1088, routed) 12.301 10.277 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2
|
|
SLICE_X163Y34 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[948]_i_1/S
|
|
SLICE_X163Y34 MUXF7 (Prop_muxf7_S_O) 0.296 10.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[948]_i_1/O
|
|
net (fo=1, routed) 0.000 10.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[948]
|
|
SLICE_X163Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.903 11.228
|
|
clock pessimism -0.498 10.730
|
|
clock uncertainty -0.093 10.637
|
|
SLICE_X163Y34 FDCE (Setup_fdce_C_D) 0.064 10.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]
|
|
-------------------------------------------------------------------
|
|
required time 10.701
|
|
arrival time -10.573
|
|
-------------------------------------------------------------------
|
|
slack 0.128
|
|
|
|
Slack (MET) : 0.128ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 13.053ns (logic 0.752ns (5.761%) route 12.301ns (94.239%))
|
|
Logic Levels: 1 (MUXF7=1)
|
|
Clock Path Skew: 0.210ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 )
|
|
Source Clock Delay (SCD): -2.480ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.796 -2.480
|
|
SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
|
|
SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q
|
|
net (fo=1088, routed) 12.301 10.277 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2
|
|
SLICE_X163Y34 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[948]_i_1/S
|
|
SLICE_X163Y34 MUXF7 (Prop_muxf7_S_O) 0.296 10.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[948]_i_1/O
|
|
net (fo=1, routed) 0.000 10.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[948]
|
|
SLICE_X163Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.903 11.228
|
|
clock pessimism -0.498 10.730
|
|
clock uncertainty -0.093 10.637
|
|
SLICE_X163Y34 FDCE (Setup_fdce_C_D) 0.064 10.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]
|
|
-------------------------------------------------------------------
|
|
required time 10.701
|
|
arrival time -10.573
|
|
-------------------------------------------------------------------
|
|
slack 0.128
|
|
|
|
Slack (MET) : 0.128ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 13.053ns (logic 0.752ns (5.761%) route 12.301ns (94.239%))
|
|
Logic Levels: 1 (MUXF7=1)
|
|
Clock Path Skew: 0.210ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 )
|
|
Source Clock Delay (SCD): -2.480ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.796 -2.480
|
|
SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
|
|
SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q
|
|
net (fo=1088, routed) 12.301 10.277 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2
|
|
SLICE_X163Y34 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[948]_i_1/S
|
|
SLICE_X163Y34 MUXF7 (Prop_muxf7_S_O) 0.296 10.573 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[948]_i_1/O
|
|
net (fo=1, routed) 0.000 10.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[948]
|
|
SLICE_X163Y34 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.903 11.228
|
|
clock pessimism -0.498 10.730
|
|
clock uncertainty -0.093 10.637
|
|
SLICE_X163Y34 FDCE (Setup_fdce_C_D) 0.064 10.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]
|
|
-------------------------------------------------------------------
|
|
required time 10.701
|
|
arrival time -10.573
|
|
-------------------------------------------------------------------
|
|
slack 0.128
|
|
|
|
Slack (MET) : 0.128ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 13.053ns (logic 0.752ns (5.761%) route 12.301ns (94.239%))
|
|
Logic Levels: 1 (MUXF7=1)
|
|
Clock Path Skew: 0.210ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 )
|
|
Source Clock Delay (SCD): -2.480ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.796 -2.480
|
|
SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
|
|
SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q
|
|
net (fo=1088, routed) 12.301 10.277 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2
|
|
SLICE_X163Y34 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[948]_i_1/S
|
|
SLICE_X163Y34 MUXF7 (Prop_muxf7_S_O) 0.296 10.573 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[948]_i_1/O
|
|
net (fo=1, routed) 0.000 10.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[948]
|
|
SLICE_X163Y34 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.903 11.228
|
|
clock pessimism -0.498 10.730
|
|
clock uncertainty -0.093 10.637
|
|
SLICE_X163Y34 FDCE (Setup_fdce_C_D) 0.064 10.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]
|
|
-------------------------------------------------------------------
|
|
required time 10.701
|
|
arrival time -10.573
|
|
-------------------------------------------------------------------
|
|
slack 0.128
|
|
|
|
Slack (MET) : 0.129ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.558ns (logic 3.335ns (26.557%) route 9.223ns (73.443%))
|
|
Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 7.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[1]
|
|
net (fo=2, routed) 1.107 8.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[5]
|
|
SLICE_X130Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/I1
|
|
SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.303 8.510 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/O
|
|
net (fo=1, routed) 0.438 8.948 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_7
|
|
SLICE_X134Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/I5
|
|
SLICE_X134Y74 LUT6 (Prop_lut6_I5_O) 0.124 9.072 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/O
|
|
net (fo=1, routed) 0.438 9.510 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0_n_0
|
|
SLICE_X138Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/I0
|
|
SLICE_X138Y74 LUT5 (Prop_lut5_I0_O) 0.124 9.634 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/O
|
|
net (fo=1, routed) 0.404 10.038 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[5]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[5])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.038
|
|
-------------------------------------------------------------------
|
|
slack 0.129
|
|
|
|
Slack (MET) : 0.129ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.558ns (logic 3.335ns (26.557%) route 9.223ns (73.443%))
|
|
Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 7.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[1]
|
|
net (fo=2, routed) 1.107 8.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[5]
|
|
SLICE_X130Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/I1
|
|
SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.303 8.510 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/O
|
|
net (fo=1, routed) 0.438 8.948 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_7
|
|
SLICE_X134Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/I5
|
|
SLICE_X134Y74 LUT6 (Prop_lut6_I5_O) 0.124 9.072 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/O
|
|
net (fo=1, routed) 0.438 9.510 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0_n_0
|
|
SLICE_X138Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/I0
|
|
SLICE_X138Y74 LUT5 (Prop_lut5_I0_O) 0.124 9.634 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/O
|
|
net (fo=1, routed) 0.404 10.038 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[5]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[5])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.038
|
|
-------------------------------------------------------------------
|
|
slack 0.129
|
|
|
|
Slack (MET) : 0.129ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.558ns (logic 3.335ns (26.557%) route 9.223ns (73.443%))
|
|
Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 7.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[1]
|
|
net (fo=2, routed) 1.107 8.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[5]
|
|
SLICE_X130Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/I1
|
|
SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.303 8.510 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/O
|
|
net (fo=1, routed) 0.438 8.948 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_7
|
|
SLICE_X134Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/I5
|
|
SLICE_X134Y74 LUT6 (Prop_lut6_I5_O) 0.124 9.072 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/O
|
|
net (fo=1, routed) 0.438 9.510 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0_n_0
|
|
SLICE_X138Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/I0
|
|
SLICE_X138Y74 LUT5 (Prop_lut5_I0_O) 0.124 9.634 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/O
|
|
net (fo=1, routed) 0.404 10.038 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[5]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[5])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.038
|
|
-------------------------------------------------------------------
|
|
slack 0.129
|
|
|
|
Slack (MET) : 0.129ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.558ns (logic 3.335ns (26.557%) route 9.223ns (73.443%))
|
|
Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 7.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[1]
|
|
net (fo=2, routed) 1.107 8.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[5]
|
|
SLICE_X130Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/I1
|
|
SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.303 8.510 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/O
|
|
net (fo=1, routed) 0.438 8.948 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_7
|
|
SLICE_X134Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/I5
|
|
SLICE_X134Y74 LUT6 (Prop_lut6_I5_O) 0.124 9.072 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/O
|
|
net (fo=1, routed) 0.438 9.510 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0_n_0
|
|
SLICE_X138Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/I0
|
|
SLICE_X138Y74 LUT5 (Prop_lut5_I0_O) 0.124 9.634 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/O
|
|
net (fo=1, routed) 0.404 10.038 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[5]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[5])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.038
|
|
-------------------------------------------------------------------
|
|
slack 0.129
|
|
|
|
Slack (MET) : 0.129ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.558ns (logic 3.335ns (26.557%) route 9.223ns (73.443%))
|
|
Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 7.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[1]
|
|
net (fo=2, routed) 1.107 8.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[5]
|
|
SLICE_X130Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/I1
|
|
SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.303 8.510 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/O
|
|
net (fo=1, routed) 0.438 8.948 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_7
|
|
SLICE_X134Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/I5
|
|
SLICE_X134Y74 LUT6 (Prop_lut6_I5_O) 0.124 9.072 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/O
|
|
net (fo=1, routed) 0.438 9.510 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0_n_0
|
|
SLICE_X138Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/I0
|
|
SLICE_X138Y74 LUT5 (Prop_lut5_I0_O) 0.124 9.634 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/O
|
|
net (fo=1, routed) 0.404 10.038 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[5]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[5])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.038
|
|
-------------------------------------------------------------------
|
|
slack 0.129
|
|
|
|
Slack (MET) : 0.129ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.558ns (logic 3.335ns (26.557%) route 9.223ns (73.443%))
|
|
Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 7.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[1]
|
|
net (fo=2, routed) 1.107 8.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[5]
|
|
SLICE_X130Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/I1
|
|
SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.303 8.510 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/O
|
|
net (fo=1, routed) 0.438 8.948 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_7
|
|
SLICE_X134Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/I5
|
|
SLICE_X134Y74 LUT6 (Prop_lut6_I5_O) 0.124 9.072 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/O
|
|
net (fo=1, routed) 0.438 9.510 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0_n_0
|
|
SLICE_X138Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/I0
|
|
SLICE_X138Y74 LUT5 (Prop_lut5_I0_O) 0.124 9.634 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/O
|
|
net (fo=1, routed) 0.404 10.038 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[5]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[5])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.038
|
|
-------------------------------------------------------------------
|
|
slack 0.129
|
|
|
|
Slack (MET) : 0.129ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.558ns (logic 3.335ns (26.557%) route 9.223ns (73.443%))
|
|
Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 7.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[1]
|
|
net (fo=2, routed) 1.107 8.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[5]
|
|
SLICE_X130Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/I1
|
|
SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.303 8.510 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/O
|
|
net (fo=1, routed) 0.438 8.948 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_7
|
|
SLICE_X134Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/I5
|
|
SLICE_X134Y74 LUT6 (Prop_lut6_I5_O) 0.124 9.072 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/O
|
|
net (fo=1, routed) 0.438 9.510 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0_n_0
|
|
SLICE_X138Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/I0
|
|
SLICE_X138Y74 LUT5 (Prop_lut5_I0_O) 0.124 9.634 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/O
|
|
net (fo=1, routed) 0.404 10.038 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[5]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[5])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.038
|
|
-------------------------------------------------------------------
|
|
slack 0.129
|
|
|
|
Slack (MET) : 0.129ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.558ns (logic 3.335ns (26.557%) route 9.223ns (73.443%))
|
|
Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 7.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[1]
|
|
net (fo=2, routed) 1.107 8.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[5]
|
|
SLICE_X130Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/I1
|
|
SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.303 8.510 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/O
|
|
net (fo=1, routed) 0.438 8.948 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_7
|
|
SLICE_X134Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/I5
|
|
SLICE_X134Y74 LUT6 (Prop_lut6_I5_O) 0.124 9.072 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/O
|
|
net (fo=1, routed) 0.438 9.510 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0_n_0
|
|
SLICE_X138Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/I0
|
|
SLICE_X138Y74 LUT5 (Prop_lut5_I0_O) 0.124 9.634 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/O
|
|
net (fo=1, routed) 0.404 10.038 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[5]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[5])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.038
|
|
-------------------------------------------------------------------
|
|
slack 0.129
|
|
|
|
Slack (MET) : 0.129ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.558ns (logic 3.335ns (26.557%) route 9.223ns (73.443%))
|
|
Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 7.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[1]
|
|
net (fo=2, routed) 1.107 8.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[5]
|
|
SLICE_X130Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/I1
|
|
SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.303 8.510 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/O
|
|
net (fo=1, routed) 0.438 8.948 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_7
|
|
SLICE_X134Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/I5
|
|
SLICE_X134Y74 LUT6 (Prop_lut6_I5_O) 0.124 9.072 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/O
|
|
net (fo=1, routed) 0.438 9.510 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0_n_0
|
|
SLICE_X138Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/I0
|
|
SLICE_X138Y74 LUT5 (Prop_lut5_I0_O) 0.124 9.634 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/O
|
|
net (fo=1, routed) 0.404 10.038 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[5]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[5])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.038
|
|
-------------------------------------------------------------------
|
|
slack 0.129
|
|
|
|
Slack (MET) : 0.129ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.558ns (logic 3.335ns (26.557%) route 9.223ns (73.443%))
|
|
Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 7.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[1]
|
|
net (fo=2, routed) 1.107 8.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[5]
|
|
SLICE_X130Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/I1
|
|
SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.303 8.510 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/O
|
|
net (fo=1, routed) 0.438 8.948 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_7
|
|
SLICE_X134Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/I5
|
|
SLICE_X134Y74 LUT6 (Prop_lut6_I5_O) 0.124 9.072 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/O
|
|
net (fo=1, routed) 0.438 9.510 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0_n_0
|
|
SLICE_X138Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/I0
|
|
SLICE_X138Y74 LUT5 (Prop_lut5_I0_O) 0.124 9.634 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/O
|
|
net (fo=1, routed) 0.404 10.038 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[5]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[5])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.038
|
|
-------------------------------------------------------------------
|
|
slack 0.129
|
|
|
|
Slack (MET) : 0.135ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.971ns (logic 0.732ns (5.643%) route 12.239ns (94.357%))
|
|
Logic Levels: 1 (MUXF7=1)
|
|
Clock Path Skew: 0.135ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.847ns = ( 11.153 - 13.000 )
|
|
Source Clock Delay (SCD): -2.480ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.796 -2.480
|
|
SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
|
|
SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q
|
|
net (fo=1088, routed) 12.239 10.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2
|
|
SLICE_X145Y37 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[731]_i_1/S
|
|
SLICE_X145Y37 MUXF7 (Prop_muxf7_S_O) 0.276 10.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[731]_i_1/O
|
|
net (fo=1, routed) 0.000 10.491 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[731]
|
|
SLICE_X145Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.828 11.153
|
|
clock pessimism -0.498 10.655
|
|
clock uncertainty -0.093 10.562
|
|
SLICE_X145Y37 FDCE (Setup_fdce_C_D) 0.064 10.626 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]
|
|
-------------------------------------------------------------------
|
|
required time 10.626
|
|
arrival time -10.491
|
|
-------------------------------------------------------------------
|
|
slack 0.135
|
|
|
|
Slack (MET) : 0.135ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.971ns (logic 0.732ns (5.643%) route 12.239ns (94.357%))
|
|
Logic Levels: 1 (MUXF7=1)
|
|
Clock Path Skew: 0.135ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.847ns = ( 11.153 - 13.000 )
|
|
Source Clock Delay (SCD): -2.480ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.796 -2.480
|
|
SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
|
|
SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q
|
|
net (fo=1088, routed) 12.239 10.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2
|
|
SLICE_X145Y37 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[731]_i_1/S
|
|
SLICE_X145Y37 MUXF7 (Prop_muxf7_S_O) 0.276 10.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[731]_i_1/O
|
|
net (fo=1, routed) 0.000 10.491 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[731]
|
|
SLICE_X145Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.828 11.153
|
|
clock pessimism -0.498 10.655
|
|
clock uncertainty -0.093 10.562
|
|
SLICE_X145Y37 FDCE (Setup_fdce_C_D) 0.064 10.626 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]
|
|
-------------------------------------------------------------------
|
|
required time 10.626
|
|
arrival time -10.491
|
|
-------------------------------------------------------------------
|
|
slack 0.135
|
|
|
|
Slack (MET) : 0.135ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.971ns (logic 0.732ns (5.643%) route 12.239ns (94.357%))
|
|
Logic Levels: 1 (MUXF7=1)
|
|
Clock Path Skew: 0.135ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.847ns = ( 11.153 - 13.000 )
|
|
Source Clock Delay (SCD): -2.480ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.796 -2.480
|
|
SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
|
|
SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q
|
|
net (fo=1088, routed) 12.239 10.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2
|
|
SLICE_X145Y37 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[731]_i_1/S
|
|
SLICE_X145Y37 MUXF7 (Prop_muxf7_S_O) 0.276 10.491 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[731]_i_1/O
|
|
net (fo=1, routed) 0.000 10.491 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[731]
|
|
SLICE_X145Y37 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.828 11.153
|
|
clock pessimism -0.498 10.655
|
|
clock uncertainty -0.093 10.562
|
|
SLICE_X145Y37 FDCE (Setup_fdce_C_D) 0.064 10.626 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]
|
|
-------------------------------------------------------------------
|
|
required time 10.626
|
|
arrival time -10.491
|
|
-------------------------------------------------------------------
|
|
slack 0.135
|
|
|
|
Slack (MET) : 0.135ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.971ns (logic 0.732ns (5.643%) route 12.239ns (94.357%))
|
|
Logic Levels: 1 (MUXF7=1)
|
|
Clock Path Skew: 0.135ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.847ns = ( 11.153 - 13.000 )
|
|
Source Clock Delay (SCD): -2.480ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.796 -2.480
|
|
SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
|
|
SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q
|
|
net (fo=1088, routed) 12.239 10.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2
|
|
SLICE_X145Y37 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[731]_i_1/S
|
|
SLICE_X145Y37 MUXF7 (Prop_muxf7_S_O) 0.276 10.491 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[731]_i_1/O
|
|
net (fo=1, routed) 0.000 10.491 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[731]
|
|
SLICE_X145Y37 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.828 11.153
|
|
clock pessimism -0.498 10.655
|
|
clock uncertainty -0.093 10.562
|
|
SLICE_X145Y37 FDCE (Setup_fdce_C_D) 0.064 10.626 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]
|
|
-------------------------------------------------------------------
|
|
required time 10.626
|
|
arrival time -10.491
|
|
-------------------------------------------------------------------
|
|
slack 0.135
|
|
|
|
Slack (MET) : 0.151ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5]
|
|
(rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.581ns (logic 3.752ns (29.822%) route 8.829ns (70.178%))
|
|
Logic Levels: 16 (CARRY4=3 LUT2=1 LUT5=3 LUT6=5 MUXF7=2 MUXF8=2)
|
|
Clock Path Skew: 0.066ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 )
|
|
Source Clock Delay (SCD): -2.481ns
|
|
Clock Pessimism Removal (CPR): -0.426ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.795 -2.481
|
|
SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q
|
|
net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0]
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4
|
|
SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O
|
|
net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1
|
|
SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O
|
|
net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1
|
|
SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O
|
|
net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5
|
|
SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O
|
|
net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0
|
|
SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O
|
|
net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1
|
|
SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O
|
|
net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0
|
|
SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1
|
|
SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O
|
|
net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0
|
|
SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0]
|
|
SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3]
|
|
net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0
|
|
SLICE_X134Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI
|
|
SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3]
|
|
net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0]
|
|
SLICE_X134Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI
|
|
SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0])
|
|
0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0]
|
|
net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0]
|
|
SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4
|
|
SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O
|
|
net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0
|
|
SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3
|
|
SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O
|
|
net (fo=29, routed) 0.725 6.593 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11
|
|
SLICE_X139Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/I3
|
|
SLICE_X139Y84 LUT5 (Prop_lut5_I3_O) 0.124 6.717 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/O
|
|
net (fo=4, routed) 0.833 7.549 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219_n_0
|
|
SLICE_X141Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/I3
|
|
SLICE_X141Y85 LUT6 (Prop_lut6_I3_O) 0.124 7.673 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/O
|
|
net (fo=2, routed) 0.809 8.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_21
|
|
SLICE_X140Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/I5
|
|
SLICE_X140Y86 LUT6 (Prop_lut6_I5_O) 0.124 8.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/O
|
|
net (fo=12, routed) 0.918 9.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76_n_0
|
|
SLICE_X140Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/I1
|
|
SLICE_X140Y87 LUT6 (Prop_lut6_I1_O) 0.124 9.648 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/O
|
|
net (fo=1, routed) 0.453 10.101 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[5]
|
|
RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.687 11.012
|
|
clock pessimism -0.426 10.586
|
|
clock uncertainty -0.093 10.493
|
|
RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[5])
|
|
-0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.252
|
|
arrival time -10.101
|
|
-------------------------------------------------------------------
|
|
slack 0.151
|
|
|
|
Slack (MET) : 0.151ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5]
|
|
(rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.581ns (logic 3.752ns (29.822%) route 8.829ns (70.178%))
|
|
Logic Levels: 16 (CARRY4=3 LUT2=1 LUT5=3 LUT6=5 MUXF7=2 MUXF8=2)
|
|
Clock Path Skew: 0.066ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 )
|
|
Source Clock Delay (SCD): -2.481ns
|
|
Clock Pessimism Removal (CPR): -0.426ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.795 -2.481
|
|
SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q
|
|
net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0]
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4
|
|
SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O
|
|
net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0
|
|
SLICE_X119Y93 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1
|
|
SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O
|
|
net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0
|
|
SLICE_X119Y93 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1
|
|
SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O
|
|
net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0
|
|
SLICE_X121Y90 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5
|
|
SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O
|
|
net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0
|
|
SLICE_X121Y90 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0
|
|
SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O
|
|
net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0
|
|
SLICE_X121Y90 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1
|
|
SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O
|
|
net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0
|
|
SLICE_X134Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1
|
|
SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O
|
|
net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0
|
|
SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0]
|
|
SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3]
|
|
net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0
|
|
SLICE_X134Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI
|
|
SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3]
|
|
net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0]
|
|
SLICE_X134Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI
|
|
SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0])
|
|
0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0]
|
|
net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0]
|
|
SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4
|
|
SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O
|
|
net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0
|
|
SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3
|
|
SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O
|
|
net (fo=29, routed) 0.725 6.593 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11
|
|
SLICE_X139Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/I3
|
|
SLICE_X139Y84 LUT5 (Prop_lut5_I3_O) 0.124 6.717 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/O
|
|
net (fo=4, routed) 0.833 7.549 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219_n_0
|
|
SLICE_X141Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/I3
|
|
SLICE_X141Y85 LUT6 (Prop_lut6_I3_O) 0.124 7.673 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/O
|
|
net (fo=2, routed) 0.809 8.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_21
|
|
SLICE_X140Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/I5
|
|
SLICE_X140Y86 LUT6 (Prop_lut6_I5_O) 0.124 8.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/O
|
|
net (fo=12, routed) 0.918 9.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76_n_0
|
|
SLICE_X140Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/I1
|
|
SLICE_X140Y87 LUT6 (Prop_lut6_I1_O) 0.124 9.648 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/O
|
|
net (fo=1, routed) 0.453 10.101 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[5]
|
|
RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.687 11.012
|
|
clock pessimism -0.426 10.586
|
|
clock uncertainty -0.093 10.493
|
|
RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[5])
|
|
-0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.252
|
|
arrival time -10.101
|
|
-------------------------------------------------------------------
|
|
slack 0.151
|
|
|
|
Slack (MET) : 0.151ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5]
|
|
(rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.581ns (logic 3.752ns (29.822%) route 8.829ns (70.178%))
|
|
Logic Levels: 16 (CARRY4=3 LUT2=1 LUT5=3 LUT6=5 MUXF7=2 MUXF8=2)
|
|
Clock Path Skew: 0.066ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 )
|
|
Source Clock Delay (SCD): -2.481ns
|
|
Clock Pessimism Removal (CPR): -0.426ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.795 -2.481
|
|
SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q
|
|
net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0]
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4
|
|
SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O
|
|
net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1
|
|
SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O
|
|
net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1
|
|
SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O
|
|
net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5
|
|
SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O
|
|
net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0
|
|
SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O
|
|
net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1
|
|
SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O
|
|
net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0
|
|
SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1
|
|
SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O
|
|
net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0
|
|
SLICE_X134Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0]
|
|
SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3]
|
|
net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0
|
|
SLICE_X134Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI
|
|
SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3]
|
|
net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0]
|
|
SLICE_X134Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI
|
|
SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0])
|
|
0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0]
|
|
net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0]
|
|
SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4
|
|
SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O
|
|
net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0
|
|
SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3
|
|
SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O
|
|
net (fo=29, routed) 0.725 6.593 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11
|
|
SLICE_X139Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/I3
|
|
SLICE_X139Y84 LUT5 (Prop_lut5_I3_O) 0.124 6.717 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/O
|
|
net (fo=4, routed) 0.833 7.549 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219_n_0
|
|
SLICE_X141Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/I3
|
|
SLICE_X141Y85 LUT6 (Prop_lut6_I3_O) 0.124 7.673 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/O
|
|
net (fo=2, routed) 0.809 8.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_21
|
|
SLICE_X140Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/I5
|
|
SLICE_X140Y86 LUT6 (Prop_lut6_I5_O) 0.124 8.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/O
|
|
net (fo=12, routed) 0.918 9.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76_n_0
|
|
SLICE_X140Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/I1
|
|
SLICE_X140Y87 LUT6 (Prop_lut6_I1_O) 0.124 9.648 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/O
|
|
net (fo=1, routed) 0.453 10.101 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[5]
|
|
RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.687 11.012
|
|
clock pessimism -0.426 10.586
|
|
clock uncertainty -0.093 10.493
|
|
RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[5])
|
|
-0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.252
|
|
arrival time -10.101
|
|
-------------------------------------------------------------------
|
|
slack 0.151
|
|
|
|
Slack (MET) : 0.151ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5]
|
|
(rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.581ns (logic 3.752ns (29.822%) route 8.829ns (70.178%))
|
|
Logic Levels: 16 (CARRY4=3 LUT2=1 LUT5=3 LUT6=5 MUXF7=2 MUXF8=2)
|
|
Clock Path Skew: 0.066ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 )
|
|
Source Clock Delay (SCD): -2.481ns
|
|
Clock Pessimism Removal (CPR): -0.426ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.795 -2.481
|
|
SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q
|
|
net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0]
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4
|
|
SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O
|
|
net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1
|
|
SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O
|
|
net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1
|
|
SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O
|
|
net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5
|
|
SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O
|
|
net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0
|
|
SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O
|
|
net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1
|
|
SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O
|
|
net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0
|
|
SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1
|
|
SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O
|
|
net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0
|
|
SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0]
|
|
SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 3.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3]
|
|
net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0
|
|
SLICE_X134Y86 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI
|
|
SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3]
|
|
net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0]
|
|
SLICE_X134Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI
|
|
SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0])
|
|
0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0]
|
|
net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0]
|
|
SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4
|
|
SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O
|
|
net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0
|
|
SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3
|
|
SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O
|
|
net (fo=29, routed) 0.725 6.593 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11
|
|
SLICE_X139Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/I3
|
|
SLICE_X139Y84 LUT5 (Prop_lut5_I3_O) 0.124 6.717 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/O
|
|
net (fo=4, routed) 0.833 7.549 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219_n_0
|
|
SLICE_X141Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/I3
|
|
SLICE_X141Y85 LUT6 (Prop_lut6_I3_O) 0.124 7.673 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/O
|
|
net (fo=2, routed) 0.809 8.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_21
|
|
SLICE_X140Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/I5
|
|
SLICE_X140Y86 LUT6 (Prop_lut6_I5_O) 0.124 8.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/O
|
|
net (fo=12, routed) 0.918 9.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76_n_0
|
|
SLICE_X140Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/I1
|
|
SLICE_X140Y87 LUT6 (Prop_lut6_I1_O) 0.124 9.648 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/O
|
|
net (fo=1, routed) 0.453 10.101 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[5]
|
|
RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.687 11.012
|
|
clock pessimism -0.426 10.586
|
|
clock uncertainty -0.093 10.493
|
|
RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[5])
|
|
-0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.252
|
|
arrival time -10.101
|
|
-------------------------------------------------------------------
|
|
slack 0.151
|
|
|
|
Slack (MET) : 0.151ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5]
|
|
(rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.581ns (logic 3.752ns (29.822%) route 8.829ns (70.178%))
|
|
Logic Levels: 16 (CARRY4=3 LUT2=1 LUT5=3 LUT6=5 MUXF7=2 MUXF8=2)
|
|
Clock Path Skew: 0.066ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 )
|
|
Source Clock Delay (SCD): -2.481ns
|
|
Clock Pessimism Removal (CPR): -0.426ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.795 -2.481
|
|
SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q
|
|
net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0]
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4
|
|
SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O
|
|
net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1
|
|
SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O
|
|
net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1
|
|
SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O
|
|
net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5
|
|
SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O
|
|
net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0
|
|
SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O
|
|
net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1
|
|
SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O
|
|
net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0
|
|
SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1
|
|
SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O
|
|
net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0
|
|
SLICE_X134Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0]
|
|
SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 3.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3]
|
|
net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0
|
|
SLICE_X134Y86 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI
|
|
SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3]
|
|
net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0]
|
|
SLICE_X134Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI
|
|
SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0])
|
|
0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0]
|
|
net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0]
|
|
SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4
|
|
SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O
|
|
net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0
|
|
SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3
|
|
SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O
|
|
net (fo=29, routed) 0.725 6.593 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11
|
|
SLICE_X139Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/I3
|
|
SLICE_X139Y84 LUT5 (Prop_lut5_I3_O) 0.124 6.717 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/O
|
|
net (fo=4, routed) 0.833 7.549 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219_n_0
|
|
SLICE_X141Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/I3
|
|
SLICE_X141Y85 LUT6 (Prop_lut6_I3_O) 0.124 7.673 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/O
|
|
net (fo=2, routed) 0.809 8.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_21
|
|
SLICE_X140Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/I5
|
|
SLICE_X140Y86 LUT6 (Prop_lut6_I5_O) 0.124 8.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/O
|
|
net (fo=12, routed) 0.918 9.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76_n_0
|
|
SLICE_X140Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/I1
|
|
SLICE_X140Y87 LUT6 (Prop_lut6_I1_O) 0.124 9.648 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/O
|
|
net (fo=1, routed) 0.453 10.101 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[5]
|
|
RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.687 11.012
|
|
clock pessimism -0.426 10.586
|
|
clock uncertainty -0.093 10.493
|
|
RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[5])
|
|
-0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.252
|
|
arrival time -10.101
|
|
-------------------------------------------------------------------
|
|
slack 0.151
|
|
|
|
Slack (MET) : 0.151ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5]
|
|
(rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.581ns (logic 3.752ns (29.822%) route 8.829ns (70.178%))
|
|
Logic Levels: 16 (CARRY4=3 LUT2=1 LUT5=3 LUT6=5 MUXF7=2 MUXF8=2)
|
|
Clock Path Skew: 0.066ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 )
|
|
Source Clock Delay (SCD): -2.481ns
|
|
Clock Pessimism Removal (CPR): -0.426ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.795 -2.481
|
|
SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q
|
|
net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0]
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4
|
|
SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O
|
|
net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1
|
|
SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O
|
|
net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1
|
|
SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O
|
|
net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5
|
|
SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O
|
|
net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0
|
|
SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O
|
|
net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1
|
|
SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O
|
|
net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0
|
|
SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1
|
|
SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O
|
|
net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0
|
|
SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0]
|
|
SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3]
|
|
net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0
|
|
SLICE_X134Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI
|
|
SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 3.327 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3]
|
|
net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0]
|
|
SLICE_X134Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI
|
|
SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0])
|
|
0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0]
|
|
net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0]
|
|
SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4
|
|
SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O
|
|
net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0
|
|
SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3
|
|
SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O
|
|
net (fo=29, routed) 0.725 6.593 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11
|
|
SLICE_X139Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/I3
|
|
SLICE_X139Y84 LUT5 (Prop_lut5_I3_O) 0.124 6.717 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/O
|
|
net (fo=4, routed) 0.833 7.549 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219_n_0
|
|
SLICE_X141Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/I3
|
|
SLICE_X141Y85 LUT6 (Prop_lut6_I3_O) 0.124 7.673 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/O
|
|
net (fo=2, routed) 0.809 8.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_21
|
|
SLICE_X140Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/I5
|
|
SLICE_X140Y86 LUT6 (Prop_lut6_I5_O) 0.124 8.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/O
|
|
net (fo=12, routed) 0.918 9.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76_n_0
|
|
SLICE_X140Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/I1
|
|
SLICE_X140Y87 LUT6 (Prop_lut6_I1_O) 0.124 9.648 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/O
|
|
net (fo=1, routed) 0.453 10.101 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[5]
|
|
RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.687 11.012
|
|
clock pessimism -0.426 10.586
|
|
clock uncertainty -0.093 10.493
|
|
RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[5])
|
|
-0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.252
|
|
arrival time -10.101
|
|
-------------------------------------------------------------------
|
|
slack 0.151
|
|
|
|
Slack (MET) : 0.151ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5]
|
|
(rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.581ns (logic 3.752ns (29.822%) route 8.829ns (70.178%))
|
|
Logic Levels: 16 (CARRY4=3 LUT2=1 LUT5=3 LUT6=5 MUXF7=2 MUXF8=2)
|
|
Clock Path Skew: 0.066ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 )
|
|
Source Clock Delay (SCD): -2.481ns
|
|
Clock Pessimism Removal (CPR): -0.426ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.795 -2.481
|
|
SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q
|
|
net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0]
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4
|
|
SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O
|
|
net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1
|
|
SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O
|
|
net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1
|
|
SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O
|
|
net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5
|
|
SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O
|
|
net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0
|
|
SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O
|
|
net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1
|
|
SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O
|
|
net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0
|
|
SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1
|
|
SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O
|
|
net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0
|
|
SLICE_X134Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0]
|
|
SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3]
|
|
net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0
|
|
SLICE_X134Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI
|
|
SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 3.327 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3]
|
|
net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0]
|
|
SLICE_X134Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI
|
|
SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0])
|
|
0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0]
|
|
net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0]
|
|
SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4
|
|
SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O
|
|
net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0
|
|
SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3
|
|
SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O
|
|
net (fo=29, routed) 0.725 6.593 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11
|
|
SLICE_X139Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/I3
|
|
SLICE_X139Y84 LUT5 (Prop_lut5_I3_O) 0.124 6.717 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/O
|
|
net (fo=4, routed) 0.833 7.549 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219_n_0
|
|
SLICE_X141Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/I3
|
|
SLICE_X141Y85 LUT6 (Prop_lut6_I3_O) 0.124 7.673 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/O
|
|
net (fo=2, routed) 0.809 8.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_21
|
|
SLICE_X140Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/I5
|
|
SLICE_X140Y86 LUT6 (Prop_lut6_I5_O) 0.124 8.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/O
|
|
net (fo=12, routed) 0.918 9.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76_n_0
|
|
SLICE_X140Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/I1
|
|
SLICE_X140Y87 LUT6 (Prop_lut6_I1_O) 0.124 9.648 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/O
|
|
net (fo=1, routed) 0.453 10.101 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[5]
|
|
RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.687 11.012
|
|
clock pessimism -0.426 10.586
|
|
clock uncertainty -0.093 10.493
|
|
RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[5])
|
|
-0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.252
|
|
arrival time -10.101
|
|
-------------------------------------------------------------------
|
|
slack 0.151
|
|
|
|
Slack (MET) : 0.151ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5]
|
|
(rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.581ns (logic 3.752ns (29.822%) route 8.829ns (70.178%))
|
|
Logic Levels: 16 (CARRY4=3 LUT2=1 LUT5=3 LUT6=5 MUXF7=2 MUXF8=2)
|
|
Clock Path Skew: 0.066ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 )
|
|
Source Clock Delay (SCD): -2.481ns
|
|
Clock Pessimism Removal (CPR): -0.426ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.795 -2.481
|
|
SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q
|
|
net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0]
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4
|
|
SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O
|
|
net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1
|
|
SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O
|
|
net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1
|
|
SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O
|
|
net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5
|
|
SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O
|
|
net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0
|
|
SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O
|
|
net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1
|
|
SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O
|
|
net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0
|
|
SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1
|
|
SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O
|
|
net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0
|
|
SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0]
|
|
SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 3.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3]
|
|
net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0
|
|
SLICE_X134Y86 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI
|
|
SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 3.327 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3]
|
|
net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0]
|
|
SLICE_X134Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI
|
|
SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0])
|
|
0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0]
|
|
net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0]
|
|
SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4
|
|
SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O
|
|
net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0
|
|
SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3
|
|
SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O
|
|
net (fo=29, routed) 0.725 6.593 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11
|
|
SLICE_X139Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/I3
|
|
SLICE_X139Y84 LUT5 (Prop_lut5_I3_O) 0.124 6.717 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/O
|
|
net (fo=4, routed) 0.833 7.549 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219_n_0
|
|
SLICE_X141Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/I3
|
|
SLICE_X141Y85 LUT6 (Prop_lut6_I3_O) 0.124 7.673 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/O
|
|
net (fo=2, routed) 0.809 8.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_21
|
|
SLICE_X140Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/I5
|
|
SLICE_X140Y86 LUT6 (Prop_lut6_I5_O) 0.124 8.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/O
|
|
net (fo=12, routed) 0.918 9.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76_n_0
|
|
SLICE_X140Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/I1
|
|
SLICE_X140Y87 LUT6 (Prop_lut6_I1_O) 0.124 9.648 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/O
|
|
net (fo=1, routed) 0.453 10.101 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[5]
|
|
RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.687 11.012
|
|
clock pessimism -0.426 10.586
|
|
clock uncertainty -0.093 10.493
|
|
RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[5])
|
|
-0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.252
|
|
arrival time -10.101
|
|
-------------------------------------------------------------------
|
|
slack 0.151
|
|
|
|
Slack (MET) : 0.151ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5]
|
|
(rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.581ns (logic 3.752ns (29.822%) route 8.829ns (70.178%))
|
|
Logic Levels: 16 (CARRY4=3 LUT2=1 LUT5=3 LUT6=5 MUXF7=2 MUXF8=2)
|
|
Clock Path Skew: 0.066ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 )
|
|
Source Clock Delay (SCD): -2.481ns
|
|
Clock Pessimism Removal (CPR): -0.426ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.795 -2.481
|
|
SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q
|
|
net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0]
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4
|
|
SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O
|
|
net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0
|
|
SLICE_X119Y93 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1
|
|
SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O
|
|
net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0
|
|
SLICE_X119Y93 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1
|
|
SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O
|
|
net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0
|
|
SLICE_X121Y90 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5
|
|
SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O
|
|
net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0
|
|
SLICE_X121Y90 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0
|
|
SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O
|
|
net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0
|
|
SLICE_X121Y90 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1
|
|
SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O
|
|
net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0
|
|
SLICE_X134Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1
|
|
SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O
|
|
net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0
|
|
SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0]
|
|
SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 3.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3]
|
|
net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0
|
|
SLICE_X134Y86 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI
|
|
SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 3.327 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3]
|
|
net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0]
|
|
SLICE_X134Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI
|
|
SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0])
|
|
0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0]
|
|
net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0]
|
|
SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4
|
|
SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O
|
|
net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0
|
|
SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3
|
|
SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O
|
|
net (fo=29, routed) 0.725 6.593 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11
|
|
SLICE_X139Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/I3
|
|
SLICE_X139Y84 LUT5 (Prop_lut5_I3_O) 0.124 6.717 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/O
|
|
net (fo=4, routed) 0.833 7.549 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219_n_0
|
|
SLICE_X141Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/I3
|
|
SLICE_X141Y85 LUT6 (Prop_lut6_I3_O) 0.124 7.673 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/O
|
|
net (fo=2, routed) 0.809 8.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_21
|
|
SLICE_X140Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/I5
|
|
SLICE_X140Y86 LUT6 (Prop_lut6_I5_O) 0.124 8.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/O
|
|
net (fo=12, routed) 0.918 9.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76_n_0
|
|
SLICE_X140Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/I1
|
|
SLICE_X140Y87 LUT6 (Prop_lut6_I1_O) 0.124 9.648 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/O
|
|
net (fo=1, routed) 0.453 10.101 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[5]
|
|
RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.687 11.012
|
|
clock pessimism -0.426 10.586
|
|
clock uncertainty -0.093 10.493
|
|
RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[5])
|
|
-0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.252
|
|
arrival time -10.101
|
|
-------------------------------------------------------------------
|
|
slack 0.151
|
|
|
|
Slack (MET) : 0.151ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5]
|
|
(rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.581ns (logic 3.752ns (29.822%) route 8.829ns (70.178%))
|
|
Logic Levels: 16 (CARRY4=3 LUT2=1 LUT5=3 LUT6=5 MUXF7=2 MUXF8=2)
|
|
Clock Path Skew: 0.066ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 )
|
|
Source Clock Delay (SCD): -2.481ns
|
|
Clock Pessimism Removal (CPR): -0.426ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.795 -2.481
|
|
SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q
|
|
net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0]
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4
|
|
SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O
|
|
net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1
|
|
SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O
|
|
net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1
|
|
SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O
|
|
net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5
|
|
SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O
|
|
net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0
|
|
SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O
|
|
net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1
|
|
SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O
|
|
net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0
|
|
SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1
|
|
SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O
|
|
net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0
|
|
SLICE_X134Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0]
|
|
SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 3.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3]
|
|
net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0
|
|
SLICE_X134Y86 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI
|
|
SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 3.327 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3]
|
|
net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0]
|
|
SLICE_X134Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI
|
|
SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0])
|
|
0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0]
|
|
net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0]
|
|
SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4
|
|
SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O
|
|
net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0
|
|
SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3
|
|
SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O
|
|
net (fo=29, routed) 0.725 6.593 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11
|
|
SLICE_X139Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/I3
|
|
SLICE_X139Y84 LUT5 (Prop_lut5_I3_O) 0.124 6.717 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/O
|
|
net (fo=4, routed) 0.833 7.549 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219_n_0
|
|
SLICE_X141Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/I3
|
|
SLICE_X141Y85 LUT6 (Prop_lut6_I3_O) 0.124 7.673 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/O
|
|
net (fo=2, routed) 0.809 8.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_21
|
|
SLICE_X140Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/I5
|
|
SLICE_X140Y86 LUT6 (Prop_lut6_I5_O) 0.124 8.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/O
|
|
net (fo=12, routed) 0.918 9.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76_n_0
|
|
SLICE_X140Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/I1
|
|
SLICE_X140Y87 LUT6 (Prop_lut6_I1_O) 0.124 9.648 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/O
|
|
net (fo=1, routed) 0.453 10.101 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[5]
|
|
RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.687 11.012
|
|
clock pessimism -0.426 10.586
|
|
clock uncertainty -0.093 10.493
|
|
RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[5])
|
|
-0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.252
|
|
arrival time -10.101
|
|
-------------------------------------------------------------------
|
|
slack 0.151
|
|
|
|
Slack (MET) : 0.155ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.532ns (logic 3.449ns (27.521%) route 9.083ns (72.479%))
|
|
Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3]
|
|
net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0
|
|
SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI
|
|
SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 7.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[1]
|
|
net (fo=2, routed) 0.351 7.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[9]
|
|
SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/I1
|
|
SLICE_X107Y75 LUT6 (Prop_lut6_I1_O) 0.303 7.878 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/O
|
|
net (fo=1, routed) 0.264 8.142 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_11
|
|
SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/I5
|
|
SLICE_X107Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.266 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/O
|
|
net (fo=1, routed) 0.991 9.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0_n_0
|
|
SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/I0
|
|
SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/O
|
|
net (fo=1, routed) 0.632 10.013 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[9]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[9])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.013
|
|
-------------------------------------------------------------------
|
|
slack 0.155
|
|
|
|
Slack (MET) : 0.155ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.532ns (logic 3.449ns (27.521%) route 9.083ns (72.479%))
|
|
Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3]
|
|
net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0
|
|
SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI
|
|
SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 7.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[1]
|
|
net (fo=2, routed) 0.351 7.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[9]
|
|
SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/I1
|
|
SLICE_X107Y75 LUT6 (Prop_lut6_I1_O) 0.303 7.878 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/O
|
|
net (fo=1, routed) 0.264 8.142 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_11
|
|
SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/I5
|
|
SLICE_X107Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.266 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/O
|
|
net (fo=1, routed) 0.991 9.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0_n_0
|
|
SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/I0
|
|
SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/O
|
|
net (fo=1, routed) 0.632 10.013 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[9]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[9])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.013
|
|
-------------------------------------------------------------------
|
|
slack 0.155
|
|
|
|
Slack (MET) : 0.155ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.532ns (logic 3.449ns (27.521%) route 9.083ns (72.479%))
|
|
Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3]
|
|
net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0
|
|
SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI
|
|
SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 7.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[1]
|
|
net (fo=2, routed) 0.351 7.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[9]
|
|
SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/I1
|
|
SLICE_X107Y75 LUT6 (Prop_lut6_I1_O) 0.303 7.878 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/O
|
|
net (fo=1, routed) 0.264 8.142 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_11
|
|
SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/I5
|
|
SLICE_X107Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.266 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/O
|
|
net (fo=1, routed) 0.991 9.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0_n_0
|
|
SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/I0
|
|
SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/O
|
|
net (fo=1, routed) 0.632 10.013 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[9]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[9])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.013
|
|
-------------------------------------------------------------------
|
|
slack 0.155
|
|
|
|
Slack (MET) : 0.155ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.532ns (logic 3.449ns (27.521%) route 9.083ns (72.479%))
|
|
Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3]
|
|
net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0
|
|
SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI
|
|
SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 7.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[1]
|
|
net (fo=2, routed) 0.351 7.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[9]
|
|
SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/I1
|
|
SLICE_X107Y75 LUT6 (Prop_lut6_I1_O) 0.303 7.878 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/O
|
|
net (fo=1, routed) 0.264 8.142 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_11
|
|
SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/I5
|
|
SLICE_X107Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.266 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/O
|
|
net (fo=1, routed) 0.991 9.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0_n_0
|
|
SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/I0
|
|
SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/O
|
|
net (fo=1, routed) 0.632 10.013 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[9]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[9])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.013
|
|
-------------------------------------------------------------------
|
|
slack 0.155
|
|
|
|
Slack (MET) : 0.155ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.532ns (logic 3.449ns (27.521%) route 9.083ns (72.479%))
|
|
Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3]
|
|
net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0
|
|
SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI
|
|
SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 7.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[1]
|
|
net (fo=2, routed) 0.351 7.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[9]
|
|
SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/I1
|
|
SLICE_X107Y75 LUT6 (Prop_lut6_I1_O) 0.303 7.878 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/O
|
|
net (fo=1, routed) 0.264 8.142 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_11
|
|
SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/I5
|
|
SLICE_X107Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.266 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/O
|
|
net (fo=1, routed) 0.991 9.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0_n_0
|
|
SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/I0
|
|
SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/O
|
|
net (fo=1, routed) 0.632 10.013 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[9]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[9])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.013
|
|
-------------------------------------------------------------------
|
|
slack 0.155
|
|
|
|
Slack (MET) : 0.155ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.532ns (logic 3.449ns (27.521%) route 9.083ns (72.479%))
|
|
Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3]
|
|
net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0
|
|
SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI
|
|
SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 7.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[1]
|
|
net (fo=2, routed) 0.351 7.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[9]
|
|
SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/I1
|
|
SLICE_X107Y75 LUT6 (Prop_lut6_I1_O) 0.303 7.878 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/O
|
|
net (fo=1, routed) 0.264 8.142 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_11
|
|
SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/I5
|
|
SLICE_X107Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.266 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/O
|
|
net (fo=1, routed) 0.991 9.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0_n_0
|
|
SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/I0
|
|
SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/O
|
|
net (fo=1, routed) 0.632 10.013 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[9]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[9])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.013
|
|
-------------------------------------------------------------------
|
|
slack 0.155
|
|
|
|
Slack (MET) : 0.155ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.532ns (logic 3.449ns (27.521%) route 9.083ns (72.479%))
|
|
Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3]
|
|
net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0
|
|
SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI
|
|
SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 7.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[1]
|
|
net (fo=2, routed) 0.351 7.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[9]
|
|
SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/I1
|
|
SLICE_X107Y75 LUT6 (Prop_lut6_I1_O) 0.303 7.878 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/O
|
|
net (fo=1, routed) 0.264 8.142 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_11
|
|
SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/I5
|
|
SLICE_X107Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.266 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/O
|
|
net (fo=1, routed) 0.991 9.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0_n_0
|
|
SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/I0
|
|
SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/O
|
|
net (fo=1, routed) 0.632 10.013 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[9]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[9])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.013
|
|
-------------------------------------------------------------------
|
|
slack 0.155
|
|
|
|
Slack (MET) : 0.155ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.532ns (logic 3.449ns (27.521%) route 9.083ns (72.479%))
|
|
Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3]
|
|
net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0
|
|
SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI
|
|
SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 7.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[1]
|
|
net (fo=2, routed) 0.351 7.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[9]
|
|
SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/I1
|
|
SLICE_X107Y75 LUT6 (Prop_lut6_I1_O) 0.303 7.878 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/O
|
|
net (fo=1, routed) 0.264 8.142 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_11
|
|
SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/I5
|
|
SLICE_X107Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.266 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/O
|
|
net (fo=1, routed) 0.991 9.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0_n_0
|
|
SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/I0
|
|
SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/O
|
|
net (fo=1, routed) 0.632 10.013 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[9]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[9])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.013
|
|
-------------------------------------------------------------------
|
|
slack 0.155
|
|
|
|
Slack (MET) : 0.155ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.532ns (logic 3.449ns (27.521%) route 9.083ns (72.479%))
|
|
Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 6.867 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3]
|
|
net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0
|
|
SLICE_X106Y75 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI
|
|
SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 7.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[1]
|
|
net (fo=2, routed) 0.351 7.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[9]
|
|
SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/I1
|
|
SLICE_X107Y75 LUT6 (Prop_lut6_I1_O) 0.303 7.878 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/O
|
|
net (fo=1, routed) 0.264 8.142 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_11
|
|
SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/I5
|
|
SLICE_X107Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.266 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/O
|
|
net (fo=1, routed) 0.991 9.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0_n_0
|
|
SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/I0
|
|
SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/O
|
|
net (fo=1, routed) 0.632 10.013 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[9]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[9])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.013
|
|
-------------------------------------------------------------------
|
|
slack 0.155
|
|
|
|
Slack (MET) : 0.155ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.532ns (logic 3.449ns (27.521%) route 9.083ns (72.479%))
|
|
Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 6.867 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3]
|
|
net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0
|
|
SLICE_X106Y75 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI
|
|
SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 7.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[1]
|
|
net (fo=2, routed) 0.351 7.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[9]
|
|
SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/I1
|
|
SLICE_X107Y75 LUT6 (Prop_lut6_I1_O) 0.303 7.878 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/O
|
|
net (fo=1, routed) 0.264 8.142 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_11
|
|
SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/I5
|
|
SLICE_X107Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.266 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/O
|
|
net (fo=1, routed) 0.991 9.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0_n_0
|
|
SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/I0
|
|
SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/O
|
|
net (fo=1, routed) 0.632 10.013 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[9]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[9])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.013
|
|
-------------------------------------------------------------------
|
|
slack 0.155
|
|
|
|
Slack (MET) : 0.157ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.530ns (logic 3.242ns (25.874%) route 9.288ns (74.126%))
|
|
Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.256 7.009 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[2]
|
|
net (fo=2, routed) 0.982 7.991 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[6]
|
|
SLICE_X129Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/I1
|
|
SLICE_X129Y75 LUT6 (Prop_lut6_I1_O) 0.302 8.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/O
|
|
net (fo=1, routed) 0.435 8.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_8
|
|
SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/I5
|
|
SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.852 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/O
|
|
net (fo=1, routed) 0.503 9.356 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0_n_0
|
|
SLICE_X138Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/I0
|
|
SLICE_X138Y73 LUT5 (Prop_lut5_I0_O) 0.124 9.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/O
|
|
net (fo=1, routed) 0.531 10.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[6]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[6])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.011
|
|
-------------------------------------------------------------------
|
|
slack 0.157
|
|
|
|
Slack (MET) : 0.157ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.530ns (logic 3.242ns (25.874%) route 9.288ns (74.126%))
|
|
Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.256 7.009 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[2]
|
|
net (fo=2, routed) 0.982 7.991 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[6]
|
|
SLICE_X129Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/I1
|
|
SLICE_X129Y75 LUT6 (Prop_lut6_I1_O) 0.302 8.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/O
|
|
net (fo=1, routed) 0.435 8.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_8
|
|
SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/I5
|
|
SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.852 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/O
|
|
net (fo=1, routed) 0.503 9.356 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0_n_0
|
|
SLICE_X138Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/I0
|
|
SLICE_X138Y73 LUT5 (Prop_lut5_I0_O) 0.124 9.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/O
|
|
net (fo=1, routed) 0.531 10.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[6]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[6])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.011
|
|
-------------------------------------------------------------------
|
|
slack 0.157
|
|
|
|
Slack (MET) : 0.157ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.530ns (logic 3.242ns (25.874%) route 9.288ns (74.126%))
|
|
Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.256 7.009 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[2]
|
|
net (fo=2, routed) 0.982 7.991 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[6]
|
|
SLICE_X129Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/I1
|
|
SLICE_X129Y75 LUT6 (Prop_lut6_I1_O) 0.302 8.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/O
|
|
net (fo=1, routed) 0.435 8.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_8
|
|
SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/I5
|
|
SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.852 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/O
|
|
net (fo=1, routed) 0.503 9.356 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0_n_0
|
|
SLICE_X138Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/I0
|
|
SLICE_X138Y73 LUT5 (Prop_lut5_I0_O) 0.124 9.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/O
|
|
net (fo=1, routed) 0.531 10.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[6]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[6])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.011
|
|
-------------------------------------------------------------------
|
|
slack 0.157
|
|
|
|
Slack (MET) : 0.157ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.530ns (logic 3.242ns (25.874%) route 9.288ns (74.126%))
|
|
Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.256 7.009 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[2]
|
|
net (fo=2, routed) 0.982 7.991 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[6]
|
|
SLICE_X129Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/I1
|
|
SLICE_X129Y75 LUT6 (Prop_lut6_I1_O) 0.302 8.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/O
|
|
net (fo=1, routed) 0.435 8.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_8
|
|
SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/I5
|
|
SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.852 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/O
|
|
net (fo=1, routed) 0.503 9.356 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0_n_0
|
|
SLICE_X138Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/I0
|
|
SLICE_X138Y73 LUT5 (Prop_lut5_I0_O) 0.124 9.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/O
|
|
net (fo=1, routed) 0.531 10.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[6]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[6])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.011
|
|
-------------------------------------------------------------------
|
|
slack 0.157
|
|
|
|
Slack (MET) : 0.157ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.530ns (logic 3.242ns (25.874%) route 9.288ns (74.126%))
|
|
Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.256 7.009 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[2]
|
|
net (fo=2, routed) 0.982 7.991 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[6]
|
|
SLICE_X129Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/I1
|
|
SLICE_X129Y75 LUT6 (Prop_lut6_I1_O) 0.302 8.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/O
|
|
net (fo=1, routed) 0.435 8.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_8
|
|
SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/I5
|
|
SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.852 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/O
|
|
net (fo=1, routed) 0.503 9.356 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0_n_0
|
|
SLICE_X138Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/I0
|
|
SLICE_X138Y73 LUT5 (Prop_lut5_I0_O) 0.124 9.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/O
|
|
net (fo=1, routed) 0.531 10.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[6]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[6])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.011
|
|
-------------------------------------------------------------------
|
|
slack 0.157
|
|
|
|
Slack (MET) : 0.157ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.530ns (logic 3.242ns (25.874%) route 9.288ns (74.126%))
|
|
Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.256 7.009 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[2]
|
|
net (fo=2, routed) 0.982 7.991 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[6]
|
|
SLICE_X129Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/I1
|
|
SLICE_X129Y75 LUT6 (Prop_lut6_I1_O) 0.302 8.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/O
|
|
net (fo=1, routed) 0.435 8.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_8
|
|
SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/I5
|
|
SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.852 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/O
|
|
net (fo=1, routed) 0.503 9.356 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0_n_0
|
|
SLICE_X138Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/I0
|
|
SLICE_X138Y73 LUT5 (Prop_lut5_I0_O) 0.124 9.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/O
|
|
net (fo=1, routed) 0.531 10.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[6]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[6])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.011
|
|
-------------------------------------------------------------------
|
|
slack 0.157
|
|
|
|
Slack (MET) : 0.157ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.530ns (logic 3.242ns (25.874%) route 9.288ns (74.126%))
|
|
Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.256 7.009 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[2]
|
|
net (fo=2, routed) 0.982 7.991 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[6]
|
|
SLICE_X129Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/I1
|
|
SLICE_X129Y75 LUT6 (Prop_lut6_I1_O) 0.302 8.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/O
|
|
net (fo=1, routed) 0.435 8.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_8
|
|
SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/I5
|
|
SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.852 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/O
|
|
net (fo=1, routed) 0.503 9.356 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0_n_0
|
|
SLICE_X138Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/I0
|
|
SLICE_X138Y73 LUT5 (Prop_lut5_I0_O) 0.124 9.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/O
|
|
net (fo=1, routed) 0.531 10.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[6]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[6])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.011
|
|
-------------------------------------------------------------------
|
|
slack 0.157
|
|
|
|
Slack (MET) : 0.157ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.530ns (logic 3.242ns (25.874%) route 9.288ns (74.126%))
|
|
Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.256 7.009 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[2]
|
|
net (fo=2, routed) 0.982 7.991 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[6]
|
|
SLICE_X129Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/I1
|
|
SLICE_X129Y75 LUT6 (Prop_lut6_I1_O) 0.302 8.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/O
|
|
net (fo=1, routed) 0.435 8.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_8
|
|
SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/I5
|
|
SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.852 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/O
|
|
net (fo=1, routed) 0.503 9.356 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0_n_0
|
|
SLICE_X138Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/I0
|
|
SLICE_X138Y73 LUT5 (Prop_lut5_I0_O) 0.124 9.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/O
|
|
net (fo=1, routed) 0.531 10.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[6]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[6])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.011
|
|
-------------------------------------------------------------------
|
|
slack 0.157
|
|
|
|
Slack (MET) : 0.157ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.530ns (logic 3.242ns (25.874%) route 9.288ns (74.126%))
|
|
Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.256 7.009 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[2]
|
|
net (fo=2, routed) 0.982 7.991 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[6]
|
|
SLICE_X129Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/I1
|
|
SLICE_X129Y75 LUT6 (Prop_lut6_I1_O) 0.302 8.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/O
|
|
net (fo=1, routed) 0.435 8.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_8
|
|
SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/I5
|
|
SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.852 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/O
|
|
net (fo=1, routed) 0.503 9.356 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0_n_0
|
|
SLICE_X138Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/I0
|
|
SLICE_X138Y73 LUT5 (Prop_lut5_I0_O) 0.124 9.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/O
|
|
net (fo=1, routed) 0.531 10.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[6]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[6])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.011
|
|
-------------------------------------------------------------------
|
|
slack 0.157
|
|
|
|
Slack (MET) : 0.157ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6]
|
|
(rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.530ns (logic 3.242ns (25.874%) route 9.288ns (74.126%))
|
|
Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1)
|
|
Clock Path Skew: 0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 )
|
|
Source Clock Delay (SCD): -2.520ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.756 -2.520
|
|
SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C
|
|
SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q
|
|
net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0
|
|
SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2
|
|
SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O
|
|
net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0
|
|
SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1
|
|
SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O
|
|
net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0
|
|
SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0
|
|
SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O
|
|
net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5
|
|
SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O
|
|
net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0
|
|
SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0
|
|
SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O
|
|
net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0
|
|
SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4
|
|
SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O
|
|
net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0
|
|
SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4
|
|
SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O
|
|
net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0
|
|
SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2
|
|
SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O
|
|
net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0
|
|
SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0]
|
|
SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3]
|
|
net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0
|
|
SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI
|
|
SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.256 7.009 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[2]
|
|
net (fo=2, routed) 0.982 7.991 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[6]
|
|
SLICE_X129Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/I1
|
|
SLICE_X129Y75 LUT6 (Prop_lut6_I1_O) 0.302 8.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/O
|
|
net (fo=1, routed) 0.435 8.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_8
|
|
SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/I5
|
|
SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.852 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/O
|
|
net (fo=1, routed) 0.503 9.356 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0_n_0
|
|
SLICE_X138Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/I0
|
|
SLICE_X138Y73 LUT5 (Prop_lut5_I0_O) 0.124 9.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/O
|
|
net (fo=1, routed) 0.531 10.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[6]
|
|
RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.675 11.000
|
|
clock pessimism -0.498 10.502
|
|
clock uncertainty -0.093 10.409
|
|
RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[6])
|
|
-0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.168
|
|
arrival time -10.011
|
|
-------------------------------------------------------------------
|
|
slack 0.157
|
|
|
|
Slack (MET) : 0.159ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 13.071ns (logic 0.770ns (5.891%) route 12.301ns (94.109%))
|
|
Logic Levels: 1 (MUXF7=1)
|
|
Clock Path Skew: 0.210ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 )
|
|
Source Clock Delay (SCD): -2.480ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.796 -2.480
|
|
SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
|
|
SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q
|
|
net (fo=1088, routed) 12.301 10.277 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2
|
|
SLICE_X162Y34 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[943]_i_2/S
|
|
SLICE_X162Y34 MUXF7 (Prop_muxf7_S_O) 0.314 10.591 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[943]_i_2/O
|
|
net (fo=1, routed) 0.000 10.591 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[943]
|
|
SLICE_X162Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.903 11.228
|
|
clock pessimism -0.498 10.730
|
|
clock uncertainty -0.093 10.637
|
|
SLICE_X162Y34 FDCE (Setup_fdce_C_D) 0.113 10.750 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]
|
|
-------------------------------------------------------------------
|
|
required time 10.750
|
|
arrival time -10.591
|
|
-------------------------------------------------------------------
|
|
slack 0.159
|
|
|
|
Slack (MET) : 0.159ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 13.071ns (logic 0.770ns (5.891%) route 12.301ns (94.109%))
|
|
Logic Levels: 1 (MUXF7=1)
|
|
Clock Path Skew: 0.210ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 )
|
|
Source Clock Delay (SCD): -2.480ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.796 -2.480
|
|
SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
|
|
SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q
|
|
net (fo=1088, routed) 12.301 10.277 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2
|
|
SLICE_X162Y34 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[943]_i_2/S
|
|
SLICE_X162Y34 MUXF7 (Prop_muxf7_S_O) 0.314 10.591 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[943]_i_2/O
|
|
net (fo=1, routed) 0.000 10.591 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[943]
|
|
SLICE_X162Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.903 11.228
|
|
clock pessimism -0.498 10.730
|
|
clock uncertainty -0.093 10.637
|
|
SLICE_X162Y34 FDCE (Setup_fdce_C_D) 0.113 10.750 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]
|
|
-------------------------------------------------------------------
|
|
required time 10.750
|
|
arrival time -10.591
|
|
-------------------------------------------------------------------
|
|
slack 0.159
|
|
|
|
Slack (MET) : 0.159ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 13.071ns (logic 0.770ns (5.891%) route 12.301ns (94.109%))
|
|
Logic Levels: 1 (MUXF7=1)
|
|
Clock Path Skew: 0.210ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 )
|
|
Source Clock Delay (SCD): -2.480ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.796 -2.480
|
|
SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
|
|
SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q
|
|
net (fo=1088, routed) 12.301 10.277 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2
|
|
SLICE_X162Y34 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[943]_i_2/S
|
|
SLICE_X162Y34 MUXF7 (Prop_muxf7_S_O) 0.314 10.591 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[943]_i_2/O
|
|
net (fo=1, routed) 0.000 10.591 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[943]
|
|
SLICE_X162Y34 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.903 11.228
|
|
clock pessimism -0.498 10.730
|
|
clock uncertainty -0.093 10.637
|
|
SLICE_X162Y34 FDCE (Setup_fdce_C_D) 0.113 10.750 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]
|
|
-------------------------------------------------------------------
|
|
required time 10.750
|
|
arrival time -10.591
|
|
-------------------------------------------------------------------
|
|
slack 0.159
|
|
|
|
Slack (MET) : 0.159ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 13.071ns (logic 0.770ns (5.891%) route 12.301ns (94.109%))
|
|
Logic Levels: 1 (MUXF7=1)
|
|
Clock Path Skew: 0.210ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 )
|
|
Source Clock Delay (SCD): -2.480ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.796 -2.480
|
|
SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
|
|
SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q
|
|
net (fo=1088, routed) 12.301 10.277 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2
|
|
SLICE_X162Y34 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[943]_i_2/S
|
|
SLICE_X162Y34 MUXF7 (Prop_muxf7_S_O) 0.314 10.591 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[943]_i_2/O
|
|
net (fo=1, routed) 0.000 10.591 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[943]
|
|
SLICE_X162Y34 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.903 11.228
|
|
clock pessimism -0.498 10.730
|
|
clock uncertainty -0.093 10.637
|
|
SLICE_X162Y34 FDCE (Setup_fdce_C_D) 0.113 10.750 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]
|
|
-------------------------------------------------------------------
|
|
required time 10.750
|
|
arrival time -10.591
|
|
-------------------------------------------------------------------
|
|
slack 0.159
|
|
|
|
Slack (MET) : 0.175ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.935ns (logic 0.818ns (6.324%) route 12.117ns (93.676%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: 0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.842ns = ( 11.158 - 13.000 )
|
|
Source Clock Delay (SCD): -2.480ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.796 -2.480
|
|
SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 12.117 10.093 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X155Y43 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3/I2
|
|
SLICE_X155Y43 LUT4 (Prop_lut4_I2_O) 0.124 10.217 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3/O
|
|
net (fo=1, routed) 0.000 10.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3_n_0
|
|
SLICE_X155Y43 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[975]_i_2/I0
|
|
SLICE_X155Y43 MUXF7 (Prop_muxf7_I0_O) 0.238 10.455 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[975]_i_2/O
|
|
net (fo=1, routed) 0.000 10.455 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[975]
|
|
SLICE_X155Y43 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.833 11.158
|
|
clock pessimism -0.498 10.660
|
|
clock uncertainty -0.093 10.567
|
|
SLICE_X155Y43 FDCE (Setup_fdce_C_D) 0.064 10.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]
|
|
-------------------------------------------------------------------
|
|
required time 10.631
|
|
arrival time -10.455
|
|
-------------------------------------------------------------------
|
|
slack 0.175
|
|
|
|
Slack (MET) : 0.175ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.935ns (logic 0.818ns (6.324%) route 12.117ns (93.676%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: 0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.842ns = ( 11.158 - 13.000 )
|
|
Source Clock Delay (SCD): -2.480ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.796 -2.480
|
|
SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 12.117 10.093 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X155Y43 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3/I2
|
|
SLICE_X155Y43 LUT4 (Prop_lut4_I2_O) 0.124 10.217 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3/O
|
|
net (fo=1, routed) 0.000 10.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3_n_0
|
|
SLICE_X155Y43 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[975]_i_2/I0
|
|
SLICE_X155Y43 MUXF7 (Prop_muxf7_I0_O) 0.238 10.455 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[975]_i_2/O
|
|
net (fo=1, routed) 0.000 10.455 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[975]
|
|
SLICE_X155Y43 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.833 11.158
|
|
clock pessimism -0.498 10.660
|
|
clock uncertainty -0.093 10.567
|
|
SLICE_X155Y43 FDCE (Setup_fdce_C_D) 0.064 10.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]
|
|
-------------------------------------------------------------------
|
|
required time 10.631
|
|
arrival time -10.455
|
|
-------------------------------------------------------------------
|
|
slack 0.175
|
|
|
|
Slack (MET) : 0.175ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.935ns (logic 0.818ns (6.324%) route 12.117ns (93.676%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: 0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.842ns = ( 11.158 - 13.000 )
|
|
Source Clock Delay (SCD): -2.480ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.796 -2.480
|
|
SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 12.117 10.093 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X155Y43 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3/I2
|
|
SLICE_X155Y43 LUT4 (Prop_lut4_I2_O) 0.124 10.217 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3/O
|
|
net (fo=1, routed) 0.000 10.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3_n_0
|
|
SLICE_X155Y43 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[975]_i_2/I0
|
|
SLICE_X155Y43 MUXF7 (Prop_muxf7_I0_O) 0.238 10.455 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[975]_i_2/O
|
|
net (fo=1, routed) 0.000 10.455 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[975]
|
|
SLICE_X155Y43 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.833 11.158
|
|
clock pessimism -0.498 10.660
|
|
clock uncertainty -0.093 10.567
|
|
SLICE_X155Y43 FDCE (Setup_fdce_C_D) 0.064 10.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]
|
|
-------------------------------------------------------------------
|
|
required time 10.631
|
|
arrival time -10.455
|
|
-------------------------------------------------------------------
|
|
slack 0.175
|
|
|
|
Slack (MET) : 0.175ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.935ns (logic 0.818ns (6.324%) route 12.117ns (93.676%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: 0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.842ns = ( 11.158 - 13.000 )
|
|
Source Clock Delay (SCD): -2.480ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.796 -2.480
|
|
SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 12.117 10.093 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X155Y43 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3/I2
|
|
SLICE_X155Y43 LUT4 (Prop_lut4_I2_O) 0.124 10.217 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3/O
|
|
net (fo=1, routed) 0.000 10.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3_n_0
|
|
SLICE_X155Y43 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[975]_i_2/I0
|
|
SLICE_X155Y43 MUXF7 (Prop_muxf7_I0_O) 0.238 10.455 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[975]_i_2/O
|
|
net (fo=1, routed) 0.000 10.455 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[975]
|
|
SLICE_X155Y43 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.833 11.158
|
|
clock pessimism -0.498 10.660
|
|
clock uncertainty -0.093 10.567
|
|
SLICE_X155Y43 FDCE (Setup_fdce_C_D) 0.064 10.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]
|
|
-------------------------------------------------------------------
|
|
required time 10.631
|
|
arrival time -10.455
|
|
-------------------------------------------------------------------
|
|
slack 0.175
|
|
|
|
Slack (MET) : 0.181ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 13.053ns (logic 0.789ns (6.045%) route 12.264ns (93.955%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: 0.214ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.768ns = ( 11.232 - 13.000 )
|
|
Source Clock Delay (SCD): -2.480ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.796 -2.480
|
|
SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 12.264 10.240 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X162Y40 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2/I2
|
|
SLICE_X162Y40 LUT4 (Prop_lut4_I2_O) 0.124 10.364 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2/O
|
|
net (fo=1, routed) 0.000 10.364 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2_n_0
|
|
SLICE_X162Y40 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[888]_i_1/I0
|
|
SLICE_X162Y40 MUXF7 (Prop_muxf7_I0_O) 0.209 10.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[888]_i_1/O
|
|
net (fo=1, routed) 0.000 10.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[888]
|
|
SLICE_X162Y40 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.907 11.232
|
|
clock pessimism -0.498 10.734
|
|
clock uncertainty -0.093 10.641
|
|
SLICE_X162Y40 FDCE (Setup_fdce_C_D) 0.113 10.754 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]
|
|
-------------------------------------------------------------------
|
|
required time 10.754
|
|
arrival time -10.573
|
|
-------------------------------------------------------------------
|
|
slack 0.181
|
|
|
|
Slack (MET) : 0.181ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 13.053ns (logic 0.789ns (6.045%) route 12.264ns (93.955%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: 0.214ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.768ns = ( 11.232 - 13.000 )
|
|
Source Clock Delay (SCD): -2.480ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.796 -2.480
|
|
SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 12.264 10.240 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X162Y40 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2/I2
|
|
SLICE_X162Y40 LUT4 (Prop_lut4_I2_O) 0.124 10.364 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2/O
|
|
net (fo=1, routed) 0.000 10.364 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2_n_0
|
|
SLICE_X162Y40 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[888]_i_1/I0
|
|
SLICE_X162Y40 MUXF7 (Prop_muxf7_I0_O) 0.209 10.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[888]_i_1/O
|
|
net (fo=1, routed) 0.000 10.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[888]
|
|
SLICE_X162Y40 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.907 11.232
|
|
clock pessimism -0.498 10.734
|
|
clock uncertainty -0.093 10.641
|
|
SLICE_X162Y40 FDCE (Setup_fdce_C_D) 0.113 10.754 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]
|
|
-------------------------------------------------------------------
|
|
required time 10.754
|
|
arrival time -10.573
|
|
-------------------------------------------------------------------
|
|
slack 0.181
|
|
|
|
Slack (MET) : 0.181ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 13.053ns (logic 0.789ns (6.045%) route 12.264ns (93.955%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: 0.214ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.768ns = ( 11.232 - 13.000 )
|
|
Source Clock Delay (SCD): -2.480ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.796 -2.480
|
|
SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 12.264 10.240 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X162Y40 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2/I2
|
|
SLICE_X162Y40 LUT4 (Prop_lut4_I2_O) 0.124 10.364 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2/O
|
|
net (fo=1, routed) 0.000 10.364 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2_n_0
|
|
SLICE_X162Y40 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[888]_i_1/I0
|
|
SLICE_X162Y40 MUXF7 (Prop_muxf7_I0_O) 0.209 10.573 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[888]_i_1/O
|
|
net (fo=1, routed) 0.000 10.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[888]
|
|
SLICE_X162Y40 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.907 11.232
|
|
clock pessimism -0.498 10.734
|
|
clock uncertainty -0.093 10.641
|
|
SLICE_X162Y40 FDCE (Setup_fdce_C_D) 0.113 10.754 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]
|
|
-------------------------------------------------------------------
|
|
required time 10.754
|
|
arrival time -10.573
|
|
-------------------------------------------------------------------
|
|
slack 0.181
|
|
|
|
Slack (MET) : 0.181ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 13.053ns (logic 0.789ns (6.045%) route 12.264ns (93.955%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: 0.214ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.768ns = ( 11.232 - 13.000 )
|
|
Source Clock Delay (SCD): -2.480ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.796 -2.480
|
|
SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 12.264 10.240 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X162Y40 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2/I2
|
|
SLICE_X162Y40 LUT4 (Prop_lut4_I2_O) 0.124 10.364 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2/O
|
|
net (fo=1, routed) 0.000 10.364 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2_n_0
|
|
SLICE_X162Y40 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[888]_i_1/I0
|
|
SLICE_X162Y40 MUXF7 (Prop_muxf7_I0_O) 0.209 10.573 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[888]_i_1/O
|
|
net (fo=1, routed) 0.000 10.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[888]
|
|
SLICE_X162Y40 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.907 11.232
|
|
clock pessimism -0.498 10.734
|
|
clock uncertainty -0.093 10.641
|
|
SLICE_X162Y40 FDCE (Setup_fdce_C_D) 0.113 10.754 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]
|
|
-------------------------------------------------------------------
|
|
required time 10.754
|
|
arrival time -10.573
|
|
-------------------------------------------------------------------
|
|
slack 0.181
|
|
|
|
Slack (MET) : 0.181ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.552ns (logic 3.951ns (31.478%) route 8.601ns (68.522%))
|
|
Logic Levels: 16 (CARRY4=3 LUT2=1 LUT3=1 LUT5=2 LUT6=5 MUXF7=2 MUXF8=2)
|
|
Clock Path Skew: 0.066ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 )
|
|
Source Clock Delay (SCD): -2.481ns
|
|
Clock Pessimism Removal (CPR): -0.426ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.795 -2.481
|
|
SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q
|
|
net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0]
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4
|
|
SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O
|
|
net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1
|
|
SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O
|
|
net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1
|
|
SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O
|
|
net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5
|
|
SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O
|
|
net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0
|
|
SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O
|
|
net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1
|
|
SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O
|
|
net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0
|
|
SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1
|
|
SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O
|
|
net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0
|
|
SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0]
|
|
SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3]
|
|
net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0
|
|
SLICE_X134Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI
|
|
SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3]
|
|
net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0]
|
|
SLICE_X134Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI
|
|
SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0])
|
|
0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0]
|
|
net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0]
|
|
SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4
|
|
SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O
|
|
net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0
|
|
SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3
|
|
SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O
|
|
net (fo=29, routed) 0.719 6.587 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11
|
|
SLICE_X139Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/I1
|
|
SLICE_X139Y86 LUT3 (Prop_lut3_I1_O) 0.120 6.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/O
|
|
net (fo=3, routed) 0.689 7.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_166_n_0
|
|
SLICE_X141Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/I0
|
|
SLICE_X141Y84 LUT6 (Prop_lut6_I0_O) 0.327 7.723 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/O
|
|
net (fo=2, routed) 0.726 8.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_18
|
|
SLICE_X141Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/I2
|
|
SLICE_X141Y87 LUT6 (Prop_lut6_I2_O) 0.124 8.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/O
|
|
net (fo=12, routed) 1.061 9.634 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78_n_0
|
|
SLICE_X140Y88 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/I3
|
|
SLICE_X140Y88 LUT6 (Prop_lut6_I3_O) 0.124 9.758 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/O
|
|
net (fo=1, routed) 0.313 10.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7]
|
|
RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.687 11.012
|
|
clock pessimism -0.426 10.586
|
|
clock uncertainty -0.093 10.493
|
|
RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7])
|
|
-0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.252
|
|
arrival time -10.071
|
|
-------------------------------------------------------------------
|
|
slack 0.181
|
|
|
|
Slack (MET) : 0.181ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.552ns (logic 3.951ns (31.478%) route 8.601ns (68.522%))
|
|
Logic Levels: 16 (CARRY4=3 LUT2=1 LUT3=1 LUT5=2 LUT6=5 MUXF7=2 MUXF8=2)
|
|
Clock Path Skew: 0.066ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 )
|
|
Source Clock Delay (SCD): -2.481ns
|
|
Clock Pessimism Removal (CPR): -0.426ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.795 -2.481
|
|
SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q
|
|
net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0]
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4
|
|
SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O
|
|
net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1
|
|
SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O
|
|
net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1
|
|
SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O
|
|
net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5
|
|
SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O
|
|
net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0
|
|
SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O
|
|
net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1
|
|
SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O
|
|
net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0
|
|
SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1
|
|
SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O
|
|
net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0
|
|
SLICE_X134Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0]
|
|
SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3]
|
|
net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0
|
|
SLICE_X134Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI
|
|
SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3]
|
|
net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0]
|
|
SLICE_X134Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI
|
|
SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0])
|
|
0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0]
|
|
net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0]
|
|
SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4
|
|
SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O
|
|
net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0
|
|
SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3
|
|
SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O
|
|
net (fo=29, routed) 0.719 6.587 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11
|
|
SLICE_X139Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/I1
|
|
SLICE_X139Y86 LUT3 (Prop_lut3_I1_O) 0.120 6.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/O
|
|
net (fo=3, routed) 0.689 7.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_166_n_0
|
|
SLICE_X141Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/I0
|
|
SLICE_X141Y84 LUT6 (Prop_lut6_I0_O) 0.327 7.723 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/O
|
|
net (fo=2, routed) 0.726 8.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_18
|
|
SLICE_X141Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/I2
|
|
SLICE_X141Y87 LUT6 (Prop_lut6_I2_O) 0.124 8.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/O
|
|
net (fo=12, routed) 1.061 9.634 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78_n_0
|
|
SLICE_X140Y88 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/I3
|
|
SLICE_X140Y88 LUT6 (Prop_lut6_I3_O) 0.124 9.758 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/O
|
|
net (fo=1, routed) 0.313 10.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7]
|
|
RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.687 11.012
|
|
clock pessimism -0.426 10.586
|
|
clock uncertainty -0.093 10.493
|
|
RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7])
|
|
-0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.252
|
|
arrival time -10.071
|
|
-------------------------------------------------------------------
|
|
slack 0.181
|
|
|
|
Slack (MET) : 0.181ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.552ns (logic 3.951ns (31.478%) route 8.601ns (68.522%))
|
|
Logic Levels: 16 (CARRY4=3 LUT2=1 LUT3=1 LUT5=2 LUT6=5 MUXF7=2 MUXF8=2)
|
|
Clock Path Skew: 0.066ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 )
|
|
Source Clock Delay (SCD): -2.481ns
|
|
Clock Pessimism Removal (CPR): -0.426ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.795 -2.481
|
|
SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q
|
|
net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0]
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4
|
|
SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O
|
|
net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1
|
|
SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O
|
|
net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1
|
|
SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O
|
|
net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5
|
|
SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O
|
|
net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0
|
|
SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O
|
|
net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1
|
|
SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O
|
|
net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0
|
|
SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1
|
|
SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O
|
|
net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0
|
|
SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0]
|
|
SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 3.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3]
|
|
net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0
|
|
SLICE_X134Y86 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI
|
|
SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3]
|
|
net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0]
|
|
SLICE_X134Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI
|
|
SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0])
|
|
0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0]
|
|
net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0]
|
|
SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4
|
|
SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O
|
|
net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0
|
|
SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3
|
|
SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O
|
|
net (fo=29, routed) 0.719 6.587 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11
|
|
SLICE_X139Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/I1
|
|
SLICE_X139Y86 LUT3 (Prop_lut3_I1_O) 0.120 6.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/O
|
|
net (fo=3, routed) 0.689 7.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_166_n_0
|
|
SLICE_X141Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/I0
|
|
SLICE_X141Y84 LUT6 (Prop_lut6_I0_O) 0.327 7.723 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/O
|
|
net (fo=2, routed) 0.726 8.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_18
|
|
SLICE_X141Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/I2
|
|
SLICE_X141Y87 LUT6 (Prop_lut6_I2_O) 0.124 8.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/O
|
|
net (fo=12, routed) 1.061 9.634 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78_n_0
|
|
SLICE_X140Y88 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/I3
|
|
SLICE_X140Y88 LUT6 (Prop_lut6_I3_O) 0.124 9.758 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/O
|
|
net (fo=1, routed) 0.313 10.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7]
|
|
RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.687 11.012
|
|
clock pessimism -0.426 10.586
|
|
clock uncertainty -0.093 10.493
|
|
RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7])
|
|
-0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.252
|
|
arrival time -10.071
|
|
-------------------------------------------------------------------
|
|
slack 0.181
|
|
|
|
Slack (MET) : 0.181ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.552ns (logic 3.951ns (31.478%) route 8.601ns (68.522%))
|
|
Logic Levels: 16 (CARRY4=3 LUT2=1 LUT3=1 LUT5=2 LUT6=5 MUXF7=2 MUXF8=2)
|
|
Clock Path Skew: 0.066ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 )
|
|
Source Clock Delay (SCD): -2.481ns
|
|
Clock Pessimism Removal (CPR): -0.426ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.795 -2.481
|
|
SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q
|
|
net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0]
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4
|
|
SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O
|
|
net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1
|
|
SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O
|
|
net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1
|
|
SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O
|
|
net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5
|
|
SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O
|
|
net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0
|
|
SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O
|
|
net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1
|
|
SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O
|
|
net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0
|
|
SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1
|
|
SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O
|
|
net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0
|
|
SLICE_X134Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0]
|
|
SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 3.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3]
|
|
net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0
|
|
SLICE_X134Y86 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI
|
|
SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3]
|
|
net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0]
|
|
SLICE_X134Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI
|
|
SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0])
|
|
0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0]
|
|
net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0]
|
|
SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4
|
|
SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O
|
|
net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0
|
|
SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3
|
|
SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O
|
|
net (fo=29, routed) 0.719 6.587 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11
|
|
SLICE_X139Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/I1
|
|
SLICE_X139Y86 LUT3 (Prop_lut3_I1_O) 0.120 6.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/O
|
|
net (fo=3, routed) 0.689 7.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_166_n_0
|
|
SLICE_X141Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/I0
|
|
SLICE_X141Y84 LUT6 (Prop_lut6_I0_O) 0.327 7.723 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/O
|
|
net (fo=2, routed) 0.726 8.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_18
|
|
SLICE_X141Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/I2
|
|
SLICE_X141Y87 LUT6 (Prop_lut6_I2_O) 0.124 8.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/O
|
|
net (fo=12, routed) 1.061 9.634 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78_n_0
|
|
SLICE_X140Y88 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/I3
|
|
SLICE_X140Y88 LUT6 (Prop_lut6_I3_O) 0.124 9.758 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/O
|
|
net (fo=1, routed) 0.313 10.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7]
|
|
RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.687 11.012
|
|
clock pessimism -0.426 10.586
|
|
clock uncertainty -0.093 10.493
|
|
RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7])
|
|
-0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.252
|
|
arrival time -10.071
|
|
-------------------------------------------------------------------
|
|
slack 0.181
|
|
|
|
Slack (MET) : 0.181ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.552ns (logic 3.951ns (31.478%) route 8.601ns (68.522%))
|
|
Logic Levels: 16 (CARRY4=3 LUT2=1 LUT3=1 LUT5=2 LUT6=5 MUXF7=2 MUXF8=2)
|
|
Clock Path Skew: 0.066ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 )
|
|
Source Clock Delay (SCD): -2.481ns
|
|
Clock Pessimism Removal (CPR): -0.426ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.795 -2.481
|
|
SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q
|
|
net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0]
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4
|
|
SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O
|
|
net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1
|
|
SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O
|
|
net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1
|
|
SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O
|
|
net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5
|
|
SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O
|
|
net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0
|
|
SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O
|
|
net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1
|
|
SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O
|
|
net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0
|
|
SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1
|
|
SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O
|
|
net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0
|
|
SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0]
|
|
SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3]
|
|
net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0
|
|
SLICE_X134Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI
|
|
SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 3.327 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3]
|
|
net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0]
|
|
SLICE_X134Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI
|
|
SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0])
|
|
0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0]
|
|
net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0]
|
|
SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4
|
|
SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O
|
|
net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0
|
|
SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3
|
|
SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O
|
|
net (fo=29, routed) 0.719 6.587 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11
|
|
SLICE_X139Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/I1
|
|
SLICE_X139Y86 LUT3 (Prop_lut3_I1_O) 0.120 6.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/O
|
|
net (fo=3, routed) 0.689 7.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_166_n_0
|
|
SLICE_X141Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/I0
|
|
SLICE_X141Y84 LUT6 (Prop_lut6_I0_O) 0.327 7.723 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/O
|
|
net (fo=2, routed) 0.726 8.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_18
|
|
SLICE_X141Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/I2
|
|
SLICE_X141Y87 LUT6 (Prop_lut6_I2_O) 0.124 8.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/O
|
|
net (fo=12, routed) 1.061 9.634 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78_n_0
|
|
SLICE_X140Y88 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/I3
|
|
SLICE_X140Y88 LUT6 (Prop_lut6_I3_O) 0.124 9.758 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/O
|
|
net (fo=1, routed) 0.313 10.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7]
|
|
RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.687 11.012
|
|
clock pessimism -0.426 10.586
|
|
clock uncertainty -0.093 10.493
|
|
RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7])
|
|
-0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.252
|
|
arrival time -10.071
|
|
-------------------------------------------------------------------
|
|
slack 0.181
|
|
|
|
Slack (MET) : 0.181ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.552ns (logic 3.951ns (31.478%) route 8.601ns (68.522%))
|
|
Logic Levels: 16 (CARRY4=3 LUT2=1 LUT3=1 LUT5=2 LUT6=5 MUXF7=2 MUXF8=2)
|
|
Clock Path Skew: 0.066ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 )
|
|
Source Clock Delay (SCD): -2.481ns
|
|
Clock Pessimism Removal (CPR): -0.426ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.795 -2.481
|
|
SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q
|
|
net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0]
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4
|
|
SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O
|
|
net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0
|
|
SLICE_X119Y93 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1
|
|
SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O
|
|
net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0
|
|
SLICE_X119Y93 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1
|
|
SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O
|
|
net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0
|
|
SLICE_X121Y90 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5
|
|
SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O
|
|
net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0
|
|
SLICE_X121Y90 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0
|
|
SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O
|
|
net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0
|
|
SLICE_X121Y90 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1
|
|
SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O
|
|
net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0
|
|
SLICE_X134Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1
|
|
SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O
|
|
net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0
|
|
SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0]
|
|
SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3]
|
|
net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0
|
|
SLICE_X134Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI
|
|
SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 3.327 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3]
|
|
net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0]
|
|
SLICE_X134Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI
|
|
SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0])
|
|
0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0]
|
|
net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0]
|
|
SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4
|
|
SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O
|
|
net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0
|
|
SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3
|
|
SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O
|
|
net (fo=29, routed) 0.719 6.587 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11
|
|
SLICE_X139Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/I1
|
|
SLICE_X139Y86 LUT3 (Prop_lut3_I1_O) 0.120 6.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/O
|
|
net (fo=3, routed) 0.689 7.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_166_n_0
|
|
SLICE_X141Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/I0
|
|
SLICE_X141Y84 LUT6 (Prop_lut6_I0_O) 0.327 7.723 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/O
|
|
net (fo=2, routed) 0.726 8.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_18
|
|
SLICE_X141Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/I2
|
|
SLICE_X141Y87 LUT6 (Prop_lut6_I2_O) 0.124 8.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/O
|
|
net (fo=12, routed) 1.061 9.634 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78_n_0
|
|
SLICE_X140Y88 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/I3
|
|
SLICE_X140Y88 LUT6 (Prop_lut6_I3_O) 0.124 9.758 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/O
|
|
net (fo=1, routed) 0.313 10.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7]
|
|
RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.687 11.012
|
|
clock pessimism -0.426 10.586
|
|
clock uncertainty -0.093 10.493
|
|
RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7])
|
|
-0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.252
|
|
arrival time -10.071
|
|
-------------------------------------------------------------------
|
|
slack 0.181
|
|
|
|
Slack (MET) : 0.181ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.552ns (logic 3.951ns (31.478%) route 8.601ns (68.522%))
|
|
Logic Levels: 16 (CARRY4=3 LUT2=1 LUT3=1 LUT5=2 LUT6=5 MUXF7=2 MUXF8=2)
|
|
Clock Path Skew: 0.066ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 )
|
|
Source Clock Delay (SCD): -2.481ns
|
|
Clock Pessimism Removal (CPR): -0.426ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.795 -2.481
|
|
SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q
|
|
net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0]
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4
|
|
SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O
|
|
net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1
|
|
SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O
|
|
net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1
|
|
SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O
|
|
net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5
|
|
SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O
|
|
net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0
|
|
SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O
|
|
net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1
|
|
SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O
|
|
net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0
|
|
SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1
|
|
SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O
|
|
net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0
|
|
SLICE_X134Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0]
|
|
SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3]
|
|
net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0
|
|
SLICE_X134Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI
|
|
SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 3.327 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3]
|
|
net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0]
|
|
SLICE_X134Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI
|
|
SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0])
|
|
0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0]
|
|
net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0]
|
|
SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4
|
|
SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O
|
|
net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0
|
|
SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3
|
|
SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O
|
|
net (fo=29, routed) 0.719 6.587 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11
|
|
SLICE_X139Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/I1
|
|
SLICE_X139Y86 LUT3 (Prop_lut3_I1_O) 0.120 6.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/O
|
|
net (fo=3, routed) 0.689 7.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_166_n_0
|
|
SLICE_X141Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/I0
|
|
SLICE_X141Y84 LUT6 (Prop_lut6_I0_O) 0.327 7.723 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/O
|
|
net (fo=2, routed) 0.726 8.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_18
|
|
SLICE_X141Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/I2
|
|
SLICE_X141Y87 LUT6 (Prop_lut6_I2_O) 0.124 8.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/O
|
|
net (fo=12, routed) 1.061 9.634 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78_n_0
|
|
SLICE_X140Y88 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/I3
|
|
SLICE_X140Y88 LUT6 (Prop_lut6_I3_O) 0.124 9.758 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/O
|
|
net (fo=1, routed) 0.313 10.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7]
|
|
RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.687 11.012
|
|
clock pessimism -0.426 10.586
|
|
clock uncertainty -0.093 10.493
|
|
RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7])
|
|
-0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.252
|
|
arrival time -10.071
|
|
-------------------------------------------------------------------
|
|
slack 0.181
|
|
|
|
Slack (MET) : 0.181ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.552ns (logic 3.951ns (31.478%) route 8.601ns (68.522%))
|
|
Logic Levels: 16 (CARRY4=3 LUT2=1 LUT3=1 LUT5=2 LUT6=5 MUXF7=2 MUXF8=2)
|
|
Clock Path Skew: 0.066ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 )
|
|
Source Clock Delay (SCD): -2.481ns
|
|
Clock Pessimism Removal (CPR): -0.426ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.795 -2.481
|
|
SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q
|
|
net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0]
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4
|
|
SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O
|
|
net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0
|
|
SLICE_X119Y93 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1
|
|
SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O
|
|
net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0
|
|
SLICE_X119Y93 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1
|
|
SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O
|
|
net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0
|
|
SLICE_X121Y90 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5
|
|
SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O
|
|
net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0
|
|
SLICE_X121Y90 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0
|
|
SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O
|
|
net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0
|
|
SLICE_X121Y90 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1
|
|
SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O
|
|
net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0
|
|
SLICE_X134Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1
|
|
SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O
|
|
net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0
|
|
SLICE_X134Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0]
|
|
SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3]
|
|
net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0
|
|
SLICE_X134Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI
|
|
SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 3.327 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3]
|
|
net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0]
|
|
SLICE_X134Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI
|
|
SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0])
|
|
0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0]
|
|
net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0]
|
|
SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4
|
|
SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O
|
|
net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0
|
|
SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3
|
|
SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O
|
|
net (fo=29, routed) 0.719 6.587 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11
|
|
SLICE_X139Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/I1
|
|
SLICE_X139Y86 LUT3 (Prop_lut3_I1_O) 0.120 6.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/O
|
|
net (fo=3, routed) 0.689 7.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_166_n_0
|
|
SLICE_X141Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/I0
|
|
SLICE_X141Y84 LUT6 (Prop_lut6_I0_O) 0.327 7.723 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/O
|
|
net (fo=2, routed) 0.726 8.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_18
|
|
SLICE_X141Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/I2
|
|
SLICE_X141Y87 LUT6 (Prop_lut6_I2_O) 0.124 8.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/O
|
|
net (fo=12, routed) 1.061 9.634 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78_n_0
|
|
SLICE_X140Y88 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/I3
|
|
SLICE_X140Y88 LUT6 (Prop_lut6_I3_O) 0.124 9.758 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/O
|
|
net (fo=1, routed) 0.313 10.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7]
|
|
RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.687 11.012
|
|
clock pessimism -0.426 10.586
|
|
clock uncertainty -0.093 10.493
|
|
RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7])
|
|
-0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.252
|
|
arrival time -10.071
|
|
-------------------------------------------------------------------
|
|
slack 0.181
|
|
|
|
Slack (MET) : 0.181ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.552ns (logic 3.951ns (31.478%) route 8.601ns (68.522%))
|
|
Logic Levels: 16 (CARRY4=3 LUT2=1 LUT3=1 LUT5=2 LUT6=5 MUXF7=2 MUXF8=2)
|
|
Clock Path Skew: 0.066ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 )
|
|
Source Clock Delay (SCD): -2.481ns
|
|
Clock Pessimism Removal (CPR): -0.426ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.795 -2.481
|
|
SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q
|
|
net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0]
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4
|
|
SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O
|
|
net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1
|
|
SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O
|
|
net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1
|
|
SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O
|
|
net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5
|
|
SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O
|
|
net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0
|
|
SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O
|
|
net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1
|
|
SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O
|
|
net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0
|
|
SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1
|
|
SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O
|
|
net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0
|
|
SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0]
|
|
SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 3.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3]
|
|
net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0
|
|
SLICE_X134Y86 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI
|
|
SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 3.327 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3]
|
|
net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0]
|
|
SLICE_X134Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI
|
|
SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0])
|
|
0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0]
|
|
net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0]
|
|
SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4
|
|
SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O
|
|
net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0
|
|
SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3
|
|
SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O
|
|
net (fo=29, routed) 0.719 6.587 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11
|
|
SLICE_X139Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/I1
|
|
SLICE_X139Y86 LUT3 (Prop_lut3_I1_O) 0.120 6.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/O
|
|
net (fo=3, routed) 0.689 7.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_166_n_0
|
|
SLICE_X141Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/I0
|
|
SLICE_X141Y84 LUT6 (Prop_lut6_I0_O) 0.327 7.723 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/O
|
|
net (fo=2, routed) 0.726 8.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_18
|
|
SLICE_X141Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/I2
|
|
SLICE_X141Y87 LUT6 (Prop_lut6_I2_O) 0.124 8.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/O
|
|
net (fo=12, routed) 1.061 9.634 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78_n_0
|
|
SLICE_X140Y88 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/I3
|
|
SLICE_X140Y88 LUT6 (Prop_lut6_I3_O) 0.124 9.758 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/O
|
|
net (fo=1, routed) 0.313 10.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7]
|
|
RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.687 11.012
|
|
clock pessimism -0.426 10.586
|
|
clock uncertainty -0.093 10.493
|
|
RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7])
|
|
-0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.252
|
|
arrival time -10.071
|
|
-------------------------------------------------------------------
|
|
slack 0.181
|
|
|
|
Slack (MET) : 0.181ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.552ns (logic 3.951ns (31.478%) route 8.601ns (68.522%))
|
|
Logic Levels: 16 (CARRY4=3 LUT2=1 LUT3=1 LUT5=2 LUT6=5 MUXF7=2 MUXF8=2)
|
|
Clock Path Skew: 0.066ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 )
|
|
Source Clock Delay (SCD): -2.481ns
|
|
Clock Pessimism Removal (CPR): -0.426ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.795 -2.481
|
|
SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C
|
|
SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q
|
|
net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0]
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4
|
|
SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O
|
|
net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1
|
|
SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O
|
|
net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0
|
|
SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1
|
|
SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O
|
|
net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5
|
|
SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O
|
|
net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0
|
|
SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O
|
|
net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0
|
|
SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1
|
|
SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O
|
|
net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0
|
|
SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1
|
|
SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O
|
|
net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0
|
|
SLICE_X134Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0]
|
|
SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 3.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3]
|
|
net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0
|
|
SLICE_X134Y86 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI
|
|
SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 3.327 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3]
|
|
net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0]
|
|
SLICE_X134Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI
|
|
SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0])
|
|
0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0]
|
|
net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0]
|
|
SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4
|
|
SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O
|
|
net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0
|
|
SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3
|
|
SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O
|
|
net (fo=29, routed) 0.719 6.587 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11
|
|
SLICE_X139Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/I1
|
|
SLICE_X139Y86 LUT3 (Prop_lut3_I1_O) 0.120 6.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/O
|
|
net (fo=3, routed) 0.689 7.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_166_n_0
|
|
SLICE_X141Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/I0
|
|
SLICE_X141Y84 LUT6 (Prop_lut6_I0_O) 0.327 7.723 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/O
|
|
net (fo=2, routed) 0.726 8.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_18
|
|
SLICE_X141Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/I2
|
|
SLICE_X141Y87 LUT6 (Prop_lut6_I2_O) 0.124 8.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/O
|
|
net (fo=12, routed) 1.061 9.634 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78_n_0
|
|
SLICE_X140Y88 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/I3
|
|
SLICE_X140Y88 LUT6 (Prop_lut6_I3_O) 0.124 9.758 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/O
|
|
net (fo=1, routed) 0.313 10.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7]
|
|
RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.687 11.012
|
|
clock pessimism -0.426 10.586
|
|
clock uncertainty -0.093 10.493
|
|
RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7])
|
|
-0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 10.252
|
|
arrival time -10.071
|
|
-------------------------------------------------------------------
|
|
slack 0.181
|
|
|
|
Slack (MET) : 0.185ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.995ns (logic 0.732ns (5.633%) route 12.263ns (94.367%))
|
|
Logic Levels: 1 (MUXF7=1)
|
|
Clock Path Skew: 0.209ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.773ns = ( 11.227 - 13.000 )
|
|
Source Clock Delay (SCD): -2.480ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.796 -2.480
|
|
SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
|
|
SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q
|
|
net (fo=1088, routed) 12.263 10.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2
|
|
SLICE_X160Y33 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[812]_i_1/S
|
|
SLICE_X160Y33 MUXF7 (Prop_muxf7_S_O) 0.276 10.515 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[812]_i_1/O
|
|
net (fo=1, routed) 0.000 10.515 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[812]
|
|
SLICE_X160Y33 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.902 11.227
|
|
clock pessimism -0.498 10.729
|
|
clock uncertainty -0.093 10.636
|
|
SLICE_X160Y33 FDCE (Setup_fdce_C_D) 0.064 10.700 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]
|
|
-------------------------------------------------------------------
|
|
required time 10.700
|
|
arrival time -10.515
|
|
-------------------------------------------------------------------
|
|
slack 0.185
|
|
|
|
Slack (MET) : 0.185ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.995ns (logic 0.732ns (5.633%) route 12.263ns (94.367%))
|
|
Logic Levels: 1 (MUXF7=1)
|
|
Clock Path Skew: 0.209ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.773ns = ( 11.227 - 13.000 )
|
|
Source Clock Delay (SCD): -2.480ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.796 -2.480
|
|
SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
|
|
SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q
|
|
net (fo=1088, routed) 12.263 10.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2
|
|
SLICE_X160Y33 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[812]_i_1/S
|
|
SLICE_X160Y33 MUXF7 (Prop_muxf7_S_O) 0.276 10.515 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[812]_i_1/O
|
|
net (fo=1, routed) 0.000 10.515 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[812]
|
|
SLICE_X160Y33 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.902 11.227
|
|
clock pessimism -0.498 10.729
|
|
clock uncertainty -0.093 10.636
|
|
SLICE_X160Y33 FDCE (Setup_fdce_C_D) 0.064 10.700 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]
|
|
-------------------------------------------------------------------
|
|
required time 10.700
|
|
arrival time -10.515
|
|
-------------------------------------------------------------------
|
|
slack 0.185
|
|
|
|
Slack (MET) : 0.185ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.995ns (logic 0.732ns (5.633%) route 12.263ns (94.367%))
|
|
Logic Levels: 1 (MUXF7=1)
|
|
Clock Path Skew: 0.209ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.773ns = ( 11.227 - 13.000 )
|
|
Source Clock Delay (SCD): -2.480ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.796 -2.480
|
|
SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
|
|
SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q
|
|
net (fo=1088, routed) 12.263 10.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2
|
|
SLICE_X160Y33 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[812]_i_1/S
|
|
SLICE_X160Y33 MUXF7 (Prop_muxf7_S_O) 0.276 10.515 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[812]_i_1/O
|
|
net (fo=1, routed) 0.000 10.515 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[812]
|
|
SLICE_X160Y33 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.902 11.227
|
|
clock pessimism -0.498 10.729
|
|
clock uncertainty -0.093 10.636
|
|
SLICE_X160Y33 FDCE (Setup_fdce_C_D) 0.064 10.700 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]
|
|
-------------------------------------------------------------------
|
|
required time 10.700
|
|
arrival time -10.515
|
|
-------------------------------------------------------------------
|
|
slack 0.185
|
|
|
|
Slack (MET) : 0.185ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.995ns (logic 0.732ns (5.633%) route 12.263ns (94.367%))
|
|
Logic Levels: 1 (MUXF7=1)
|
|
Clock Path Skew: 0.209ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.773ns = ( 11.227 - 13.000 )
|
|
Source Clock Delay (SCD): -2.480ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.796 -2.480
|
|
SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
|
|
SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q
|
|
net (fo=1088, routed) 12.263 10.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2
|
|
SLICE_X160Y33 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[812]_i_1/S
|
|
SLICE_X160Y33 MUXF7 (Prop_muxf7_S_O) 0.276 10.515 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[812]_i_1/O
|
|
net (fo=1, routed) 0.000 10.515 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[812]
|
|
SLICE_X160Y33 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.902 11.227
|
|
clock pessimism -0.498 10.729
|
|
clock uncertainty -0.093 10.636
|
|
SLICE_X160Y33 FDCE (Setup_fdce_C_D) 0.064 10.700 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]
|
|
-------------------------------------------------------------------
|
|
required time 10.700
|
|
arrival time -10.515
|
|
-------------------------------------------------------------------
|
|
slack 0.185
|
|
|
|
Slack (MET) : 0.188ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[946]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.992ns (logic 0.732ns (5.634%) route 12.260ns (94.366%))
|
|
Logic Levels: 1 (MUXF7=1)
|
|
Clock Path Skew: 0.210ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 )
|
|
Source Clock Delay (SCD): -2.480ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.796 -2.480
|
|
SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
|
|
SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q
|
|
net (fo=1088, routed) 12.260 10.237 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2
|
|
SLICE_X163Y34 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[946]_i_1/S
|
|
SLICE_X163Y34 MUXF7 (Prop_muxf7_S_O) 0.276 10.513 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[946]_i_1/O
|
|
net (fo=1, routed) 0.000 10.513 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[946]
|
|
SLICE_X163Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[946]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.903 11.228
|
|
clock pessimism -0.498 10.730
|
|
clock uncertainty -0.093 10.637
|
|
SLICE_X163Y34 FDCE (Setup_fdce_C_D) 0.064 10.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[946]
|
|
-------------------------------------------------------------------
|
|
required time 10.701
|
|
arrival time -10.513
|
|
-------------------------------------------------------------------
|
|
slack 0.188
|
|
|
|
Slack (MET) : 0.188ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[946]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: mlkem_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 12.992ns (logic 0.732ns (5.634%) route 12.260ns (94.366%))
|
|
Logic Levels: 1 (MUXF7=1)
|
|
Clock Path Skew: 0.210ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 )
|
|
Source Clock Delay (SCD): -2.480ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.796 -2.480
|
|
SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C
|
|
SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q
|
|
net (fo=1088, routed) 12.260 10.237 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2
|
|
SLICE_X163Y34 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[946]_i_1/S
|
|
SLICE_X163Y34 MUXF7 (Prop_muxf7_S_O) 0.276 10.513 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[946]_i_1/O
|
|
net (fo=1, routed) 0.000 10.513 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[946]
|
|
SLICE_X163Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[946]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.903 11.228
|
|
clock pessimism -0.498 10.730
|
|
clock uncertainty -0.093 10.637
|
|
SLICE_X163Y34 FDCE (Setup_fdce_C_D) 0.064 10.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[946]
|
|
-------------------------------------------------------------------
|
|
required time 10.701
|
|
arrival time -10.513
|
|
-------------------------------------------------------------------
|
|
slack 0.188
|
|
|
|
Slack (MET) : 0.253ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.397ns (logic 6.886ns (44.722%) route 8.511ns (55.278%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.846 9.523 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 13.069 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.069 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -13.069
|
|
-------------------------------------------------------------------
|
|
slack 0.253
|
|
|
|
Slack (MET) : 0.253ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.397ns (logic 6.886ns (44.722%) route 8.511ns (55.278%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.846 9.523 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 13.069 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.069 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -13.069
|
|
-------------------------------------------------------------------
|
|
slack 0.253
|
|
|
|
Slack (MET) : 0.253ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.397ns (logic 6.886ns (44.722%) route 8.511ns (55.278%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.846 9.523 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 13.069 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.069 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -13.069
|
|
-------------------------------------------------------------------
|
|
slack 0.253
|
|
|
|
Slack (MET) : 0.253ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.397ns (logic 6.886ns (44.722%) route 8.511ns (55.278%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.846 9.523 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 13.069 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.069 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -13.069
|
|
-------------------------------------------------------------------
|
|
slack 0.253
|
|
|
|
Slack (MET) : 0.253ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.397ns (logic 6.886ns (44.722%) route 8.511ns (55.278%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.846 9.523 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 13.069 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.069 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -13.069
|
|
-------------------------------------------------------------------
|
|
slack 0.253
|
|
|
|
Slack (MET) : 0.253ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.397ns (logic 6.886ns (44.722%) route 8.511ns (55.278%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.846 9.523 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 13.069 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.069 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -13.069
|
|
-------------------------------------------------------------------
|
|
slack 0.253
|
|
|
|
Slack (MET) : 0.253ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.397ns (logic 6.886ns (44.722%) route 8.511ns (55.278%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.846 9.523 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 13.069 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.069 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -13.069
|
|
-------------------------------------------------------------------
|
|
slack 0.253
|
|
|
|
Slack (MET) : 0.253ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.397ns (logic 6.886ns (44.722%) route 8.511ns (55.278%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.846 9.523 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 13.069 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.069 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -13.069
|
|
-------------------------------------------------------------------
|
|
slack 0.253
|
|
|
|
Slack (MET) : 0.253ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.397ns (logic 6.886ns (44.722%) route 8.511ns (55.278%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.846 9.523 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 13.069 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.069 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -13.069
|
|
-------------------------------------------------------------------
|
|
slack 0.253
|
|
|
|
Slack (MET) : 0.253ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.397ns (logic 6.886ns (44.722%) route 8.511ns (55.278%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.846 9.523 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 13.069 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.069 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -13.069
|
|
-------------------------------------------------------------------
|
|
slack 0.253
|
|
|
|
Slack (MET) : 0.323ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[18]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.407ns (logic 5.205ns (33.780%) route 10.202ns (66.220%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3
|
|
SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=136, routed) 0.977 2.066 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0
|
|
SLICE_X20Y79 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0
|
|
SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.150 2.216 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O
|
|
net (fo=1, routed) 0.661 2.877 u_matmul_axi_slave/ep_rd_c1[18]
|
|
SLICE_X21Y79 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/I0
|
|
SLICE_X21Y79 LUT4 (Prop_lut4_I0_O) 0.328 3.205 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/O
|
|
net (fo=1, routed) 0.671 3.877 u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0_n_0
|
|
SLICE_X25Y79 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/I4
|
|
SLICE_X25Y79 LUT5 (Prop_lut5_I4_O) 0.124 4.001 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/O
|
|
net (fo=1, routed) 0.578 4.578 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[18]
|
|
SLICE_X29Y79 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/I5
|
|
SLICE_X29Y79 LUT6 (Prop_lut6_I5_O) 0.124 4.702 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/O
|
|
net (fo=3, routed) 0.632 5.334 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18]
|
|
SLICE_X29Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0
|
|
SLICE_X29Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.458 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O
|
|
net (fo=2, routed) 4.015 9.473 ext_ram_data_IOBUF[18]_inst/I
|
|
AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I
|
|
AB17 OBUFT (Prop_obuft_I_O) 3.527 12.999 r ext_ram_data_IOBUF[18]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.999 ext_ram_data[18]
|
|
AB17 r ext_ram_data[18] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.999
|
|
-------------------------------------------------------------------
|
|
slack 0.323
|
|
|
|
Slack (MET) : 0.323ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[18]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.407ns (logic 5.205ns (33.780%) route 10.202ns (66.220%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3
|
|
SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=136, routed) 0.977 2.066 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0
|
|
SLICE_X20Y79 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0
|
|
SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.150 2.216 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O
|
|
net (fo=1, routed) 0.661 2.877 u_matmul_axi_slave/ep_rd_c1[18]
|
|
SLICE_X21Y79 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/I0
|
|
SLICE_X21Y79 LUT4 (Prop_lut4_I0_O) 0.328 3.205 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/O
|
|
net (fo=1, routed) 0.671 3.877 u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0_n_0
|
|
SLICE_X25Y79 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/I4
|
|
SLICE_X25Y79 LUT5 (Prop_lut5_I4_O) 0.124 4.001 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/O
|
|
net (fo=1, routed) 0.578 4.578 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[18]
|
|
SLICE_X29Y79 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/I5
|
|
SLICE_X29Y79 LUT6 (Prop_lut6_I5_O) 0.124 4.702 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/O
|
|
net (fo=3, routed) 0.632 5.334 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18]
|
|
SLICE_X29Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0
|
|
SLICE_X29Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.458 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O
|
|
net (fo=2, routed) 4.015 9.473 ext_ram_data_IOBUF[18]_inst/I
|
|
AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I
|
|
AB17 OBUFT (Prop_obuft_I_O) 3.527 12.999 r ext_ram_data_IOBUF[18]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.999 ext_ram_data[18]
|
|
AB17 r ext_ram_data[18] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.999
|
|
-------------------------------------------------------------------
|
|
slack 0.323
|
|
|
|
Slack (MET) : 0.342ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[22]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.308ns (logic 6.883ns (44.963%) route 8.425ns (55.037%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.760 9.437 ext_ram_data_IOBUF[22]_inst/T
|
|
Y15 f ext_ram_data_IOBUF[22]_inst/OBUFT/T
|
|
Y15 OBUFT (TriStatE_obuft_T_O)
|
|
3.543 12.980 r ext_ram_data_IOBUF[22]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.980 ext_ram_data[22]
|
|
Y15 r ext_ram_data[22] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.980
|
|
-------------------------------------------------------------------
|
|
slack 0.342
|
|
|
|
Slack (MET) : 0.342ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[22]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.308ns (logic 6.883ns (44.963%) route 8.425ns (55.037%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.760 9.437 ext_ram_data_IOBUF[22]_inst/T
|
|
Y15 f ext_ram_data_IOBUF[22]_inst/OBUFT/T
|
|
Y15 OBUFT (TriStatE_obuft_T_O)
|
|
3.543 12.980 r ext_ram_data_IOBUF[22]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.980 ext_ram_data[22]
|
|
Y15 r ext_ram_data[22] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.980
|
|
-------------------------------------------------------------------
|
|
slack 0.342
|
|
|
|
Slack (MET) : 0.342ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[22]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.308ns (logic 6.883ns (44.963%) route 8.425ns (55.037%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.760 9.437 ext_ram_data_IOBUF[22]_inst/T
|
|
Y15 f ext_ram_data_IOBUF[22]_inst/OBUFT/T
|
|
Y15 OBUFT (TriStatE_obuft_T_O)
|
|
3.543 12.980 r ext_ram_data_IOBUF[22]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.980 ext_ram_data[22]
|
|
Y15 r ext_ram_data[22] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.980
|
|
-------------------------------------------------------------------
|
|
slack 0.342
|
|
|
|
Slack (MET) : 0.342ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[22]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.308ns (logic 6.883ns (44.963%) route 8.425ns (55.037%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.760 9.437 ext_ram_data_IOBUF[22]_inst/T
|
|
Y15 f ext_ram_data_IOBUF[22]_inst/OBUFT/T
|
|
Y15 OBUFT (TriStatE_obuft_T_O)
|
|
3.543 12.980 r ext_ram_data_IOBUF[22]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.980 ext_ram_data[22]
|
|
Y15 r ext_ram_data[22] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.980
|
|
-------------------------------------------------------------------
|
|
slack 0.342
|
|
|
|
Slack (MET) : 0.342ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[22]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.308ns (logic 6.883ns (44.963%) route 8.425ns (55.037%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.760 9.437 ext_ram_data_IOBUF[22]_inst/T
|
|
Y15 f ext_ram_data_IOBUF[22]_inst/OBUFT/T
|
|
Y15 OBUFT (TriStatE_obuft_T_O)
|
|
3.543 12.980 r ext_ram_data_IOBUF[22]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.980 ext_ram_data[22]
|
|
Y15 r ext_ram_data[22] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.980
|
|
-------------------------------------------------------------------
|
|
slack 0.342
|
|
|
|
Slack (MET) : 0.342ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[22]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.308ns (logic 6.883ns (44.963%) route 8.425ns (55.037%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.760 9.437 ext_ram_data_IOBUF[22]_inst/T
|
|
Y15 f ext_ram_data_IOBUF[22]_inst/OBUFT/T
|
|
Y15 OBUFT (TriStatE_obuft_T_O)
|
|
3.543 12.980 r ext_ram_data_IOBUF[22]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.980 ext_ram_data[22]
|
|
Y15 r ext_ram_data[22] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.980
|
|
-------------------------------------------------------------------
|
|
slack 0.342
|
|
|
|
Slack (MET) : 0.342ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[22]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.308ns (logic 6.883ns (44.963%) route 8.425ns (55.037%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.760 9.437 ext_ram_data_IOBUF[22]_inst/T
|
|
Y15 f ext_ram_data_IOBUF[22]_inst/OBUFT/T
|
|
Y15 OBUFT (TriStatE_obuft_T_O)
|
|
3.543 12.980 r ext_ram_data_IOBUF[22]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.980 ext_ram_data[22]
|
|
Y15 r ext_ram_data[22] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.980
|
|
-------------------------------------------------------------------
|
|
slack 0.342
|
|
|
|
Slack (MET) : 0.342ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[22]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.308ns (logic 6.883ns (44.963%) route 8.425ns (55.037%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.760 9.437 ext_ram_data_IOBUF[22]_inst/T
|
|
Y15 f ext_ram_data_IOBUF[22]_inst/OBUFT/T
|
|
Y15 OBUFT (TriStatE_obuft_T_O)
|
|
3.543 12.980 r ext_ram_data_IOBUF[22]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.980 ext_ram_data[22]
|
|
Y15 r ext_ram_data[22] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.980
|
|
-------------------------------------------------------------------
|
|
slack 0.342
|
|
|
|
Slack (MET) : 0.342ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[22]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.308ns (logic 6.883ns (44.963%) route 8.425ns (55.037%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.760 9.437 ext_ram_data_IOBUF[22]_inst/T
|
|
Y15 f ext_ram_data_IOBUF[22]_inst/OBUFT/T
|
|
Y15 OBUFT (TriStatE_obuft_T_O)
|
|
3.543 12.980 r ext_ram_data_IOBUF[22]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.980 ext_ram_data[22]
|
|
Y15 r ext_ram_data[22] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.980
|
|
-------------------------------------------------------------------
|
|
slack 0.342
|
|
|
|
Slack (MET) : 0.342ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[22]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.308ns (logic 6.883ns (44.963%) route 8.425ns (55.037%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.760 9.437 ext_ram_data_IOBUF[22]_inst/T
|
|
Y15 f ext_ram_data_IOBUF[22]_inst/OBUFT/T
|
|
Y15 OBUFT (TriStatE_obuft_T_O)
|
|
3.543 12.980 r ext_ram_data_IOBUF[22]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.980 ext_ram_data[22]
|
|
Y15 r ext_ram_data[22] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.980
|
|
-------------------------------------------------------------------
|
|
slack 0.342
|
|
|
|
Slack (MET) : 0.395ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[20]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.335ns (logic 5.244ns (34.199%) route 10.090ns (65.801%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4
|
|
SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=136, routed) 1.322 2.300 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRB1
|
|
SLICE_X20Y79 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/RADR1
|
|
SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.152 2.452 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/O
|
|
net (fo=1, routed) 0.667 3.119 u_matmul_axi_slave/ep_rd_c1[20]
|
|
SLICE_X24Y78 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/I0
|
|
SLICE_X24Y78 LUT4 (Prop_lut4_I0_O) 0.348 3.467 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/O
|
|
net (fo=1, routed) 0.430 3.897 u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0_n_0
|
|
SLICE_X24Y78 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/I4
|
|
SLICE_X24Y78 LUT5 (Prop_lut5_I4_O) 0.124 4.021 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/O
|
|
net (fo=1, routed) 0.598 4.620 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[20]
|
|
SLICE_X28Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/I5
|
|
SLICE_X28Y80 LUT6 (Prop_lut6_I5_O) 0.124 4.744 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/O
|
|
net (fo=3, routed) 0.682 5.425 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20]
|
|
SLICE_X28Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0
|
|
SLICE_X28Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.549 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O
|
|
net (fo=2, routed) 3.834 9.383 ext_ram_data_IOBUF[20]_inst/I
|
|
AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I
|
|
AD18 OBUFT (Prop_obuft_I_O) 3.544 12.927 r ext_ram_data_IOBUF[20]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.927 ext_ram_data[20]
|
|
AD18 r ext_ram_data[20] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.927
|
|
-------------------------------------------------------------------
|
|
slack 0.395
|
|
|
|
Slack (MET) : 0.395ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[20]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.335ns (logic 5.244ns (34.199%) route 10.090ns (65.801%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4
|
|
SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=136, routed) 1.322 2.300 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRB1
|
|
SLICE_X20Y79 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/RADR1
|
|
SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.152 2.452 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/O
|
|
net (fo=1, routed) 0.667 3.119 u_matmul_axi_slave/ep_rd_c1[20]
|
|
SLICE_X24Y78 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/I0
|
|
SLICE_X24Y78 LUT4 (Prop_lut4_I0_O) 0.348 3.467 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/O
|
|
net (fo=1, routed) 0.430 3.897 u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0_n_0
|
|
SLICE_X24Y78 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/I4
|
|
SLICE_X24Y78 LUT5 (Prop_lut5_I4_O) 0.124 4.021 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/O
|
|
net (fo=1, routed) 0.598 4.620 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[20]
|
|
SLICE_X28Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/I5
|
|
SLICE_X28Y80 LUT6 (Prop_lut6_I5_O) 0.124 4.744 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/O
|
|
net (fo=3, routed) 0.682 5.425 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20]
|
|
SLICE_X28Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0
|
|
SLICE_X28Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.549 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O
|
|
net (fo=2, routed) 3.834 9.383 ext_ram_data_IOBUF[20]_inst/I
|
|
AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I
|
|
AD18 OBUFT (Prop_obuft_I_O) 3.544 12.927 r ext_ram_data_IOBUF[20]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.927 ext_ram_data[20]
|
|
AD18 r ext_ram_data[20] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.927
|
|
-------------------------------------------------------------------
|
|
slack 0.395
|
|
|
|
Slack (MET) : 0.395ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[20]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.335ns (logic 5.244ns (34.199%) route 10.090ns (65.801%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4
|
|
SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=136, routed) 1.322 2.300 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRB1
|
|
SLICE_X20Y79 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/RADR1
|
|
SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.152 2.452 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/O
|
|
net (fo=1, routed) 0.667 3.119 u_matmul_axi_slave/ep_rd_c1[20]
|
|
SLICE_X24Y78 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/I0
|
|
SLICE_X24Y78 LUT4 (Prop_lut4_I0_O) 0.348 3.467 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/O
|
|
net (fo=1, routed) 0.430 3.897 u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0_n_0
|
|
SLICE_X24Y78 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/I4
|
|
SLICE_X24Y78 LUT5 (Prop_lut5_I4_O) 0.124 4.021 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/O
|
|
net (fo=1, routed) 0.598 4.620 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[20]
|
|
SLICE_X28Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/I5
|
|
SLICE_X28Y80 LUT6 (Prop_lut6_I5_O) 0.124 4.744 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/O
|
|
net (fo=3, routed) 0.682 5.425 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20]
|
|
SLICE_X28Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0
|
|
SLICE_X28Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.549 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O
|
|
net (fo=2, routed) 3.834 9.383 ext_ram_data_IOBUF[20]_inst/I
|
|
AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I
|
|
AD18 OBUFT (Prop_obuft_I_O) 3.544 12.927 r ext_ram_data_IOBUF[20]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.927 ext_ram_data[20]
|
|
AD18 r ext_ram_data[20] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.927
|
|
-------------------------------------------------------------------
|
|
slack 0.395
|
|
|
|
Slack (MET) : 0.395ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[20]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.335ns (logic 5.244ns (34.199%) route 10.090ns (65.801%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4
|
|
SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=136, routed) 1.322 2.300 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRB1
|
|
SLICE_X20Y79 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/RADR1
|
|
SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.152 2.452 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/O
|
|
net (fo=1, routed) 0.667 3.119 u_matmul_axi_slave/ep_rd_c1[20]
|
|
SLICE_X24Y78 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/I0
|
|
SLICE_X24Y78 LUT4 (Prop_lut4_I0_O) 0.348 3.467 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/O
|
|
net (fo=1, routed) 0.430 3.897 u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0_n_0
|
|
SLICE_X24Y78 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/I4
|
|
SLICE_X24Y78 LUT5 (Prop_lut5_I4_O) 0.124 4.021 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/O
|
|
net (fo=1, routed) 0.598 4.620 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[20]
|
|
SLICE_X28Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/I5
|
|
SLICE_X28Y80 LUT6 (Prop_lut6_I5_O) 0.124 4.744 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/O
|
|
net (fo=3, routed) 0.682 5.425 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20]
|
|
SLICE_X28Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0
|
|
SLICE_X28Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.549 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O
|
|
net (fo=2, routed) 3.834 9.383 ext_ram_data_IOBUF[20]_inst/I
|
|
AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I
|
|
AD18 OBUFT (Prop_obuft_I_O) 3.544 12.927 r ext_ram_data_IOBUF[20]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.927 ext_ram_data[20]
|
|
AD18 r ext_ram_data[20] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.927
|
|
-------------------------------------------------------------------
|
|
slack 0.395
|
|
|
|
Slack (MET) : 0.395ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[20]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.335ns (logic 5.244ns (34.199%) route 10.090ns (65.801%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4
|
|
SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=136, routed) 1.322 2.300 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRB1
|
|
SLICE_X20Y79 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/RADR1
|
|
SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.152 2.452 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/O
|
|
net (fo=1, routed) 0.667 3.119 u_matmul_axi_slave/ep_rd_c1[20]
|
|
SLICE_X24Y78 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/I0
|
|
SLICE_X24Y78 LUT4 (Prop_lut4_I0_O) 0.348 3.467 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/O
|
|
net (fo=1, routed) 0.430 3.897 u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0_n_0
|
|
SLICE_X24Y78 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/I4
|
|
SLICE_X24Y78 LUT5 (Prop_lut5_I4_O) 0.124 4.021 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/O
|
|
net (fo=1, routed) 0.598 4.620 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[20]
|
|
SLICE_X28Y80 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/I5
|
|
SLICE_X28Y80 LUT6 (Prop_lut6_I5_O) 0.124 4.744 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/O
|
|
net (fo=3, routed) 0.682 5.425 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20]
|
|
SLICE_X28Y80 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0
|
|
SLICE_X28Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.549 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O
|
|
net (fo=2, routed) 3.834 9.383 ext_ram_data_IOBUF[20]_inst/I
|
|
AD18 f ext_ram_data_IOBUF[20]_inst/OBUFT/I
|
|
AD18 OBUFT (Prop_obuft_I_O) 3.544 12.927 f ext_ram_data_IOBUF[20]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.927 ext_ram_data[20]
|
|
AD18 f ext_ram_data[20] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.927
|
|
-------------------------------------------------------------------
|
|
slack 0.395
|
|
|
|
Slack (MET) : 0.395ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[20]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.335ns (logic 5.244ns (34.199%) route 10.090ns (65.801%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4
|
|
SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=136, routed) 1.322 2.300 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRB1
|
|
SLICE_X20Y79 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/RADR1
|
|
SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.152 2.452 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/O
|
|
net (fo=1, routed) 0.667 3.119 u_matmul_axi_slave/ep_rd_c1[20]
|
|
SLICE_X24Y78 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/I0
|
|
SLICE_X24Y78 LUT4 (Prop_lut4_I0_O) 0.348 3.467 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/O
|
|
net (fo=1, routed) 0.430 3.897 u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0_n_0
|
|
SLICE_X24Y78 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/I4
|
|
SLICE_X24Y78 LUT5 (Prop_lut5_I4_O) 0.124 4.021 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/O
|
|
net (fo=1, routed) 0.598 4.620 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[20]
|
|
SLICE_X28Y80 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/I5
|
|
SLICE_X28Y80 LUT6 (Prop_lut6_I5_O) 0.124 4.744 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/O
|
|
net (fo=3, routed) 0.682 5.425 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20]
|
|
SLICE_X28Y80 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0
|
|
SLICE_X28Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.549 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O
|
|
net (fo=2, routed) 3.834 9.383 ext_ram_data_IOBUF[20]_inst/I
|
|
AD18 f ext_ram_data_IOBUF[20]_inst/OBUFT/I
|
|
AD18 OBUFT (Prop_obuft_I_O) 3.544 12.927 f ext_ram_data_IOBUF[20]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.927 ext_ram_data[20]
|
|
AD18 f ext_ram_data[20] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.927
|
|
-------------------------------------------------------------------
|
|
slack 0.395
|
|
|
|
Slack (MET) : 0.395ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[20]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.335ns (logic 5.244ns (34.199%) route 10.090ns (65.801%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4
|
|
SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=136, routed) 1.322 2.300 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRB1
|
|
SLICE_X20Y79 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/RADR1
|
|
SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.152 2.452 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/O
|
|
net (fo=1, routed) 0.667 3.119 u_matmul_axi_slave/ep_rd_c1[20]
|
|
SLICE_X24Y78 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/I0
|
|
SLICE_X24Y78 LUT4 (Prop_lut4_I0_O) 0.348 3.467 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/O
|
|
net (fo=1, routed) 0.430 3.897 u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0_n_0
|
|
SLICE_X24Y78 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/I4
|
|
SLICE_X24Y78 LUT5 (Prop_lut5_I4_O) 0.124 4.021 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/O
|
|
net (fo=1, routed) 0.598 4.620 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[20]
|
|
SLICE_X28Y80 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/I5
|
|
SLICE_X28Y80 LUT6 (Prop_lut6_I5_O) 0.124 4.744 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/O
|
|
net (fo=3, routed) 0.682 5.425 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20]
|
|
SLICE_X28Y80 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0
|
|
SLICE_X28Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.549 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O
|
|
net (fo=2, routed) 3.834 9.383 ext_ram_data_IOBUF[20]_inst/I
|
|
AD18 f ext_ram_data_IOBUF[20]_inst/OBUFT/I
|
|
AD18 OBUFT (Prop_obuft_I_O) 3.544 12.927 f ext_ram_data_IOBUF[20]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.927 ext_ram_data[20]
|
|
AD18 f ext_ram_data[20] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.927
|
|
-------------------------------------------------------------------
|
|
slack 0.395
|
|
|
|
Slack (MET) : 0.395ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[20]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.335ns (logic 5.244ns (34.199%) route 10.090ns (65.801%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4
|
|
SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=136, routed) 1.322 2.300 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRB1
|
|
SLICE_X20Y79 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/RADR1
|
|
SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.152 2.452 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/O
|
|
net (fo=1, routed) 0.667 3.119 u_matmul_axi_slave/ep_rd_c1[20]
|
|
SLICE_X24Y78 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/I0
|
|
SLICE_X24Y78 LUT4 (Prop_lut4_I0_O) 0.348 3.467 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/O
|
|
net (fo=1, routed) 0.430 3.897 u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0_n_0
|
|
SLICE_X24Y78 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/I4
|
|
SLICE_X24Y78 LUT5 (Prop_lut5_I4_O) 0.124 4.021 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/O
|
|
net (fo=1, routed) 0.598 4.620 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[20]
|
|
SLICE_X28Y80 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/I5
|
|
SLICE_X28Y80 LUT6 (Prop_lut6_I5_O) 0.124 4.744 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/O
|
|
net (fo=3, routed) 0.682 5.425 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20]
|
|
SLICE_X28Y80 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0
|
|
SLICE_X28Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.549 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O
|
|
net (fo=2, routed) 3.834 9.383 ext_ram_data_IOBUF[20]_inst/I
|
|
AD18 f ext_ram_data_IOBUF[20]_inst/OBUFT/I
|
|
AD18 OBUFT (Prop_obuft_I_O) 3.544 12.927 f ext_ram_data_IOBUF[20]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.927 ext_ram_data[20]
|
|
AD18 f ext_ram_data[20] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.927
|
|
-------------------------------------------------------------------
|
|
slack 0.395
|
|
|
|
Slack (MET) : 0.403ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.248ns (logic 6.876ns (45.098%) route 8.371ns (54.902%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.706 9.383 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 12.919 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.919 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.919
|
|
-------------------------------------------------------------------
|
|
slack 0.403
|
|
|
|
Slack (MET) : 0.403ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.248ns (logic 6.876ns (45.098%) route 8.371ns (54.902%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.706 9.383 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 12.919 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.919 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.919
|
|
-------------------------------------------------------------------
|
|
slack 0.403
|
|
|
|
Slack (MET) : 0.403ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.248ns (logic 6.876ns (45.098%) route 8.371ns (54.902%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.706 9.383 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 12.919 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.919 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.919
|
|
-------------------------------------------------------------------
|
|
slack 0.403
|
|
|
|
Slack (MET) : 0.403ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.248ns (logic 6.876ns (45.098%) route 8.371ns (54.902%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.706 9.383 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 12.919 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.919 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.919
|
|
-------------------------------------------------------------------
|
|
slack 0.403
|
|
|
|
Slack (MET) : 0.403ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.248ns (logic 6.876ns (45.098%) route 8.371ns (54.902%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.706 9.383 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 12.919 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.919 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.919
|
|
-------------------------------------------------------------------
|
|
slack 0.403
|
|
|
|
Slack (MET) : 0.403ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.248ns (logic 6.876ns (45.098%) route 8.371ns (54.902%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.706 9.383 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 12.919 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.919 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.919
|
|
-------------------------------------------------------------------
|
|
slack 0.403
|
|
|
|
Slack (MET) : 0.403ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.248ns (logic 6.876ns (45.098%) route 8.371ns (54.902%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.706 9.383 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 12.919 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.919 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.919
|
|
-------------------------------------------------------------------
|
|
slack 0.403
|
|
|
|
Slack (MET) : 0.403ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.248ns (logic 6.876ns (45.098%) route 8.371ns (54.902%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.706 9.383 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 12.919 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.919 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.919
|
|
-------------------------------------------------------------------
|
|
slack 0.403
|
|
|
|
Slack (MET) : 0.403ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.248ns (logic 6.876ns (45.098%) route 8.371ns (54.902%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.706 9.383 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 12.919 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.919 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.919
|
|
-------------------------------------------------------------------
|
|
slack 0.403
|
|
|
|
Slack (MET) : 0.403ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.248ns (logic 6.876ns (45.098%) route 8.371ns (54.902%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.706 9.383 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 12.919 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.919 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.919
|
|
-------------------------------------------------------------------
|
|
slack 0.403
|
|
|
|
Slack (MET) : 0.416ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[6]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.314ns (logic 5.138ns (33.551%) route 10.176ns (66.449%))
|
|
Logic Levels: 8 (LUT3=1 LUT4=1 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4
|
|
SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=136, routed) 1.690 2.668 u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/ADDRB1
|
|
SLICE_X36Y83 r u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/RADR1
|
|
SLICE_X36Y83 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.152 2.820 r u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/O
|
|
net (fo=1, routed) 1.421 4.241 u_matmul_axi_slave/ep_rd_c1[38]
|
|
SLICE_X23Y79 r u_matmul_axi_slave/ram_reg_i_46/I3
|
|
SLICE_X23Y79 LUT5 (Prop_lut5_I3_O) 0.348 4.589 r u_matmul_axi_slave/ram_reg_i_46/O
|
|
net (fo=1, routed) 0.461 5.050 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[6]
|
|
SLICE_X19Y79 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/I5
|
|
SLICE_X19Y79 LUT6 (Prop_lut6_I5_O) 0.124 5.174 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/O
|
|
net (fo=4, routed) 0.529 5.703 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1
|
|
SLICE_X12Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/I0
|
|
SLICE_X12Y76 LUT3 (Prop_lut3_I0_O) 0.124 5.827 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/O
|
|
net (fo=2, routed) 3.517 9.344 ext_ram_data_IOBUF[6]_inst/I
|
|
AE20 r ext_ram_data_IOBUF[6]_inst/OBUFT/I
|
|
AE20 OBUFT (Prop_obuft_I_O) 3.562 12.906 r ext_ram_data_IOBUF[6]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.906 ext_ram_data[6]
|
|
AE20 r ext_ram_data[6] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.906
|
|
-------------------------------------------------------------------
|
|
slack 0.416
|
|
|
|
Slack (MET) : 0.416ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[6]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.314ns (logic 5.138ns (33.551%) route 10.176ns (66.449%))
|
|
Logic Levels: 8 (LUT3=1 LUT4=1 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4
|
|
SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=136, routed) 1.690 2.668 u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/ADDRB1
|
|
SLICE_X36Y83 r u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/RADR1
|
|
SLICE_X36Y83 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.152 2.820 r u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/O
|
|
net (fo=1, routed) 1.421 4.241 u_matmul_axi_slave/ep_rd_c1[38]
|
|
SLICE_X23Y79 r u_matmul_axi_slave/ram_reg_i_46/I3
|
|
SLICE_X23Y79 LUT5 (Prop_lut5_I3_O) 0.348 4.589 r u_matmul_axi_slave/ram_reg_i_46/O
|
|
net (fo=1, routed) 0.461 5.050 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[6]
|
|
SLICE_X19Y79 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/I5
|
|
SLICE_X19Y79 LUT6 (Prop_lut6_I5_O) 0.124 5.174 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/O
|
|
net (fo=4, routed) 0.529 5.703 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1
|
|
SLICE_X12Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/I0
|
|
SLICE_X12Y76 LUT3 (Prop_lut3_I0_O) 0.124 5.827 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/O
|
|
net (fo=2, routed) 3.517 9.344 ext_ram_data_IOBUF[6]_inst/I
|
|
AE20 r ext_ram_data_IOBUF[6]_inst/OBUFT/I
|
|
AE20 OBUFT (Prop_obuft_I_O) 3.562 12.906 r ext_ram_data_IOBUF[6]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.906 ext_ram_data[6]
|
|
AE20 r ext_ram_data[6] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.906
|
|
-------------------------------------------------------------------
|
|
slack 0.416
|
|
|
|
Slack (MET) : 0.416ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[6]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.314ns (logic 5.138ns (33.551%) route 10.176ns (66.449%))
|
|
Logic Levels: 8 (LUT3=1 LUT4=1 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4
|
|
SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=136, routed) 1.690 2.668 u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/ADDRB1
|
|
SLICE_X36Y83 f u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/RADR1
|
|
SLICE_X36Y83 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.152 2.820 r u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/O
|
|
net (fo=1, routed) 1.421 4.241 u_matmul_axi_slave/ep_rd_c1[38]
|
|
SLICE_X23Y79 r u_matmul_axi_slave/ram_reg_i_46/I3
|
|
SLICE_X23Y79 LUT5 (Prop_lut5_I3_O) 0.348 4.589 r u_matmul_axi_slave/ram_reg_i_46/O
|
|
net (fo=1, routed) 0.461 5.050 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[6]
|
|
SLICE_X19Y79 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/I5
|
|
SLICE_X19Y79 LUT6 (Prop_lut6_I5_O) 0.124 5.174 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/O
|
|
net (fo=4, routed) 0.529 5.703 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1
|
|
SLICE_X12Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/I0
|
|
SLICE_X12Y76 LUT3 (Prop_lut3_I0_O) 0.124 5.827 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/O
|
|
net (fo=2, routed) 3.517 9.344 ext_ram_data_IOBUF[6]_inst/I
|
|
AE20 r ext_ram_data_IOBUF[6]_inst/OBUFT/I
|
|
AE20 OBUFT (Prop_obuft_I_O) 3.562 12.906 r ext_ram_data_IOBUF[6]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.906 ext_ram_data[6]
|
|
AE20 r ext_ram_data[6] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.906
|
|
-------------------------------------------------------------------
|
|
slack 0.416
|
|
|
|
Slack (MET) : 0.416ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[6]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.314ns (logic 5.138ns (33.551%) route 10.176ns (66.449%))
|
|
Logic Levels: 8 (LUT3=1 LUT4=1 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4
|
|
SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=136, routed) 1.690 2.668 u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/ADDRB1
|
|
SLICE_X36Y83 f u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/RADR1
|
|
SLICE_X36Y83 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.152 2.820 r u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/O
|
|
net (fo=1, routed) 1.421 4.241 u_matmul_axi_slave/ep_rd_c1[38]
|
|
SLICE_X23Y79 r u_matmul_axi_slave/ram_reg_i_46/I3
|
|
SLICE_X23Y79 LUT5 (Prop_lut5_I3_O) 0.348 4.589 r u_matmul_axi_slave/ram_reg_i_46/O
|
|
net (fo=1, routed) 0.461 5.050 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[6]
|
|
SLICE_X19Y79 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/I5
|
|
SLICE_X19Y79 LUT6 (Prop_lut6_I5_O) 0.124 5.174 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/O
|
|
net (fo=4, routed) 0.529 5.703 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1
|
|
SLICE_X12Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/I0
|
|
SLICE_X12Y76 LUT3 (Prop_lut3_I0_O) 0.124 5.827 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/O
|
|
net (fo=2, routed) 3.517 9.344 ext_ram_data_IOBUF[6]_inst/I
|
|
AE20 r ext_ram_data_IOBUF[6]_inst/OBUFT/I
|
|
AE20 OBUFT (Prop_obuft_I_O) 3.562 12.906 r ext_ram_data_IOBUF[6]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.906 ext_ram_data[6]
|
|
AE20 r ext_ram_data[6] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.906
|
|
-------------------------------------------------------------------
|
|
slack 0.416
|
|
|
|
Slack (MET) : 0.416ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[6]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.314ns (logic 5.138ns (33.551%) route 10.176ns (66.449%))
|
|
Logic Levels: 8 (LUT3=1 LUT4=1 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4
|
|
SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=136, routed) 1.690 2.668 u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/ADDRB1
|
|
SLICE_X36Y83 r u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/RADR1
|
|
SLICE_X36Y83 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.152 2.820 f u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/O
|
|
net (fo=1, routed) 1.421 4.241 u_matmul_axi_slave/ep_rd_c1[38]
|
|
SLICE_X23Y79 f u_matmul_axi_slave/ram_reg_i_46/I3
|
|
SLICE_X23Y79 LUT5 (Prop_lut5_I3_O) 0.348 4.589 f u_matmul_axi_slave/ram_reg_i_46/O
|
|
net (fo=1, routed) 0.461 5.050 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[6]
|
|
SLICE_X19Y79 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/I5
|
|
SLICE_X19Y79 LUT6 (Prop_lut6_I5_O) 0.124 5.174 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/O
|
|
net (fo=4, routed) 0.529 5.703 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1
|
|
SLICE_X12Y76 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/I0
|
|
SLICE_X12Y76 LUT3 (Prop_lut3_I0_O) 0.124 5.827 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/O
|
|
net (fo=2, routed) 3.517 9.344 ext_ram_data_IOBUF[6]_inst/I
|
|
AE20 f ext_ram_data_IOBUF[6]_inst/OBUFT/I
|
|
AE20 OBUFT (Prop_obuft_I_O) 3.562 12.906 f ext_ram_data_IOBUF[6]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.906 ext_ram_data[6]
|
|
AE20 f ext_ram_data[6] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.906
|
|
-------------------------------------------------------------------
|
|
slack 0.416
|
|
|
|
Slack (MET) : 0.416ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[6]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.314ns (logic 5.138ns (33.551%) route 10.176ns (66.449%))
|
|
Logic Levels: 8 (LUT3=1 LUT4=1 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4
|
|
SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=136, routed) 1.690 2.668 u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/ADDRB1
|
|
SLICE_X36Y83 r u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/RADR1
|
|
SLICE_X36Y83 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.152 2.820 f u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/O
|
|
net (fo=1, routed) 1.421 4.241 u_matmul_axi_slave/ep_rd_c1[38]
|
|
SLICE_X23Y79 f u_matmul_axi_slave/ram_reg_i_46/I3
|
|
SLICE_X23Y79 LUT5 (Prop_lut5_I3_O) 0.348 4.589 f u_matmul_axi_slave/ram_reg_i_46/O
|
|
net (fo=1, routed) 0.461 5.050 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[6]
|
|
SLICE_X19Y79 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/I5
|
|
SLICE_X19Y79 LUT6 (Prop_lut6_I5_O) 0.124 5.174 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/O
|
|
net (fo=4, routed) 0.529 5.703 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1
|
|
SLICE_X12Y76 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/I0
|
|
SLICE_X12Y76 LUT3 (Prop_lut3_I0_O) 0.124 5.827 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/O
|
|
net (fo=2, routed) 3.517 9.344 ext_ram_data_IOBUF[6]_inst/I
|
|
AE20 f ext_ram_data_IOBUF[6]_inst/OBUFT/I
|
|
AE20 OBUFT (Prop_obuft_I_O) 3.562 12.906 f ext_ram_data_IOBUF[6]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.906 ext_ram_data[6]
|
|
AE20 f ext_ram_data[6] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.906
|
|
-------------------------------------------------------------------
|
|
slack 0.416
|
|
|
|
Slack (MET) : 0.416ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[6]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.314ns (logic 5.138ns (33.551%) route 10.176ns (66.449%))
|
|
Logic Levels: 8 (LUT3=1 LUT4=1 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4
|
|
SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=136, routed) 1.690 2.668 u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/ADDRB1
|
|
SLICE_X36Y83 f u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/RADR1
|
|
SLICE_X36Y83 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.152 2.820 f u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/O
|
|
net (fo=1, routed) 1.421 4.241 u_matmul_axi_slave/ep_rd_c1[38]
|
|
SLICE_X23Y79 f u_matmul_axi_slave/ram_reg_i_46/I3
|
|
SLICE_X23Y79 LUT5 (Prop_lut5_I3_O) 0.348 4.589 f u_matmul_axi_slave/ram_reg_i_46/O
|
|
net (fo=1, routed) 0.461 5.050 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[6]
|
|
SLICE_X19Y79 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/I5
|
|
SLICE_X19Y79 LUT6 (Prop_lut6_I5_O) 0.124 5.174 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/O
|
|
net (fo=4, routed) 0.529 5.703 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1
|
|
SLICE_X12Y76 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/I0
|
|
SLICE_X12Y76 LUT3 (Prop_lut3_I0_O) 0.124 5.827 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/O
|
|
net (fo=2, routed) 3.517 9.344 ext_ram_data_IOBUF[6]_inst/I
|
|
AE20 f ext_ram_data_IOBUF[6]_inst/OBUFT/I
|
|
AE20 OBUFT (Prop_obuft_I_O) 3.562 12.906 f ext_ram_data_IOBUF[6]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.906 ext_ram_data[6]
|
|
AE20 f ext_ram_data[6] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.906
|
|
-------------------------------------------------------------------
|
|
slack 0.416
|
|
|
|
Slack (MET) : 0.416ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[6]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.314ns (logic 5.138ns (33.551%) route 10.176ns (66.449%))
|
|
Logic Levels: 8 (LUT3=1 LUT4=1 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4
|
|
SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=136, routed) 1.690 2.668 u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/ADDRB1
|
|
SLICE_X36Y83 f u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/RADR1
|
|
SLICE_X36Y83 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.152 2.820 f u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/O
|
|
net (fo=1, routed) 1.421 4.241 u_matmul_axi_slave/ep_rd_c1[38]
|
|
SLICE_X23Y79 f u_matmul_axi_slave/ram_reg_i_46/I3
|
|
SLICE_X23Y79 LUT5 (Prop_lut5_I3_O) 0.348 4.589 f u_matmul_axi_slave/ram_reg_i_46/O
|
|
net (fo=1, routed) 0.461 5.050 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[6]
|
|
SLICE_X19Y79 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/I5
|
|
SLICE_X19Y79 LUT6 (Prop_lut6_I5_O) 0.124 5.174 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/O
|
|
net (fo=4, routed) 0.529 5.703 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1
|
|
SLICE_X12Y76 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/I0
|
|
SLICE_X12Y76 LUT3 (Prop_lut3_I0_O) 0.124 5.827 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/O
|
|
net (fo=2, routed) 3.517 9.344 ext_ram_data_IOBUF[6]_inst/I
|
|
AE20 f ext_ram_data_IOBUF[6]_inst/OBUFT/I
|
|
AE20 OBUFT (Prop_obuft_I_O) 3.562 12.906 f ext_ram_data_IOBUF[6]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.906 ext_ram_data[6]
|
|
AE20 f ext_ram_data[6] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.906
|
|
-------------------------------------------------------------------
|
|
slack 0.416
|
|
|
|
Slack (MET) : 0.422ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[31]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.308ns (logic 5.033ns (32.879%) route 10.275ns (67.121%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3
|
|
SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0
|
|
SLICE_X22Y86 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0
|
|
SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O
|
|
net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31]
|
|
SLICE_X24Y84 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0
|
|
SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O
|
|
net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0
|
|
SLICE_X24Y83 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4
|
|
SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O
|
|
net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31]
|
|
SLICE_X27Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5
|
|
SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O
|
|
net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31]
|
|
SLICE_X30Y85 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0
|
|
SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=2, routed) 3.465 9.315 ext_ram_data_IOBUF[31]_inst/I
|
|
AC23 r ext_ram_data_IOBUF[31]_inst/OBUFT/I
|
|
AC23 OBUFT (Prop_obuft_I_O) 3.585 12.900 r ext_ram_data_IOBUF[31]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.900 ext_ram_data[31]
|
|
AC23 r ext_ram_data[31] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.900
|
|
-------------------------------------------------------------------
|
|
slack 0.422
|
|
|
|
Slack (MET) : 0.422ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[31]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.308ns (logic 5.033ns (32.879%) route 10.275ns (67.121%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3
|
|
SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0
|
|
SLICE_X22Y86 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0
|
|
SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O
|
|
net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31]
|
|
SLICE_X24Y84 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0
|
|
SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O
|
|
net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0
|
|
SLICE_X24Y83 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4
|
|
SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O
|
|
net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31]
|
|
SLICE_X27Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5
|
|
SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O
|
|
net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31]
|
|
SLICE_X30Y85 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0
|
|
SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=2, routed) 3.465 9.315 ext_ram_data_IOBUF[31]_inst/I
|
|
AC23 r ext_ram_data_IOBUF[31]_inst/OBUFT/I
|
|
AC23 OBUFT (Prop_obuft_I_O) 3.585 12.900 r ext_ram_data_IOBUF[31]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.900 ext_ram_data[31]
|
|
AC23 r ext_ram_data[31] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.900
|
|
-------------------------------------------------------------------
|
|
slack 0.422
|
|
|
|
Slack (MET) : 0.422ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[31]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.308ns (logic 5.033ns (32.879%) route 10.275ns (67.121%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3
|
|
SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0
|
|
SLICE_X22Y86 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0
|
|
SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O
|
|
net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31]
|
|
SLICE_X24Y84 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0
|
|
SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O
|
|
net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0
|
|
SLICE_X24Y83 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4
|
|
SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O
|
|
net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31]
|
|
SLICE_X27Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5
|
|
SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O
|
|
net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31]
|
|
SLICE_X30Y85 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0
|
|
SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=2, routed) 3.465 9.315 ext_ram_data_IOBUF[31]_inst/I
|
|
AC23 r ext_ram_data_IOBUF[31]_inst/OBUFT/I
|
|
AC23 OBUFT (Prop_obuft_I_O) 3.585 12.900 r ext_ram_data_IOBUF[31]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.900 ext_ram_data[31]
|
|
AC23 r ext_ram_data[31] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.900
|
|
-------------------------------------------------------------------
|
|
slack 0.422
|
|
|
|
Slack (MET) : 0.422ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[31]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.308ns (logic 5.033ns (32.879%) route 10.275ns (67.121%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3
|
|
SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0
|
|
SLICE_X22Y86 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0
|
|
SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O
|
|
net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31]
|
|
SLICE_X24Y84 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0
|
|
SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O
|
|
net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0
|
|
SLICE_X24Y83 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4
|
|
SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O
|
|
net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31]
|
|
SLICE_X27Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5
|
|
SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O
|
|
net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31]
|
|
SLICE_X30Y85 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0
|
|
SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=2, routed) 3.465 9.315 ext_ram_data_IOBUF[31]_inst/I
|
|
AC23 r ext_ram_data_IOBUF[31]_inst/OBUFT/I
|
|
AC23 OBUFT (Prop_obuft_I_O) 3.585 12.900 r ext_ram_data_IOBUF[31]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.900 ext_ram_data[31]
|
|
AC23 r ext_ram_data[31] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.900
|
|
-------------------------------------------------------------------
|
|
slack 0.422
|
|
|
|
Slack (MET) : 0.422ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[31]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.308ns (logic 5.033ns (32.879%) route 10.275ns (67.121%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3
|
|
SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0
|
|
SLICE_X22Y86 f u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0
|
|
SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O
|
|
net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31]
|
|
SLICE_X24Y84 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0
|
|
SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O
|
|
net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0
|
|
SLICE_X24Y83 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4
|
|
SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O
|
|
net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31]
|
|
SLICE_X27Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5
|
|
SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O
|
|
net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31]
|
|
SLICE_X30Y85 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0
|
|
SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=2, routed) 3.465 9.315 ext_ram_data_IOBUF[31]_inst/I
|
|
AC23 r ext_ram_data_IOBUF[31]_inst/OBUFT/I
|
|
AC23 OBUFT (Prop_obuft_I_O) 3.585 12.900 r ext_ram_data_IOBUF[31]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.900 ext_ram_data[31]
|
|
AC23 r ext_ram_data[31] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.900
|
|
-------------------------------------------------------------------
|
|
slack 0.422
|
|
|
|
Slack (MET) : 0.422ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[31]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.308ns (logic 5.033ns (32.879%) route 10.275ns (67.121%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3
|
|
SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0
|
|
SLICE_X22Y86 f u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0
|
|
SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O
|
|
net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31]
|
|
SLICE_X24Y84 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0
|
|
SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O
|
|
net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0
|
|
SLICE_X24Y83 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4
|
|
SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O
|
|
net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31]
|
|
SLICE_X27Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5
|
|
SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O
|
|
net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31]
|
|
SLICE_X30Y85 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0
|
|
SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=2, routed) 3.465 9.315 ext_ram_data_IOBUF[31]_inst/I
|
|
AC23 r ext_ram_data_IOBUF[31]_inst/OBUFT/I
|
|
AC23 OBUFT (Prop_obuft_I_O) 3.585 12.900 r ext_ram_data_IOBUF[31]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.900 ext_ram_data[31]
|
|
AC23 r ext_ram_data[31] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.900
|
|
-------------------------------------------------------------------
|
|
slack 0.422
|
|
|
|
Slack (MET) : 0.422ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[31]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.308ns (logic 5.033ns (32.879%) route 10.275ns (67.121%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3
|
|
SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0
|
|
SLICE_X22Y86 f u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0
|
|
SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O
|
|
net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31]
|
|
SLICE_X24Y84 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0
|
|
SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O
|
|
net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0
|
|
SLICE_X24Y83 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4
|
|
SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O
|
|
net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31]
|
|
SLICE_X27Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5
|
|
SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O
|
|
net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31]
|
|
SLICE_X30Y85 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0
|
|
SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=2, routed) 3.465 9.315 ext_ram_data_IOBUF[31]_inst/I
|
|
AC23 r ext_ram_data_IOBUF[31]_inst/OBUFT/I
|
|
AC23 OBUFT (Prop_obuft_I_O) 3.585 12.900 r ext_ram_data_IOBUF[31]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.900 ext_ram_data[31]
|
|
AC23 r ext_ram_data[31] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.900
|
|
-------------------------------------------------------------------
|
|
slack 0.422
|
|
|
|
Slack (MET) : 0.422ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[31]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.308ns (logic 5.033ns (32.879%) route 10.275ns (67.121%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3
|
|
SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0
|
|
SLICE_X22Y86 f u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0
|
|
SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O
|
|
net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31]
|
|
SLICE_X24Y84 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0
|
|
SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O
|
|
net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0
|
|
SLICE_X24Y83 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4
|
|
SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O
|
|
net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31]
|
|
SLICE_X27Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5
|
|
SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O
|
|
net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31]
|
|
SLICE_X30Y85 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0
|
|
SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=2, routed) 3.465 9.315 ext_ram_data_IOBUF[31]_inst/I
|
|
AC23 r ext_ram_data_IOBUF[31]_inst/OBUFT/I
|
|
AC23 OBUFT (Prop_obuft_I_O) 3.585 12.900 r ext_ram_data_IOBUF[31]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.900 ext_ram_data[31]
|
|
AC23 r ext_ram_data[31] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.900
|
|
-------------------------------------------------------------------
|
|
slack 0.422
|
|
|
|
Slack (MET) : 0.422ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[31]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.308ns (logic 5.033ns (32.879%) route 10.275ns (67.121%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3
|
|
SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0
|
|
SLICE_X22Y86 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0
|
|
SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.124 2.572 f u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O
|
|
net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31]
|
|
SLICE_X24Y84 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0
|
|
SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O
|
|
net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0
|
|
SLICE_X24Y83 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4
|
|
SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O
|
|
net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31]
|
|
SLICE_X27Y83 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5
|
|
SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O
|
|
net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31]
|
|
SLICE_X30Y85 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0
|
|
SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=2, routed) 3.465 9.315 ext_ram_data_IOBUF[31]_inst/I
|
|
AC23 f ext_ram_data_IOBUF[31]_inst/OBUFT/I
|
|
AC23 OBUFT (Prop_obuft_I_O) 3.585 12.900 f ext_ram_data_IOBUF[31]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.900 ext_ram_data[31]
|
|
AC23 f ext_ram_data[31] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.900
|
|
-------------------------------------------------------------------
|
|
slack 0.422
|
|
|
|
Slack (MET) : 0.422ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[31]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.308ns (logic 5.033ns (32.879%) route 10.275ns (67.121%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3
|
|
SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0
|
|
SLICE_X22Y86 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0
|
|
SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.124 2.572 f u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O
|
|
net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31]
|
|
SLICE_X24Y84 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0
|
|
SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O
|
|
net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0
|
|
SLICE_X24Y83 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4
|
|
SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O
|
|
net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31]
|
|
SLICE_X27Y83 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5
|
|
SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O
|
|
net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31]
|
|
SLICE_X30Y85 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0
|
|
SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=2, routed) 3.465 9.315 ext_ram_data_IOBUF[31]_inst/I
|
|
AC23 f ext_ram_data_IOBUF[31]_inst/OBUFT/I
|
|
AC23 OBUFT (Prop_obuft_I_O) 3.585 12.900 f ext_ram_data_IOBUF[31]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.900 ext_ram_data[31]
|
|
AC23 f ext_ram_data[31] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.900
|
|
-------------------------------------------------------------------
|
|
slack 0.422
|
|
|
|
Slack (MET) : 0.443ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[6]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.287ns (logic 5.138ns (33.611%) route 10.149ns (66.389%))
|
|
Logic Levels: 8 (LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3
|
|
SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=136, routed) 1.551 2.641 u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/ADDRB0
|
|
SLICE_X36Y83 r u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/RADR0
|
|
SLICE_X36Y83 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.152 2.793 r u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/O
|
|
net (fo=1, routed) 1.421 4.214 u_matmul_axi_slave/ep_rd_c1[38]
|
|
SLICE_X23Y79 r u_matmul_axi_slave/ram_reg_i_46/I3
|
|
SLICE_X23Y79 LUT5 (Prop_lut5_I3_O) 0.348 4.562 r u_matmul_axi_slave/ram_reg_i_46/O
|
|
net (fo=1, routed) 0.461 5.023 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[6]
|
|
SLICE_X19Y79 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/I5
|
|
SLICE_X19Y79 LUT6 (Prop_lut6_I5_O) 0.124 5.147 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/O
|
|
net (fo=4, routed) 0.529 5.676 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1
|
|
SLICE_X12Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/I0
|
|
SLICE_X12Y76 LUT3 (Prop_lut3_I0_O) 0.124 5.800 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/O
|
|
net (fo=2, routed) 3.517 9.317 ext_ram_data_IOBUF[6]_inst/I
|
|
AE20 r ext_ram_data_IOBUF[6]_inst/OBUFT/I
|
|
AE20 OBUFT (Prop_obuft_I_O) 3.562 12.879 r ext_ram_data_IOBUF[6]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.879 ext_ram_data[6]
|
|
AE20 r ext_ram_data[6] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.879
|
|
-------------------------------------------------------------------
|
|
slack 0.443
|
|
|
|
Slack (MET) : 0.443ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[6]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.287ns (logic 5.138ns (33.611%) route 10.149ns (66.389%))
|
|
Logic Levels: 8 (LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3
|
|
SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=136, routed) 1.551 2.641 u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/ADDRB0
|
|
SLICE_X36Y83 r u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/RADR0
|
|
SLICE_X36Y83 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.152 2.793 r u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/O
|
|
net (fo=1, routed) 1.421 4.214 u_matmul_axi_slave/ep_rd_c1[38]
|
|
SLICE_X23Y79 r u_matmul_axi_slave/ram_reg_i_46/I3
|
|
SLICE_X23Y79 LUT5 (Prop_lut5_I3_O) 0.348 4.562 r u_matmul_axi_slave/ram_reg_i_46/O
|
|
net (fo=1, routed) 0.461 5.023 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[6]
|
|
SLICE_X19Y79 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/I5
|
|
SLICE_X19Y79 LUT6 (Prop_lut6_I5_O) 0.124 5.147 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/O
|
|
net (fo=4, routed) 0.529 5.676 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1
|
|
SLICE_X12Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/I0
|
|
SLICE_X12Y76 LUT3 (Prop_lut3_I0_O) 0.124 5.800 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/O
|
|
net (fo=2, routed) 3.517 9.317 ext_ram_data_IOBUF[6]_inst/I
|
|
AE20 r ext_ram_data_IOBUF[6]_inst/OBUFT/I
|
|
AE20 OBUFT (Prop_obuft_I_O) 3.562 12.879 r ext_ram_data_IOBUF[6]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.879 ext_ram_data[6]
|
|
AE20 r ext_ram_data[6] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.879
|
|
-------------------------------------------------------------------
|
|
slack 0.443
|
|
|
|
Slack (MET) : 0.475ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.176ns (logic 6.904ns (45.493%) route 8.272ns (54.507%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.488 9.283 base_ram_data_IOBUF[1]_inst/T
|
|
L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T
|
|
L25 OBUFT (TriStatE_obuft_T_O)
|
|
3.564 12.847 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.847 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.847
|
|
-------------------------------------------------------------------
|
|
slack 0.475
|
|
|
|
Slack (MET) : 0.475ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.176ns (logic 6.904ns (45.493%) route 8.272ns (54.507%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.488 9.283 base_ram_data_IOBUF[1]_inst/T
|
|
L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T
|
|
L25 OBUFT (TriStatE_obuft_T_O)
|
|
3.564 12.847 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.847 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.847
|
|
-------------------------------------------------------------------
|
|
slack 0.475
|
|
|
|
Slack (MET) : 0.475ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.176ns (logic 6.904ns (45.493%) route 8.272ns (54.507%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.488 9.283 base_ram_data_IOBUF[1]_inst/T
|
|
L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T
|
|
L25 OBUFT (TriStatE_obuft_T_O)
|
|
3.564 12.847 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.847 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.847
|
|
-------------------------------------------------------------------
|
|
slack 0.475
|
|
|
|
Slack (MET) : 0.475ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.176ns (logic 6.904ns (45.493%) route 8.272ns (54.507%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.488 9.283 base_ram_data_IOBUF[1]_inst/T
|
|
L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T
|
|
L25 OBUFT (TriStatE_obuft_T_O)
|
|
3.564 12.847 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.847 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.847
|
|
-------------------------------------------------------------------
|
|
slack 0.475
|
|
|
|
Slack (MET) : 0.475ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.176ns (logic 6.904ns (45.493%) route 8.272ns (54.507%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.488 9.283 base_ram_data_IOBUF[1]_inst/T
|
|
L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T
|
|
L25 OBUFT (TriStatE_obuft_T_O)
|
|
3.564 12.847 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.847 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.847
|
|
-------------------------------------------------------------------
|
|
slack 0.475
|
|
|
|
Slack (MET) : 0.475ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.176ns (logic 6.904ns (45.493%) route 8.272ns (54.507%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.488 9.283 base_ram_data_IOBUF[1]_inst/T
|
|
L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T
|
|
L25 OBUFT (TriStatE_obuft_T_O)
|
|
3.564 12.847 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.847 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.847
|
|
-------------------------------------------------------------------
|
|
slack 0.475
|
|
|
|
Slack (MET) : 0.475ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.176ns (logic 6.904ns (45.493%) route 8.272ns (54.507%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.488 9.283 base_ram_data_IOBUF[1]_inst/T
|
|
L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T
|
|
L25 OBUFT (TriStatE_obuft_T_O)
|
|
3.564 12.847 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.847 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.847
|
|
-------------------------------------------------------------------
|
|
slack 0.475
|
|
|
|
Slack (MET) : 0.475ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.176ns (logic 6.904ns (45.493%) route 8.272ns (54.507%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.488 9.283 base_ram_data_IOBUF[1]_inst/T
|
|
L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T
|
|
L25 OBUFT (TriStatE_obuft_T_O)
|
|
3.564 12.847 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.847 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.847
|
|
-------------------------------------------------------------------
|
|
slack 0.475
|
|
|
|
Slack (MET) : 0.475ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.176ns (logic 6.904ns (45.493%) route 8.272ns (54.507%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.488 9.283 base_ram_data_IOBUF[1]_inst/T
|
|
L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T
|
|
L25 OBUFT (TriStatE_obuft_T_O)
|
|
3.564 12.847 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.847 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.847
|
|
-------------------------------------------------------------------
|
|
slack 0.475
|
|
|
|
Slack (MET) : 0.475ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.176ns (logic 6.904ns (45.493%) route 8.272ns (54.507%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.488 9.283 base_ram_data_IOBUF[1]_inst/T
|
|
L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T
|
|
L25 OBUFT (TriStatE_obuft_T_O)
|
|
3.564 12.847 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.847 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.847
|
|
-------------------------------------------------------------------
|
|
slack 0.475
|
|
|
|
Slack (MET) : 0.483ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[31]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.247ns (logic 4.979ns (32.656%) route 10.268ns (67.344%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3
|
|
SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0
|
|
SLICE_X22Y86 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0
|
|
SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O
|
|
net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31]
|
|
SLICE_X24Y84 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0
|
|
SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O
|
|
net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0
|
|
SLICE_X24Y83 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4
|
|
SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O
|
|
net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31]
|
|
SLICE_X27Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5
|
|
SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O
|
|
net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31]
|
|
SLICE_X30Y85 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0
|
|
SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=2, routed) 3.458 9.308 base_ram_data_IOBUF[31]_inst/I
|
|
M22 r base_ram_data_IOBUF[31]_inst/OBUFT/I
|
|
M22 OBUFT (Prop_obuft_I_O) 3.531 12.839 r base_ram_data_IOBUF[31]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.839 base_ram_data[31]
|
|
M22 r base_ram_data[31] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.839
|
|
-------------------------------------------------------------------
|
|
slack 0.483
|
|
|
|
Slack (MET) : 0.483ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[31]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.247ns (logic 4.979ns (32.656%) route 10.268ns (67.344%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3
|
|
SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0
|
|
SLICE_X22Y86 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0
|
|
SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O
|
|
net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31]
|
|
SLICE_X24Y84 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0
|
|
SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O
|
|
net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0
|
|
SLICE_X24Y83 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4
|
|
SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O
|
|
net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31]
|
|
SLICE_X27Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5
|
|
SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O
|
|
net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31]
|
|
SLICE_X30Y85 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0
|
|
SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=2, routed) 3.458 9.308 base_ram_data_IOBUF[31]_inst/I
|
|
M22 r base_ram_data_IOBUF[31]_inst/OBUFT/I
|
|
M22 OBUFT (Prop_obuft_I_O) 3.531 12.839 r base_ram_data_IOBUF[31]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.839 base_ram_data[31]
|
|
M22 r base_ram_data[31] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.839
|
|
-------------------------------------------------------------------
|
|
slack 0.483
|
|
|
|
Slack (MET) : 0.483ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[31]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.247ns (logic 4.979ns (32.656%) route 10.268ns (67.344%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3
|
|
SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0
|
|
SLICE_X22Y86 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0
|
|
SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O
|
|
net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31]
|
|
SLICE_X24Y84 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0
|
|
SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O
|
|
net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0
|
|
SLICE_X24Y83 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4
|
|
SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O
|
|
net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31]
|
|
SLICE_X27Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5
|
|
SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O
|
|
net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31]
|
|
SLICE_X30Y85 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0
|
|
SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=2, routed) 3.458 9.308 base_ram_data_IOBUF[31]_inst/I
|
|
M22 r base_ram_data_IOBUF[31]_inst/OBUFT/I
|
|
M22 OBUFT (Prop_obuft_I_O) 3.531 12.839 r base_ram_data_IOBUF[31]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.839 base_ram_data[31]
|
|
M22 r base_ram_data[31] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.839
|
|
-------------------------------------------------------------------
|
|
slack 0.483
|
|
|
|
Slack (MET) : 0.483ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[31]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.247ns (logic 4.979ns (32.656%) route 10.268ns (67.344%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3
|
|
SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0
|
|
SLICE_X22Y86 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0
|
|
SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O
|
|
net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31]
|
|
SLICE_X24Y84 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0
|
|
SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O
|
|
net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0
|
|
SLICE_X24Y83 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4
|
|
SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O
|
|
net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31]
|
|
SLICE_X27Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5
|
|
SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O
|
|
net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31]
|
|
SLICE_X30Y85 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0
|
|
SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=2, routed) 3.458 9.308 base_ram_data_IOBUF[31]_inst/I
|
|
M22 r base_ram_data_IOBUF[31]_inst/OBUFT/I
|
|
M22 OBUFT (Prop_obuft_I_O) 3.531 12.839 r base_ram_data_IOBUF[31]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.839 base_ram_data[31]
|
|
M22 r base_ram_data[31] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.839
|
|
-------------------------------------------------------------------
|
|
slack 0.483
|
|
|
|
Slack (MET) : 0.483ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[31]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.247ns (logic 4.979ns (32.656%) route 10.268ns (67.344%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3
|
|
SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0
|
|
SLICE_X22Y86 f u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0
|
|
SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O
|
|
net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31]
|
|
SLICE_X24Y84 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0
|
|
SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O
|
|
net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0
|
|
SLICE_X24Y83 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4
|
|
SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O
|
|
net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31]
|
|
SLICE_X27Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5
|
|
SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O
|
|
net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31]
|
|
SLICE_X30Y85 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0
|
|
SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=2, routed) 3.458 9.308 base_ram_data_IOBUF[31]_inst/I
|
|
M22 r base_ram_data_IOBUF[31]_inst/OBUFT/I
|
|
M22 OBUFT (Prop_obuft_I_O) 3.531 12.839 r base_ram_data_IOBUF[31]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.839 base_ram_data[31]
|
|
M22 r base_ram_data[31] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.839
|
|
-------------------------------------------------------------------
|
|
slack 0.483
|
|
|
|
Slack (MET) : 0.483ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[31]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.247ns (logic 4.979ns (32.656%) route 10.268ns (67.344%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3
|
|
SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0
|
|
SLICE_X22Y86 f u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0
|
|
SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O
|
|
net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31]
|
|
SLICE_X24Y84 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0
|
|
SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O
|
|
net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0
|
|
SLICE_X24Y83 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4
|
|
SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O
|
|
net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31]
|
|
SLICE_X27Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5
|
|
SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O
|
|
net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31]
|
|
SLICE_X30Y85 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0
|
|
SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=2, routed) 3.458 9.308 base_ram_data_IOBUF[31]_inst/I
|
|
M22 r base_ram_data_IOBUF[31]_inst/OBUFT/I
|
|
M22 OBUFT (Prop_obuft_I_O) 3.531 12.839 r base_ram_data_IOBUF[31]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.839 base_ram_data[31]
|
|
M22 r base_ram_data[31] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.839
|
|
-------------------------------------------------------------------
|
|
slack 0.483
|
|
|
|
Slack (MET) : 0.483ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[31]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.247ns (logic 4.979ns (32.656%) route 10.268ns (67.344%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3
|
|
SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0
|
|
SLICE_X22Y86 f u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0
|
|
SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O
|
|
net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31]
|
|
SLICE_X24Y84 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0
|
|
SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O
|
|
net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0
|
|
SLICE_X24Y83 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4
|
|
SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O
|
|
net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31]
|
|
SLICE_X27Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5
|
|
SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O
|
|
net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31]
|
|
SLICE_X30Y85 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0
|
|
SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=2, routed) 3.458 9.308 base_ram_data_IOBUF[31]_inst/I
|
|
M22 r base_ram_data_IOBUF[31]_inst/OBUFT/I
|
|
M22 OBUFT (Prop_obuft_I_O) 3.531 12.839 r base_ram_data_IOBUF[31]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.839 base_ram_data[31]
|
|
M22 r base_ram_data[31] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.839
|
|
-------------------------------------------------------------------
|
|
slack 0.483
|
|
|
|
Slack (MET) : 0.483ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[31]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.247ns (logic 4.979ns (32.656%) route 10.268ns (67.344%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3
|
|
SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0
|
|
SLICE_X22Y86 f u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0
|
|
SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O
|
|
net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31]
|
|
SLICE_X24Y84 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0
|
|
SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O
|
|
net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0
|
|
SLICE_X24Y83 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4
|
|
SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O
|
|
net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31]
|
|
SLICE_X27Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5
|
|
SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O
|
|
net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31]
|
|
SLICE_X30Y85 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0
|
|
SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=2, routed) 3.458 9.308 base_ram_data_IOBUF[31]_inst/I
|
|
M22 r base_ram_data_IOBUF[31]_inst/OBUFT/I
|
|
M22 OBUFT (Prop_obuft_I_O) 3.531 12.839 r base_ram_data_IOBUF[31]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.839 base_ram_data[31]
|
|
M22 r base_ram_data[31] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.839
|
|
-------------------------------------------------------------------
|
|
slack 0.483
|
|
|
|
Slack (MET) : 0.483ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[31]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.247ns (logic 4.979ns (32.656%) route 10.268ns (67.344%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3
|
|
SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0
|
|
SLICE_X22Y86 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0
|
|
SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.124 2.572 f u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O
|
|
net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31]
|
|
SLICE_X24Y84 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0
|
|
SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O
|
|
net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0
|
|
SLICE_X24Y83 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4
|
|
SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O
|
|
net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31]
|
|
SLICE_X27Y83 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5
|
|
SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O
|
|
net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31]
|
|
SLICE_X30Y85 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0
|
|
SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=2, routed) 3.458 9.308 base_ram_data_IOBUF[31]_inst/I
|
|
M22 f base_ram_data_IOBUF[31]_inst/OBUFT/I
|
|
M22 OBUFT (Prop_obuft_I_O) 3.531 12.839 f base_ram_data_IOBUF[31]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.839 base_ram_data[31]
|
|
M22 f base_ram_data[31] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.839
|
|
-------------------------------------------------------------------
|
|
slack 0.483
|
|
|
|
Slack (MET) : 0.483ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[31]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.247ns (logic 4.979ns (32.656%) route 10.268ns (67.344%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.868ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.408ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.868 -2.408
|
|
SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C
|
|
SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q
|
|
net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6]
|
|
SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0
|
|
SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O
|
|
net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6]
|
|
SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2
|
|
SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O
|
|
net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]
|
|
SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3
|
|
SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0
|
|
SLICE_X22Y86 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0
|
|
SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.124 2.572 f u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O
|
|
net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31]
|
|
SLICE_X24Y84 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0
|
|
SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O
|
|
net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0
|
|
SLICE_X24Y83 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4
|
|
SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O
|
|
net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31]
|
|
SLICE_X27Y83 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5
|
|
SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O
|
|
net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31]
|
|
SLICE_X30Y85 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0
|
|
SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=2, routed) 3.458 9.308 base_ram_data_IOBUF[31]_inst/I
|
|
M22 f base_ram_data_IOBUF[31]_inst/OBUFT/I
|
|
M22 OBUFT (Prop_obuft_I_O) 3.531 12.839 f base_ram_data_IOBUF[31]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.839 base_ram_data[31]
|
|
M22 f base_ram_data[31] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.839
|
|
-------------------------------------------------------------------
|
|
slack 0.483
|
|
|
|
Slack (MET) : 0.489ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[19]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.161ns (logic 6.897ns (45.492%) route 8.264ns (54.508%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.599 9.276 ext_ram_data_IOBUF[19]_inst/T
|
|
AC18 f ext_ram_data_IOBUF[19]_inst/OBUFT/T
|
|
AC18 OBUFT (TriStatE_obuft_T_O)
|
|
3.557 12.833 r ext_ram_data_IOBUF[19]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.833 ext_ram_data[19]
|
|
AC18 r ext_ram_data[19] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.833
|
|
-------------------------------------------------------------------
|
|
slack 0.489
|
|
|
|
Slack (MET) : 0.489ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[19]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.161ns (logic 6.897ns (45.492%) route 8.264ns (54.508%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.599 9.276 ext_ram_data_IOBUF[19]_inst/T
|
|
AC18 f ext_ram_data_IOBUF[19]_inst/OBUFT/T
|
|
AC18 OBUFT (TriStatE_obuft_T_O)
|
|
3.557 12.833 r ext_ram_data_IOBUF[19]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.833 ext_ram_data[19]
|
|
AC18 r ext_ram_data[19] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.833
|
|
-------------------------------------------------------------------
|
|
slack 0.489
|
|
|
|
Slack (MET) : 0.489ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[19]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.161ns (logic 6.897ns (45.492%) route 8.264ns (54.508%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.599 9.276 ext_ram_data_IOBUF[19]_inst/T
|
|
AC18 f ext_ram_data_IOBUF[19]_inst/OBUFT/T
|
|
AC18 OBUFT (TriStatE_obuft_T_O)
|
|
3.557 12.833 r ext_ram_data_IOBUF[19]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.833 ext_ram_data[19]
|
|
AC18 r ext_ram_data[19] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.833
|
|
-------------------------------------------------------------------
|
|
slack 0.489
|
|
|
|
Slack (MET) : 0.489ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[19]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.161ns (logic 6.897ns (45.492%) route 8.264ns (54.508%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.599 9.276 ext_ram_data_IOBUF[19]_inst/T
|
|
AC18 f ext_ram_data_IOBUF[19]_inst/OBUFT/T
|
|
AC18 OBUFT (TriStatE_obuft_T_O)
|
|
3.557 12.833 r ext_ram_data_IOBUF[19]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.833 ext_ram_data[19]
|
|
AC18 r ext_ram_data[19] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.833
|
|
-------------------------------------------------------------------
|
|
slack 0.489
|
|
|
|
Slack (MET) : 0.489ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[19]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.161ns (logic 6.897ns (45.492%) route 8.264ns (54.508%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.599 9.276 ext_ram_data_IOBUF[19]_inst/T
|
|
AC18 f ext_ram_data_IOBUF[19]_inst/OBUFT/T
|
|
AC18 OBUFT (TriStatE_obuft_T_O)
|
|
3.557 12.833 r ext_ram_data_IOBUF[19]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.833 ext_ram_data[19]
|
|
AC18 r ext_ram_data[19] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.833
|
|
-------------------------------------------------------------------
|
|
slack 0.489
|
|
|
|
Slack (MET) : 0.489ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[19]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.161ns (logic 6.897ns (45.492%) route 8.264ns (54.508%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.599 9.276 ext_ram_data_IOBUF[19]_inst/T
|
|
AC18 f ext_ram_data_IOBUF[19]_inst/OBUFT/T
|
|
AC18 OBUFT (TriStatE_obuft_T_O)
|
|
3.557 12.833 r ext_ram_data_IOBUF[19]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.833 ext_ram_data[19]
|
|
AC18 r ext_ram_data[19] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.833
|
|
-------------------------------------------------------------------
|
|
slack 0.489
|
|
|
|
Slack (MET) : 0.489ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[19]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.161ns (logic 6.897ns (45.492%) route 8.264ns (54.508%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.599 9.276 ext_ram_data_IOBUF[19]_inst/T
|
|
AC18 f ext_ram_data_IOBUF[19]_inst/OBUFT/T
|
|
AC18 OBUFT (TriStatE_obuft_T_O)
|
|
3.557 12.833 r ext_ram_data_IOBUF[19]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.833 ext_ram_data[19]
|
|
AC18 r ext_ram_data[19] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.833
|
|
-------------------------------------------------------------------
|
|
slack 0.489
|
|
|
|
Slack (MET) : 0.489ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[19]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.161ns (logic 6.897ns (45.492%) route 8.264ns (54.508%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.599 9.276 ext_ram_data_IOBUF[19]_inst/T
|
|
AC18 f ext_ram_data_IOBUF[19]_inst/OBUFT/T
|
|
AC18 OBUFT (TriStatE_obuft_T_O)
|
|
3.557 12.833 r ext_ram_data_IOBUF[19]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.833 ext_ram_data[19]
|
|
AC18 r ext_ram_data[19] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.833
|
|
-------------------------------------------------------------------
|
|
slack 0.489
|
|
|
|
Slack (MET) : 0.489ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[19]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.161ns (logic 6.897ns (45.492%) route 8.264ns (54.508%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.599 9.276 ext_ram_data_IOBUF[19]_inst/T
|
|
AC18 f ext_ram_data_IOBUF[19]_inst/OBUFT/T
|
|
AC18 OBUFT (TriStatE_obuft_T_O)
|
|
3.557 12.833 r ext_ram_data_IOBUF[19]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.833 ext_ram_data[19]
|
|
AC18 r ext_ram_data[19] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.833
|
|
-------------------------------------------------------------------
|
|
slack 0.489
|
|
|
|
Slack (MET) : 0.489ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[19]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.161ns (logic 6.897ns (45.492%) route 8.264ns (54.508%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.599 9.276 ext_ram_data_IOBUF[19]_inst/T
|
|
AC18 f ext_ram_data_IOBUF[19]_inst/OBUFT/T
|
|
AC18 OBUFT (TriStatE_obuft_T_O)
|
|
3.557 12.833 r ext_ram_data_IOBUF[19]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.833 ext_ram_data[19]
|
|
AC18 r ext_ram_data[19] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.833
|
|
-------------------------------------------------------------------
|
|
slack 0.489
|
|
|
|
Slack (MET) : 0.508ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[23]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.143ns (logic 6.882ns (45.449%) route 8.261ns (54.551%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.595 9.272 ext_ram_data_IOBUF[23]_inst/T
|
|
AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T
|
|
AA15 OBUFT (TriStatE_obuft_T_O)
|
|
3.542 12.815 r ext_ram_data_IOBUF[23]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.815 ext_ram_data[23]
|
|
AA15 r ext_ram_data[23] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.815
|
|
-------------------------------------------------------------------
|
|
slack 0.508
|
|
|
|
Slack (MET) : 0.508ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[23]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.143ns (logic 6.882ns (45.449%) route 8.261ns (54.551%))
|
|
Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.947ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.329ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.947 -2.329
|
|
SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C
|
|
SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q
|
|
net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4]
|
|
SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4
|
|
SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O
|
|
net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0
|
|
SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0
|
|
SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O
|
|
net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10]
|
|
SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0]
|
|
SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.595 9.272 ext_ram_data_IOBUF[23]_inst/T
|
|
AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T
|
|
AA15 OBUFT (TriStatE_obuft_T_O)
|
|
3.542 12.815 r ext_ram_data_IOBUF[23]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.815 ext_ram_data[23]
|
|
AA15 r ext_ram_data[23] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.102 13.622
|
|
output delay -0.300 13.322
|
|
-------------------------------------------------------------------
|
|
required time 13.322
|
|
arrival time -12.815
|
|
-------------------------------------------------------------------
|
|
slack 0.508
|
|
|
|
Slack (MET) : 0.737ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.089ns (logic 8.012ns (27.543%) route 21.077ns (72.457%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2
|
|
SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O
|
|
net (fo=20, routed) 0.677 24.234 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2
|
|
SLICE_X117Y153 f u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/I2
|
|
SLICE_X117Y153 LUT6 (Prop_lut6_I2_O) 0.332 24.566 r u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/O
|
|
net (fo=1, routed) 0.909 25.475 u_cpu/id_stage/ds_to_es_bus_r_reg[189]_2
|
|
SLICE_X113Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/I3
|
|
SLICE_X113Y158 LUT4 (Prop_lut4_I3_O) 0.124 25.599 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/O
|
|
net (fo=1, routed) 0.715 26.314 u_cpu/id_stage/ds_to_es_bus_r[189]_i_5_n_0
|
|
SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/I4
|
|
SLICE_X112Y158 LUT6 (Prop_lut6_I4_O) 0.124 26.438 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/O
|
|
net (fo=1, routed) 0.000 26.438 u_cpu/exe_stage/ds_to_es_bus[139]
|
|
SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.079 27.175 u_cpu/exe_stage/ds_to_es_bus_r_reg[189]
|
|
-------------------------------------------------------------------
|
|
required time 27.175
|
|
arrival time -26.438
|
|
-------------------------------------------------------------------
|
|
slack 0.737
|
|
|
|
Slack (MET) : 0.737ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.089ns (logic 8.012ns (27.543%) route 21.077ns (72.457%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2
|
|
SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O
|
|
net (fo=20, routed) 0.677 24.234 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2
|
|
SLICE_X117Y153 f u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/I2
|
|
SLICE_X117Y153 LUT6 (Prop_lut6_I2_O) 0.332 24.566 r u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/O
|
|
net (fo=1, routed) 0.909 25.475 u_cpu/id_stage/ds_to_es_bus_r_reg[189]_2
|
|
SLICE_X113Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/I3
|
|
SLICE_X113Y158 LUT4 (Prop_lut4_I3_O) 0.124 25.599 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/O
|
|
net (fo=1, routed) 0.715 26.314 u_cpu/id_stage/ds_to_es_bus_r[189]_i_5_n_0
|
|
SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/I4
|
|
SLICE_X112Y158 LUT6 (Prop_lut6_I4_O) 0.124 26.438 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/O
|
|
net (fo=1, routed) 0.000 26.438 u_cpu/exe_stage/ds_to_es_bus[139]
|
|
SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.079 27.175 u_cpu/exe_stage/ds_to_es_bus_r_reg[189]
|
|
-------------------------------------------------------------------
|
|
required time 27.175
|
|
arrival time -26.438
|
|
-------------------------------------------------------------------
|
|
slack 0.737
|
|
|
|
Slack (MET) : 0.737ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.089ns (logic 8.012ns (27.543%) route 21.077ns (72.457%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2
|
|
SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O
|
|
net (fo=20, routed) 0.677 24.234 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2
|
|
SLICE_X117Y153 f u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/I2
|
|
SLICE_X117Y153 LUT6 (Prop_lut6_I2_O) 0.332 24.566 r u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/O
|
|
net (fo=1, routed) 0.909 25.475 u_cpu/id_stage/ds_to_es_bus_r_reg[189]_2
|
|
SLICE_X113Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/I3
|
|
SLICE_X113Y158 LUT4 (Prop_lut4_I3_O) 0.124 25.599 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/O
|
|
net (fo=1, routed) 0.715 26.314 u_cpu/id_stage/ds_to_es_bus_r[189]_i_5_n_0
|
|
SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/I4
|
|
SLICE_X112Y158 LUT6 (Prop_lut6_I4_O) 0.124 26.438 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/O
|
|
net (fo=1, routed) 0.000 26.438 u_cpu/exe_stage/ds_to_es_bus[139]
|
|
SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.079 27.175 u_cpu/exe_stage/ds_to_es_bus_r_reg[189]
|
|
-------------------------------------------------------------------
|
|
required time 27.175
|
|
arrival time -26.438
|
|
-------------------------------------------------------------------
|
|
slack 0.737
|
|
|
|
Slack (MET) : 0.737ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.089ns (logic 8.012ns (27.543%) route 21.077ns (72.457%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2
|
|
SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O
|
|
net (fo=20, routed) 0.677 24.234 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2
|
|
SLICE_X117Y153 f u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/I2
|
|
SLICE_X117Y153 LUT6 (Prop_lut6_I2_O) 0.332 24.566 r u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/O
|
|
net (fo=1, routed) 0.909 25.475 u_cpu/id_stage/ds_to_es_bus_r_reg[189]_2
|
|
SLICE_X113Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/I3
|
|
SLICE_X113Y158 LUT4 (Prop_lut4_I3_O) 0.124 25.599 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/O
|
|
net (fo=1, routed) 0.715 26.314 u_cpu/id_stage/ds_to_es_bus_r[189]_i_5_n_0
|
|
SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/I4
|
|
SLICE_X112Y158 LUT6 (Prop_lut6_I4_O) 0.124 26.438 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/O
|
|
net (fo=1, routed) 0.000 26.438 u_cpu/exe_stage/ds_to_es_bus[139]
|
|
SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.079 27.175 u_cpu/exe_stage/ds_to_es_bus_r_reg[189]
|
|
-------------------------------------------------------------------
|
|
required time 27.175
|
|
arrival time -26.438
|
|
-------------------------------------------------------------------
|
|
slack 0.737
|
|
|
|
Slack (MET) : 0.737ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.089ns (logic 8.012ns (27.543%) route 21.077ns (72.457%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2
|
|
SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O
|
|
net (fo=20, routed) 0.677 24.234 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2
|
|
SLICE_X117Y153 f u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/I2
|
|
SLICE_X117Y153 LUT6 (Prop_lut6_I2_O) 0.332 24.566 r u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/O
|
|
net (fo=1, routed) 0.909 25.475 u_cpu/id_stage/ds_to_es_bus_r_reg[189]_2
|
|
SLICE_X113Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/I3
|
|
SLICE_X113Y158 LUT4 (Prop_lut4_I3_O) 0.124 25.599 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/O
|
|
net (fo=1, routed) 0.715 26.314 u_cpu/id_stage/ds_to_es_bus_r[189]_i_5_n_0
|
|
SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/I4
|
|
SLICE_X112Y158 LUT6 (Prop_lut6_I4_O) 0.124 26.438 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/O
|
|
net (fo=1, routed) 0.000 26.438 u_cpu/exe_stage/ds_to_es_bus[139]
|
|
SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.079 27.175 u_cpu/exe_stage/ds_to_es_bus_r_reg[189]
|
|
-------------------------------------------------------------------
|
|
required time 27.175
|
|
arrival time -26.438
|
|
-------------------------------------------------------------------
|
|
slack 0.737
|
|
|
|
Slack (MET) : 0.737ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.089ns (logic 8.012ns (27.543%) route 21.077ns (72.457%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2
|
|
SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O
|
|
net (fo=20, routed) 0.677 24.234 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2
|
|
SLICE_X117Y153 f u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/I2
|
|
SLICE_X117Y153 LUT6 (Prop_lut6_I2_O) 0.332 24.566 r u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/O
|
|
net (fo=1, routed) 0.909 25.475 u_cpu/id_stage/ds_to_es_bus_r_reg[189]_2
|
|
SLICE_X113Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/I3
|
|
SLICE_X113Y158 LUT4 (Prop_lut4_I3_O) 0.124 25.599 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/O
|
|
net (fo=1, routed) 0.715 26.314 u_cpu/id_stage/ds_to_es_bus_r[189]_i_5_n_0
|
|
SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/I4
|
|
SLICE_X112Y158 LUT6 (Prop_lut6_I4_O) 0.124 26.438 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/O
|
|
net (fo=1, routed) 0.000 26.438 u_cpu/exe_stage/ds_to_es_bus[139]
|
|
SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.079 27.175 u_cpu/exe_stage/ds_to_es_bus_r_reg[189]
|
|
-------------------------------------------------------------------
|
|
required time 27.175
|
|
arrival time -26.438
|
|
-------------------------------------------------------------------
|
|
slack 0.737
|
|
|
|
Slack (MET) : 0.737ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.089ns (logic 8.012ns (27.543%) route 21.077ns (72.457%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2
|
|
SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O
|
|
net (fo=20, routed) 0.677 24.234 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2
|
|
SLICE_X117Y153 f u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/I2
|
|
SLICE_X117Y153 LUT6 (Prop_lut6_I2_O) 0.332 24.566 r u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/O
|
|
net (fo=1, routed) 0.909 25.475 u_cpu/id_stage/ds_to_es_bus_r_reg[189]_2
|
|
SLICE_X113Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/I3
|
|
SLICE_X113Y158 LUT4 (Prop_lut4_I3_O) 0.124 25.599 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/O
|
|
net (fo=1, routed) 0.715 26.314 u_cpu/id_stage/ds_to_es_bus_r[189]_i_5_n_0
|
|
SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/I4
|
|
SLICE_X112Y158 LUT6 (Prop_lut6_I4_O) 0.124 26.438 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/O
|
|
net (fo=1, routed) 0.000 26.438 u_cpu/exe_stage/ds_to_es_bus[139]
|
|
SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.079 27.175 u_cpu/exe_stage/ds_to_es_bus_r_reg[189]
|
|
-------------------------------------------------------------------
|
|
required time 27.175
|
|
arrival time -26.438
|
|
-------------------------------------------------------------------
|
|
slack 0.737
|
|
|
|
Slack (MET) : 0.737ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.089ns (logic 8.012ns (27.543%) route 21.077ns (72.457%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2
|
|
SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O
|
|
net (fo=20, routed) 0.677 24.234 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2
|
|
SLICE_X117Y153 f u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/I2
|
|
SLICE_X117Y153 LUT6 (Prop_lut6_I2_O) 0.332 24.566 r u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/O
|
|
net (fo=1, routed) 0.909 25.475 u_cpu/id_stage/ds_to_es_bus_r_reg[189]_2
|
|
SLICE_X113Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/I3
|
|
SLICE_X113Y158 LUT4 (Prop_lut4_I3_O) 0.124 25.599 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/O
|
|
net (fo=1, routed) 0.715 26.314 u_cpu/id_stage/ds_to_es_bus_r[189]_i_5_n_0
|
|
SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/I4
|
|
SLICE_X112Y158 LUT6 (Prop_lut6_I4_O) 0.124 26.438 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/O
|
|
net (fo=1, routed) 0.000 26.438 u_cpu/exe_stage/ds_to_es_bus[139]
|
|
SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.079 27.175 u_cpu/exe_stage/ds_to_es_bus_r_reg[189]
|
|
-------------------------------------------------------------------
|
|
required time 27.175
|
|
arrival time -26.438
|
|
-------------------------------------------------------------------
|
|
slack 0.737
|
|
|
|
Slack (MET) : 0.737ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.089ns (logic 8.012ns (27.543%) route 21.077ns (72.457%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2
|
|
SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O
|
|
net (fo=20, routed) 0.677 24.234 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2
|
|
SLICE_X117Y153 f u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/I2
|
|
SLICE_X117Y153 LUT6 (Prop_lut6_I2_O) 0.332 24.566 r u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/O
|
|
net (fo=1, routed) 0.909 25.475 u_cpu/id_stage/ds_to_es_bus_r_reg[189]_2
|
|
SLICE_X113Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/I3
|
|
SLICE_X113Y158 LUT4 (Prop_lut4_I3_O) 0.124 25.599 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/O
|
|
net (fo=1, routed) 0.715 26.314 u_cpu/id_stage/ds_to_es_bus_r[189]_i_5_n_0
|
|
SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/I4
|
|
SLICE_X112Y158 LUT6 (Prop_lut6_I4_O) 0.124 26.438 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/O
|
|
net (fo=1, routed) 0.000 26.438 u_cpu/exe_stage/ds_to_es_bus[139]
|
|
SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.079 27.175 u_cpu/exe_stage/ds_to_es_bus_r_reg[189]
|
|
-------------------------------------------------------------------
|
|
required time 27.175
|
|
arrival time -26.438
|
|
-------------------------------------------------------------------
|
|
slack 0.737
|
|
|
|
Slack (MET) : 0.737ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.089ns (logic 8.012ns (27.543%) route 21.077ns (72.457%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2
|
|
SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O
|
|
net (fo=20, routed) 0.677 24.234 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2
|
|
SLICE_X117Y153 f u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/I2
|
|
SLICE_X117Y153 LUT6 (Prop_lut6_I2_O) 0.332 24.566 r u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/O
|
|
net (fo=1, routed) 0.909 25.475 u_cpu/id_stage/ds_to_es_bus_r_reg[189]_2
|
|
SLICE_X113Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/I3
|
|
SLICE_X113Y158 LUT4 (Prop_lut4_I3_O) 0.124 25.599 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/O
|
|
net (fo=1, routed) 0.715 26.314 u_cpu/id_stage/ds_to_es_bus_r[189]_i_5_n_0
|
|
SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/I4
|
|
SLICE_X112Y158 LUT6 (Prop_lut6_I4_O) 0.124 26.438 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/O
|
|
net (fo=1, routed) 0.000 26.438 u_cpu/exe_stage/ds_to_es_bus[139]
|
|
SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.079 27.175 u_cpu/exe_stage/ds_to_es_bus_r_reg[189]
|
|
-------------------------------------------------------------------
|
|
required time 27.175
|
|
arrival time -26.438
|
|
-------------------------------------------------------------------
|
|
slack 0.737
|
|
|
|
Slack (MET) : 0.754ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.021ns (logic 8.005ns (27.583%) route 21.016ns (72.417%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=9 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.143ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.920 23.433 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4
|
|
SLICE_X110Y154 LUT5 (Prop_lut5_I4_O) 0.118 23.551 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O
|
|
net (fo=19, routed) 0.702 24.253 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2_0
|
|
SLICE_X115Y154 f u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/I0
|
|
SLICE_X115Y154 LUT5 (Prop_lut5_I0_O) 0.326 24.579 r u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/O
|
|
net (fo=1, routed) 0.421 25.000 u_cpu/id_stage/ds_to_es_bus_r_reg[193]_6
|
|
SLICE_X114Y152 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/I3
|
|
SLICE_X114Y152 LUT6 (Prop_lut6_I3_O) 0.124 25.124 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/O
|
|
net (fo=1, routed) 1.122 26.246 u_cpu/id_stage/ds_to_es_bus_r[193]_i_2_n_0
|
|
SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/I1
|
|
SLICE_X110Y160 LUT6 (Prop_lut6_I1_O) 0.124 26.370 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/O
|
|
net (fo=1, routed) 0.000 26.370 u_cpu/exe_stage/ds_to_es_bus[143]
|
|
SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.395 27.720
|
|
clock pessimism -0.514 27.207
|
|
clock uncertainty -0.113 27.093
|
|
SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.031 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[193]
|
|
-------------------------------------------------------------------
|
|
required time 27.124
|
|
arrival time -26.370
|
|
-------------------------------------------------------------------
|
|
slack 0.754
|
|
|
|
Slack (MET) : 0.754ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.021ns (logic 8.005ns (27.583%) route 21.016ns (72.417%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=9 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.143ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.920 23.433 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4
|
|
SLICE_X110Y154 LUT5 (Prop_lut5_I4_O) 0.118 23.551 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O
|
|
net (fo=19, routed) 0.702 24.253 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2_0
|
|
SLICE_X115Y154 f u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/I0
|
|
SLICE_X115Y154 LUT5 (Prop_lut5_I0_O) 0.326 24.579 r u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/O
|
|
net (fo=1, routed) 0.421 25.000 u_cpu/id_stage/ds_to_es_bus_r_reg[193]_6
|
|
SLICE_X114Y152 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/I3
|
|
SLICE_X114Y152 LUT6 (Prop_lut6_I3_O) 0.124 25.124 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/O
|
|
net (fo=1, routed) 1.122 26.246 u_cpu/id_stage/ds_to_es_bus_r[193]_i_2_n_0
|
|
SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/I1
|
|
SLICE_X110Y160 LUT6 (Prop_lut6_I1_O) 0.124 26.370 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/O
|
|
net (fo=1, routed) 0.000 26.370 u_cpu/exe_stage/ds_to_es_bus[143]
|
|
SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.395 27.720
|
|
clock pessimism -0.514 27.207
|
|
clock uncertainty -0.113 27.093
|
|
SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.031 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[193]
|
|
-------------------------------------------------------------------
|
|
required time 27.124
|
|
arrival time -26.370
|
|
-------------------------------------------------------------------
|
|
slack 0.754
|
|
|
|
Slack (MET) : 0.754ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.021ns (logic 8.005ns (27.583%) route 21.016ns (72.417%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=9 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.143ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.920 23.433 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4
|
|
SLICE_X110Y154 LUT5 (Prop_lut5_I4_O) 0.118 23.551 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O
|
|
net (fo=19, routed) 0.702 24.253 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2_0
|
|
SLICE_X115Y154 f u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/I0
|
|
SLICE_X115Y154 LUT5 (Prop_lut5_I0_O) 0.326 24.579 r u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/O
|
|
net (fo=1, routed) 0.421 25.000 u_cpu/id_stage/ds_to_es_bus_r_reg[193]_6
|
|
SLICE_X114Y152 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/I3
|
|
SLICE_X114Y152 LUT6 (Prop_lut6_I3_O) 0.124 25.124 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/O
|
|
net (fo=1, routed) 1.122 26.246 u_cpu/id_stage/ds_to_es_bus_r[193]_i_2_n_0
|
|
SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/I1
|
|
SLICE_X110Y160 LUT6 (Prop_lut6_I1_O) 0.124 26.370 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/O
|
|
net (fo=1, routed) 0.000 26.370 u_cpu/exe_stage/ds_to_es_bus[143]
|
|
SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.395 27.720
|
|
clock pessimism -0.514 27.207
|
|
clock uncertainty -0.113 27.093
|
|
SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.031 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[193]
|
|
-------------------------------------------------------------------
|
|
required time 27.124
|
|
arrival time -26.370
|
|
-------------------------------------------------------------------
|
|
slack 0.754
|
|
|
|
Slack (MET) : 0.754ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.021ns (logic 8.005ns (27.583%) route 21.016ns (72.417%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=9 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.143ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.920 23.433 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4
|
|
SLICE_X110Y154 LUT5 (Prop_lut5_I4_O) 0.118 23.551 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O
|
|
net (fo=19, routed) 0.702 24.253 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2_0
|
|
SLICE_X115Y154 f u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/I0
|
|
SLICE_X115Y154 LUT5 (Prop_lut5_I0_O) 0.326 24.579 r u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/O
|
|
net (fo=1, routed) 0.421 25.000 u_cpu/id_stage/ds_to_es_bus_r_reg[193]_6
|
|
SLICE_X114Y152 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/I3
|
|
SLICE_X114Y152 LUT6 (Prop_lut6_I3_O) 0.124 25.124 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/O
|
|
net (fo=1, routed) 1.122 26.246 u_cpu/id_stage/ds_to_es_bus_r[193]_i_2_n_0
|
|
SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/I1
|
|
SLICE_X110Y160 LUT6 (Prop_lut6_I1_O) 0.124 26.370 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/O
|
|
net (fo=1, routed) 0.000 26.370 u_cpu/exe_stage/ds_to_es_bus[143]
|
|
SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.395 27.720
|
|
clock pessimism -0.514 27.207
|
|
clock uncertainty -0.113 27.093
|
|
SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.031 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[193]
|
|
-------------------------------------------------------------------
|
|
required time 27.124
|
|
arrival time -26.370
|
|
-------------------------------------------------------------------
|
|
slack 0.754
|
|
|
|
Slack (MET) : 0.754ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.021ns (logic 8.005ns (27.583%) route 21.016ns (72.417%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=9 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.143ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.920 23.433 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4
|
|
SLICE_X110Y154 LUT5 (Prop_lut5_I4_O) 0.118 23.551 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O
|
|
net (fo=19, routed) 0.702 24.253 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2_0
|
|
SLICE_X115Y154 f u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/I0
|
|
SLICE_X115Y154 LUT5 (Prop_lut5_I0_O) 0.326 24.579 r u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/O
|
|
net (fo=1, routed) 0.421 25.000 u_cpu/id_stage/ds_to_es_bus_r_reg[193]_6
|
|
SLICE_X114Y152 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/I3
|
|
SLICE_X114Y152 LUT6 (Prop_lut6_I3_O) 0.124 25.124 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/O
|
|
net (fo=1, routed) 1.122 26.246 u_cpu/id_stage/ds_to_es_bus_r[193]_i_2_n_0
|
|
SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/I1
|
|
SLICE_X110Y160 LUT6 (Prop_lut6_I1_O) 0.124 26.370 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/O
|
|
net (fo=1, routed) 0.000 26.370 u_cpu/exe_stage/ds_to_es_bus[143]
|
|
SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.395 27.720
|
|
clock pessimism -0.514 27.207
|
|
clock uncertainty -0.113 27.093
|
|
SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.031 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[193]
|
|
-------------------------------------------------------------------
|
|
required time 27.124
|
|
arrival time -26.370
|
|
-------------------------------------------------------------------
|
|
slack 0.754
|
|
|
|
Slack (MET) : 0.754ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.021ns (logic 8.005ns (27.583%) route 21.016ns (72.417%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=9 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.143ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.920 23.433 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4
|
|
SLICE_X110Y154 LUT5 (Prop_lut5_I4_O) 0.118 23.551 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O
|
|
net (fo=19, routed) 0.702 24.253 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2_0
|
|
SLICE_X115Y154 f u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/I0
|
|
SLICE_X115Y154 LUT5 (Prop_lut5_I0_O) 0.326 24.579 r u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/O
|
|
net (fo=1, routed) 0.421 25.000 u_cpu/id_stage/ds_to_es_bus_r_reg[193]_6
|
|
SLICE_X114Y152 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/I3
|
|
SLICE_X114Y152 LUT6 (Prop_lut6_I3_O) 0.124 25.124 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/O
|
|
net (fo=1, routed) 1.122 26.246 u_cpu/id_stage/ds_to_es_bus_r[193]_i_2_n_0
|
|
SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/I1
|
|
SLICE_X110Y160 LUT6 (Prop_lut6_I1_O) 0.124 26.370 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/O
|
|
net (fo=1, routed) 0.000 26.370 u_cpu/exe_stage/ds_to_es_bus[143]
|
|
SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.395 27.720
|
|
clock pessimism -0.514 27.207
|
|
clock uncertainty -0.113 27.093
|
|
SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.031 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[193]
|
|
-------------------------------------------------------------------
|
|
required time 27.124
|
|
arrival time -26.370
|
|
-------------------------------------------------------------------
|
|
slack 0.754
|
|
|
|
Slack (MET) : 0.754ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.021ns (logic 8.005ns (27.583%) route 21.016ns (72.417%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=9 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.143ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.920 23.433 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4
|
|
SLICE_X110Y154 LUT5 (Prop_lut5_I4_O) 0.118 23.551 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O
|
|
net (fo=19, routed) 0.702 24.253 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2_0
|
|
SLICE_X115Y154 f u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/I0
|
|
SLICE_X115Y154 LUT5 (Prop_lut5_I0_O) 0.326 24.579 r u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/O
|
|
net (fo=1, routed) 0.421 25.000 u_cpu/id_stage/ds_to_es_bus_r_reg[193]_6
|
|
SLICE_X114Y152 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/I3
|
|
SLICE_X114Y152 LUT6 (Prop_lut6_I3_O) 0.124 25.124 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/O
|
|
net (fo=1, routed) 1.122 26.246 u_cpu/id_stage/ds_to_es_bus_r[193]_i_2_n_0
|
|
SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/I1
|
|
SLICE_X110Y160 LUT6 (Prop_lut6_I1_O) 0.124 26.370 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/O
|
|
net (fo=1, routed) 0.000 26.370 u_cpu/exe_stage/ds_to_es_bus[143]
|
|
SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.395 27.720
|
|
clock pessimism -0.514 27.207
|
|
clock uncertainty -0.113 27.093
|
|
SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.031 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[193]
|
|
-------------------------------------------------------------------
|
|
required time 27.124
|
|
arrival time -26.370
|
|
-------------------------------------------------------------------
|
|
slack 0.754
|
|
|
|
Slack (MET) : 0.754ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.021ns (logic 8.005ns (27.583%) route 21.016ns (72.417%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=9 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.143ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.920 23.433 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4
|
|
SLICE_X110Y154 LUT5 (Prop_lut5_I4_O) 0.118 23.551 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O
|
|
net (fo=19, routed) 0.702 24.253 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2_0
|
|
SLICE_X115Y154 f u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/I0
|
|
SLICE_X115Y154 LUT5 (Prop_lut5_I0_O) 0.326 24.579 r u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/O
|
|
net (fo=1, routed) 0.421 25.000 u_cpu/id_stage/ds_to_es_bus_r_reg[193]_6
|
|
SLICE_X114Y152 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/I3
|
|
SLICE_X114Y152 LUT6 (Prop_lut6_I3_O) 0.124 25.124 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/O
|
|
net (fo=1, routed) 1.122 26.246 u_cpu/id_stage/ds_to_es_bus_r[193]_i_2_n_0
|
|
SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/I1
|
|
SLICE_X110Y160 LUT6 (Prop_lut6_I1_O) 0.124 26.370 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/O
|
|
net (fo=1, routed) 0.000 26.370 u_cpu/exe_stage/ds_to_es_bus[143]
|
|
SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.395 27.720
|
|
clock pessimism -0.514 27.207
|
|
clock uncertainty -0.113 27.093
|
|
SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.031 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[193]
|
|
-------------------------------------------------------------------
|
|
required time 27.124
|
|
arrival time -26.370
|
|
-------------------------------------------------------------------
|
|
slack 0.754
|
|
|
|
Slack (MET) : 0.754ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.021ns (logic 8.005ns (27.583%) route 21.016ns (72.417%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=9 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.143ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.920 23.433 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4
|
|
SLICE_X110Y154 LUT5 (Prop_lut5_I4_O) 0.118 23.551 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O
|
|
net (fo=19, routed) 0.702 24.253 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2_0
|
|
SLICE_X115Y154 f u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/I0
|
|
SLICE_X115Y154 LUT5 (Prop_lut5_I0_O) 0.326 24.579 r u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/O
|
|
net (fo=1, routed) 0.421 25.000 u_cpu/id_stage/ds_to_es_bus_r_reg[193]_6
|
|
SLICE_X114Y152 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/I3
|
|
SLICE_X114Y152 LUT6 (Prop_lut6_I3_O) 0.124 25.124 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/O
|
|
net (fo=1, routed) 1.122 26.246 u_cpu/id_stage/ds_to_es_bus_r[193]_i_2_n_0
|
|
SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/I1
|
|
SLICE_X110Y160 LUT6 (Prop_lut6_I1_O) 0.124 26.370 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/O
|
|
net (fo=1, routed) 0.000 26.370 u_cpu/exe_stage/ds_to_es_bus[143]
|
|
SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.395 27.720
|
|
clock pessimism -0.514 27.207
|
|
clock uncertainty -0.113 27.093
|
|
SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.031 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[193]
|
|
-------------------------------------------------------------------
|
|
required time 27.124
|
|
arrival time -26.370
|
|
-------------------------------------------------------------------
|
|
slack 0.754
|
|
|
|
Slack (MET) : 0.754ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.021ns (logic 8.005ns (27.583%) route 21.016ns (72.417%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=9 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.143ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.920 23.433 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4
|
|
SLICE_X110Y154 LUT5 (Prop_lut5_I4_O) 0.118 23.551 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O
|
|
net (fo=19, routed) 0.702 24.253 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2_0
|
|
SLICE_X115Y154 f u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/I0
|
|
SLICE_X115Y154 LUT5 (Prop_lut5_I0_O) 0.326 24.579 r u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/O
|
|
net (fo=1, routed) 0.421 25.000 u_cpu/id_stage/ds_to_es_bus_r_reg[193]_6
|
|
SLICE_X114Y152 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/I3
|
|
SLICE_X114Y152 LUT6 (Prop_lut6_I3_O) 0.124 25.124 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/O
|
|
net (fo=1, routed) 1.122 26.246 u_cpu/id_stage/ds_to_es_bus_r[193]_i_2_n_0
|
|
SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/I1
|
|
SLICE_X110Y160 LUT6 (Prop_lut6_I1_O) 0.124 26.370 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/O
|
|
net (fo=1, routed) 0.000 26.370 u_cpu/exe_stage/ds_to_es_bus[143]
|
|
SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.395 27.720
|
|
clock pessimism -0.514 27.207
|
|
clock uncertainty -0.113 27.093
|
|
SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.031 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[193]
|
|
-------------------------------------------------------------------
|
|
required time 27.124
|
|
arrival time -26.370
|
|
-------------------------------------------------------------------
|
|
slack 0.754
|
|
|
|
Slack (MET) : 0.793ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.035ns (logic 7.809ns (26.895%) route 21.226ns (73.105%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1
|
|
SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O
|
|
net (fo=32, routed) 0.967 24.378 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0
|
|
SLICE_X111Y155 f u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/I2
|
|
SLICE_X111Y155 LUT4 (Prop_lut4_I2_O) 0.124 24.502 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/O
|
|
net (fo=1, routed) 0.819 25.321 u_cpu/id_stage/ds_to_es_bus_r[186]_i_11_n_0
|
|
SLICE_X116Y155 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/I3
|
|
SLICE_X116Y155 LUT4 (Prop_lut4_I3_O) 0.124 25.445 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/O
|
|
net (fo=1, routed) 0.815 26.260 u_cpu/id_stage/ds_to_es_bus_r[186]_i_4_n_0
|
|
SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/I3
|
|
SLICE_X112Y158 LUT6 (Prop_lut6_I3_O) 0.124 26.384 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/O
|
|
net (fo=1, routed) 0.000 26.384 u_cpu/exe_stage/ds_to_es_bus[136]
|
|
SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.081 27.177 u_cpu/exe_stage/ds_to_es_bus_r_reg[186]
|
|
-------------------------------------------------------------------
|
|
required time 27.177
|
|
arrival time -26.384
|
|
-------------------------------------------------------------------
|
|
slack 0.793
|
|
|
|
Slack (MET) : 0.793ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.035ns (logic 7.809ns (26.895%) route 21.226ns (73.105%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1
|
|
SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O
|
|
net (fo=32, routed) 0.967 24.378 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0
|
|
SLICE_X111Y155 f u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/I2
|
|
SLICE_X111Y155 LUT4 (Prop_lut4_I2_O) 0.124 24.502 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/O
|
|
net (fo=1, routed) 0.819 25.321 u_cpu/id_stage/ds_to_es_bus_r[186]_i_11_n_0
|
|
SLICE_X116Y155 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/I3
|
|
SLICE_X116Y155 LUT4 (Prop_lut4_I3_O) 0.124 25.445 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/O
|
|
net (fo=1, routed) 0.815 26.260 u_cpu/id_stage/ds_to_es_bus_r[186]_i_4_n_0
|
|
SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/I3
|
|
SLICE_X112Y158 LUT6 (Prop_lut6_I3_O) 0.124 26.384 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/O
|
|
net (fo=1, routed) 0.000 26.384 u_cpu/exe_stage/ds_to_es_bus[136]
|
|
SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.081 27.177 u_cpu/exe_stage/ds_to_es_bus_r_reg[186]
|
|
-------------------------------------------------------------------
|
|
required time 27.177
|
|
arrival time -26.384
|
|
-------------------------------------------------------------------
|
|
slack 0.793
|
|
|
|
Slack (MET) : 0.793ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.035ns (logic 7.809ns (26.895%) route 21.226ns (73.105%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1
|
|
SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O
|
|
net (fo=32, routed) 0.967 24.378 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0
|
|
SLICE_X111Y155 f u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/I2
|
|
SLICE_X111Y155 LUT4 (Prop_lut4_I2_O) 0.124 24.502 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/O
|
|
net (fo=1, routed) 0.819 25.321 u_cpu/id_stage/ds_to_es_bus_r[186]_i_11_n_0
|
|
SLICE_X116Y155 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/I3
|
|
SLICE_X116Y155 LUT4 (Prop_lut4_I3_O) 0.124 25.445 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/O
|
|
net (fo=1, routed) 0.815 26.260 u_cpu/id_stage/ds_to_es_bus_r[186]_i_4_n_0
|
|
SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/I3
|
|
SLICE_X112Y158 LUT6 (Prop_lut6_I3_O) 0.124 26.384 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/O
|
|
net (fo=1, routed) 0.000 26.384 u_cpu/exe_stage/ds_to_es_bus[136]
|
|
SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.081 27.177 u_cpu/exe_stage/ds_to_es_bus_r_reg[186]
|
|
-------------------------------------------------------------------
|
|
required time 27.177
|
|
arrival time -26.384
|
|
-------------------------------------------------------------------
|
|
slack 0.793
|
|
|
|
Slack (MET) : 0.793ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.035ns (logic 7.809ns (26.895%) route 21.226ns (73.105%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1
|
|
SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O
|
|
net (fo=32, routed) 0.967 24.378 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0
|
|
SLICE_X111Y155 f u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/I2
|
|
SLICE_X111Y155 LUT4 (Prop_lut4_I2_O) 0.124 24.502 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/O
|
|
net (fo=1, routed) 0.819 25.321 u_cpu/id_stage/ds_to_es_bus_r[186]_i_11_n_0
|
|
SLICE_X116Y155 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/I3
|
|
SLICE_X116Y155 LUT4 (Prop_lut4_I3_O) 0.124 25.445 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/O
|
|
net (fo=1, routed) 0.815 26.260 u_cpu/id_stage/ds_to_es_bus_r[186]_i_4_n_0
|
|
SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/I3
|
|
SLICE_X112Y158 LUT6 (Prop_lut6_I3_O) 0.124 26.384 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/O
|
|
net (fo=1, routed) 0.000 26.384 u_cpu/exe_stage/ds_to_es_bus[136]
|
|
SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.081 27.177 u_cpu/exe_stage/ds_to_es_bus_r_reg[186]
|
|
-------------------------------------------------------------------
|
|
required time 27.177
|
|
arrival time -26.384
|
|
-------------------------------------------------------------------
|
|
slack 0.793
|
|
|
|
Slack (MET) : 0.793ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.035ns (logic 7.809ns (26.895%) route 21.226ns (73.105%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1
|
|
SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O
|
|
net (fo=32, routed) 0.967 24.378 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0
|
|
SLICE_X111Y155 f u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/I2
|
|
SLICE_X111Y155 LUT4 (Prop_lut4_I2_O) 0.124 24.502 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/O
|
|
net (fo=1, routed) 0.819 25.321 u_cpu/id_stage/ds_to_es_bus_r[186]_i_11_n_0
|
|
SLICE_X116Y155 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/I3
|
|
SLICE_X116Y155 LUT4 (Prop_lut4_I3_O) 0.124 25.445 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/O
|
|
net (fo=1, routed) 0.815 26.260 u_cpu/id_stage/ds_to_es_bus_r[186]_i_4_n_0
|
|
SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/I3
|
|
SLICE_X112Y158 LUT6 (Prop_lut6_I3_O) 0.124 26.384 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/O
|
|
net (fo=1, routed) 0.000 26.384 u_cpu/exe_stage/ds_to_es_bus[136]
|
|
SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.081 27.177 u_cpu/exe_stage/ds_to_es_bus_r_reg[186]
|
|
-------------------------------------------------------------------
|
|
required time 27.177
|
|
arrival time -26.384
|
|
-------------------------------------------------------------------
|
|
slack 0.793
|
|
|
|
Slack (MET) : 0.793ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.035ns (logic 7.809ns (26.895%) route 21.226ns (73.105%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1
|
|
SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O
|
|
net (fo=32, routed) 0.967 24.378 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0
|
|
SLICE_X111Y155 f u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/I2
|
|
SLICE_X111Y155 LUT4 (Prop_lut4_I2_O) 0.124 24.502 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/O
|
|
net (fo=1, routed) 0.819 25.321 u_cpu/id_stage/ds_to_es_bus_r[186]_i_11_n_0
|
|
SLICE_X116Y155 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/I3
|
|
SLICE_X116Y155 LUT4 (Prop_lut4_I3_O) 0.124 25.445 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/O
|
|
net (fo=1, routed) 0.815 26.260 u_cpu/id_stage/ds_to_es_bus_r[186]_i_4_n_0
|
|
SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/I3
|
|
SLICE_X112Y158 LUT6 (Prop_lut6_I3_O) 0.124 26.384 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/O
|
|
net (fo=1, routed) 0.000 26.384 u_cpu/exe_stage/ds_to_es_bus[136]
|
|
SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.081 27.177 u_cpu/exe_stage/ds_to_es_bus_r_reg[186]
|
|
-------------------------------------------------------------------
|
|
required time 27.177
|
|
arrival time -26.384
|
|
-------------------------------------------------------------------
|
|
slack 0.793
|
|
|
|
Slack (MET) : 0.793ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.035ns (logic 7.809ns (26.895%) route 21.226ns (73.105%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1
|
|
SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O
|
|
net (fo=32, routed) 0.967 24.378 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0
|
|
SLICE_X111Y155 f u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/I2
|
|
SLICE_X111Y155 LUT4 (Prop_lut4_I2_O) 0.124 24.502 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/O
|
|
net (fo=1, routed) 0.819 25.321 u_cpu/id_stage/ds_to_es_bus_r[186]_i_11_n_0
|
|
SLICE_X116Y155 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/I3
|
|
SLICE_X116Y155 LUT4 (Prop_lut4_I3_O) 0.124 25.445 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/O
|
|
net (fo=1, routed) 0.815 26.260 u_cpu/id_stage/ds_to_es_bus_r[186]_i_4_n_0
|
|
SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/I3
|
|
SLICE_X112Y158 LUT6 (Prop_lut6_I3_O) 0.124 26.384 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/O
|
|
net (fo=1, routed) 0.000 26.384 u_cpu/exe_stage/ds_to_es_bus[136]
|
|
SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.081 27.177 u_cpu/exe_stage/ds_to_es_bus_r_reg[186]
|
|
-------------------------------------------------------------------
|
|
required time 27.177
|
|
arrival time -26.384
|
|
-------------------------------------------------------------------
|
|
slack 0.793
|
|
|
|
Slack (MET) : 0.793ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.035ns (logic 7.809ns (26.895%) route 21.226ns (73.105%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1
|
|
SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O
|
|
net (fo=32, routed) 0.967 24.378 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0
|
|
SLICE_X111Y155 f u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/I2
|
|
SLICE_X111Y155 LUT4 (Prop_lut4_I2_O) 0.124 24.502 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/O
|
|
net (fo=1, routed) 0.819 25.321 u_cpu/id_stage/ds_to_es_bus_r[186]_i_11_n_0
|
|
SLICE_X116Y155 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/I3
|
|
SLICE_X116Y155 LUT4 (Prop_lut4_I3_O) 0.124 25.445 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/O
|
|
net (fo=1, routed) 0.815 26.260 u_cpu/id_stage/ds_to_es_bus_r[186]_i_4_n_0
|
|
SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/I3
|
|
SLICE_X112Y158 LUT6 (Prop_lut6_I3_O) 0.124 26.384 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/O
|
|
net (fo=1, routed) 0.000 26.384 u_cpu/exe_stage/ds_to_es_bus[136]
|
|
SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.081 27.177 u_cpu/exe_stage/ds_to_es_bus_r_reg[186]
|
|
-------------------------------------------------------------------
|
|
required time 27.177
|
|
arrival time -26.384
|
|
-------------------------------------------------------------------
|
|
slack 0.793
|
|
|
|
Slack (MET) : 0.793ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.035ns (logic 7.809ns (26.895%) route 21.226ns (73.105%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1
|
|
SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O
|
|
net (fo=32, routed) 0.967 24.378 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0
|
|
SLICE_X111Y155 f u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/I2
|
|
SLICE_X111Y155 LUT4 (Prop_lut4_I2_O) 0.124 24.502 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/O
|
|
net (fo=1, routed) 0.819 25.321 u_cpu/id_stage/ds_to_es_bus_r[186]_i_11_n_0
|
|
SLICE_X116Y155 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/I3
|
|
SLICE_X116Y155 LUT4 (Prop_lut4_I3_O) 0.124 25.445 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/O
|
|
net (fo=1, routed) 0.815 26.260 u_cpu/id_stage/ds_to_es_bus_r[186]_i_4_n_0
|
|
SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/I3
|
|
SLICE_X112Y158 LUT6 (Prop_lut6_I3_O) 0.124 26.384 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/O
|
|
net (fo=1, routed) 0.000 26.384 u_cpu/exe_stage/ds_to_es_bus[136]
|
|
SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.081 27.177 u_cpu/exe_stage/ds_to_es_bus_r_reg[186]
|
|
-------------------------------------------------------------------
|
|
required time 27.177
|
|
arrival time -26.384
|
|
-------------------------------------------------------------------
|
|
slack 0.793
|
|
|
|
Slack (MET) : 0.793ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.035ns (logic 7.809ns (26.895%) route 21.226ns (73.105%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1
|
|
SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O
|
|
net (fo=32, routed) 0.967 24.378 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0
|
|
SLICE_X111Y155 f u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/I2
|
|
SLICE_X111Y155 LUT4 (Prop_lut4_I2_O) 0.124 24.502 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/O
|
|
net (fo=1, routed) 0.819 25.321 u_cpu/id_stage/ds_to_es_bus_r[186]_i_11_n_0
|
|
SLICE_X116Y155 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/I3
|
|
SLICE_X116Y155 LUT4 (Prop_lut4_I3_O) 0.124 25.445 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/O
|
|
net (fo=1, routed) 0.815 26.260 u_cpu/id_stage/ds_to_es_bus_r[186]_i_4_n_0
|
|
SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/I3
|
|
SLICE_X112Y158 LUT6 (Prop_lut6_I3_O) 0.124 26.384 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/O
|
|
net (fo=1, routed) 0.000 26.384 u_cpu/exe_stage/ds_to_es_bus[136]
|
|
SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.081 27.177 u_cpu/exe_stage/ds_to_es_bus_r_reg[186]
|
|
-------------------------------------------------------------------
|
|
required time 27.177
|
|
arrival time -26.384
|
|
-------------------------------------------------------------------
|
|
slack 0.793
|
|
|
|
Slack (MET) : 0.803ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.973ns (logic 8.037ns (27.740%) route 20.936ns (72.260%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0
|
|
SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O
|
|
net (fo=27, routed) 0.894 25.117 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3
|
|
SLICE_X114Y152 f u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/I2
|
|
SLICE_X114Y152 LUT4 (Prop_lut4_I2_O) 0.150 25.267 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/O
|
|
net (fo=1, routed) 0.729 25.996 u_cpu/id_stage/ds_to_es_bus_r[168]_i_2_n_0
|
|
SLICE_X110Y152 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/I1
|
|
SLICE_X110Y152 LUT6 (Prop_lut6_I1_O) 0.326 26.322 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/O
|
|
net (fo=1, routed) 0.000 26.322 u_cpu/exe_stage/ds_to_es_bus[118]
|
|
SLICE_X110Y152 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X110Y152 FDRE (Setup_fdre_C_D) 0.029 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[168]
|
|
-------------------------------------------------------------------
|
|
required time 27.125
|
|
arrival time -26.322
|
|
-------------------------------------------------------------------
|
|
slack 0.803
|
|
|
|
Slack (MET) : 0.803ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.973ns (logic 8.037ns (27.740%) route 20.936ns (72.260%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0
|
|
SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O
|
|
net (fo=27, routed) 0.894 25.117 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3
|
|
SLICE_X114Y152 f u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/I2
|
|
SLICE_X114Y152 LUT4 (Prop_lut4_I2_O) 0.150 25.267 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/O
|
|
net (fo=1, routed) 0.729 25.996 u_cpu/id_stage/ds_to_es_bus_r[168]_i_2_n_0
|
|
SLICE_X110Y152 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/I1
|
|
SLICE_X110Y152 LUT6 (Prop_lut6_I1_O) 0.326 26.322 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/O
|
|
net (fo=1, routed) 0.000 26.322 u_cpu/exe_stage/ds_to_es_bus[118]
|
|
SLICE_X110Y152 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X110Y152 FDRE (Setup_fdre_C_D) 0.029 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[168]
|
|
-------------------------------------------------------------------
|
|
required time 27.125
|
|
arrival time -26.322
|
|
-------------------------------------------------------------------
|
|
slack 0.803
|
|
|
|
Slack (MET) : 0.803ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.973ns (logic 8.037ns (27.740%) route 20.936ns (72.260%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0
|
|
SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O
|
|
net (fo=27, routed) 0.894 25.117 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3
|
|
SLICE_X114Y152 f u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/I2
|
|
SLICE_X114Y152 LUT4 (Prop_lut4_I2_O) 0.150 25.267 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/O
|
|
net (fo=1, routed) 0.729 25.996 u_cpu/id_stage/ds_to_es_bus_r[168]_i_2_n_0
|
|
SLICE_X110Y152 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/I1
|
|
SLICE_X110Y152 LUT6 (Prop_lut6_I1_O) 0.326 26.322 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/O
|
|
net (fo=1, routed) 0.000 26.322 u_cpu/exe_stage/ds_to_es_bus[118]
|
|
SLICE_X110Y152 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X110Y152 FDRE (Setup_fdre_C_D) 0.029 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[168]
|
|
-------------------------------------------------------------------
|
|
required time 27.125
|
|
arrival time -26.322
|
|
-------------------------------------------------------------------
|
|
slack 0.803
|
|
|
|
Slack (MET) : 0.803ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.973ns (logic 8.037ns (27.740%) route 20.936ns (72.260%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0
|
|
SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O
|
|
net (fo=27, routed) 0.894 25.117 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3
|
|
SLICE_X114Y152 f u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/I2
|
|
SLICE_X114Y152 LUT4 (Prop_lut4_I2_O) 0.150 25.267 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/O
|
|
net (fo=1, routed) 0.729 25.996 u_cpu/id_stage/ds_to_es_bus_r[168]_i_2_n_0
|
|
SLICE_X110Y152 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/I1
|
|
SLICE_X110Y152 LUT6 (Prop_lut6_I1_O) 0.326 26.322 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/O
|
|
net (fo=1, routed) 0.000 26.322 u_cpu/exe_stage/ds_to_es_bus[118]
|
|
SLICE_X110Y152 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X110Y152 FDRE (Setup_fdre_C_D) 0.029 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[168]
|
|
-------------------------------------------------------------------
|
|
required time 27.125
|
|
arrival time -26.322
|
|
-------------------------------------------------------------------
|
|
slack 0.803
|
|
|
|
Slack (MET) : 0.803ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.973ns (logic 8.037ns (27.740%) route 20.936ns (72.260%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0
|
|
SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O
|
|
net (fo=27, routed) 0.894 25.117 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3
|
|
SLICE_X114Y152 f u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/I2
|
|
SLICE_X114Y152 LUT4 (Prop_lut4_I2_O) 0.150 25.267 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/O
|
|
net (fo=1, routed) 0.729 25.996 u_cpu/id_stage/ds_to_es_bus_r[168]_i_2_n_0
|
|
SLICE_X110Y152 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/I1
|
|
SLICE_X110Y152 LUT6 (Prop_lut6_I1_O) 0.326 26.322 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/O
|
|
net (fo=1, routed) 0.000 26.322 u_cpu/exe_stage/ds_to_es_bus[118]
|
|
SLICE_X110Y152 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X110Y152 FDRE (Setup_fdre_C_D) 0.029 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[168]
|
|
-------------------------------------------------------------------
|
|
required time 27.125
|
|
arrival time -26.322
|
|
-------------------------------------------------------------------
|
|
slack 0.803
|
|
|
|
Slack (MET) : 0.803ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.973ns (logic 8.037ns (27.740%) route 20.936ns (72.260%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0
|
|
SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O
|
|
net (fo=27, routed) 0.894 25.117 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3
|
|
SLICE_X114Y152 f u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/I2
|
|
SLICE_X114Y152 LUT4 (Prop_lut4_I2_O) 0.150 25.267 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/O
|
|
net (fo=1, routed) 0.729 25.996 u_cpu/id_stage/ds_to_es_bus_r[168]_i_2_n_0
|
|
SLICE_X110Y152 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/I1
|
|
SLICE_X110Y152 LUT6 (Prop_lut6_I1_O) 0.326 26.322 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/O
|
|
net (fo=1, routed) 0.000 26.322 u_cpu/exe_stage/ds_to_es_bus[118]
|
|
SLICE_X110Y152 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X110Y152 FDRE (Setup_fdre_C_D) 0.029 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[168]
|
|
-------------------------------------------------------------------
|
|
required time 27.125
|
|
arrival time -26.322
|
|
-------------------------------------------------------------------
|
|
slack 0.803
|
|
|
|
Slack (MET) : 0.803ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.973ns (logic 8.037ns (27.740%) route 20.936ns (72.260%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0
|
|
SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O
|
|
net (fo=27, routed) 0.894 25.117 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3
|
|
SLICE_X114Y152 f u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/I2
|
|
SLICE_X114Y152 LUT4 (Prop_lut4_I2_O) 0.150 25.267 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/O
|
|
net (fo=1, routed) 0.729 25.996 u_cpu/id_stage/ds_to_es_bus_r[168]_i_2_n_0
|
|
SLICE_X110Y152 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/I1
|
|
SLICE_X110Y152 LUT6 (Prop_lut6_I1_O) 0.326 26.322 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/O
|
|
net (fo=1, routed) 0.000 26.322 u_cpu/exe_stage/ds_to_es_bus[118]
|
|
SLICE_X110Y152 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X110Y152 FDRE (Setup_fdre_C_D) 0.029 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[168]
|
|
-------------------------------------------------------------------
|
|
required time 27.125
|
|
arrival time -26.322
|
|
-------------------------------------------------------------------
|
|
slack 0.803
|
|
|
|
Slack (MET) : 0.803ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.973ns (logic 8.037ns (27.740%) route 20.936ns (72.260%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0
|
|
SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O
|
|
net (fo=27, routed) 0.894 25.117 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3
|
|
SLICE_X114Y152 f u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/I2
|
|
SLICE_X114Y152 LUT4 (Prop_lut4_I2_O) 0.150 25.267 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/O
|
|
net (fo=1, routed) 0.729 25.996 u_cpu/id_stage/ds_to_es_bus_r[168]_i_2_n_0
|
|
SLICE_X110Y152 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/I1
|
|
SLICE_X110Y152 LUT6 (Prop_lut6_I1_O) 0.326 26.322 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/O
|
|
net (fo=1, routed) 0.000 26.322 u_cpu/exe_stage/ds_to_es_bus[118]
|
|
SLICE_X110Y152 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X110Y152 FDRE (Setup_fdre_C_D) 0.029 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[168]
|
|
-------------------------------------------------------------------
|
|
required time 27.125
|
|
arrival time -26.322
|
|
-------------------------------------------------------------------
|
|
slack 0.803
|
|
|
|
Slack (MET) : 0.803ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.973ns (logic 8.037ns (27.740%) route 20.936ns (72.260%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0
|
|
SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O
|
|
net (fo=27, routed) 0.894 25.117 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3
|
|
SLICE_X114Y152 f u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/I2
|
|
SLICE_X114Y152 LUT4 (Prop_lut4_I2_O) 0.150 25.267 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/O
|
|
net (fo=1, routed) 0.729 25.996 u_cpu/id_stage/ds_to_es_bus_r[168]_i_2_n_0
|
|
SLICE_X110Y152 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/I1
|
|
SLICE_X110Y152 LUT6 (Prop_lut6_I1_O) 0.326 26.322 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/O
|
|
net (fo=1, routed) 0.000 26.322 u_cpu/exe_stage/ds_to_es_bus[118]
|
|
SLICE_X110Y152 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X110Y152 FDRE (Setup_fdre_C_D) 0.029 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[168]
|
|
-------------------------------------------------------------------
|
|
required time 27.125
|
|
arrival time -26.322
|
|
-------------------------------------------------------------------
|
|
slack 0.803
|
|
|
|
Slack (MET) : 0.803ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.973ns (logic 8.037ns (27.740%) route 20.936ns (72.260%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0
|
|
SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O
|
|
net (fo=27, routed) 0.894 25.117 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3
|
|
SLICE_X114Y152 f u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/I2
|
|
SLICE_X114Y152 LUT4 (Prop_lut4_I2_O) 0.150 25.267 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/O
|
|
net (fo=1, routed) 0.729 25.996 u_cpu/id_stage/ds_to_es_bus_r[168]_i_2_n_0
|
|
SLICE_X110Y152 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/I1
|
|
SLICE_X110Y152 LUT6 (Prop_lut6_I1_O) 0.326 26.322 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/O
|
|
net (fo=1, routed) 0.000 26.322 u_cpu/exe_stage/ds_to_es_bus[118]
|
|
SLICE_X110Y152 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X110Y152 FDRE (Setup_fdre_C_D) 0.029 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[168]
|
|
-------------------------------------------------------------------
|
|
required time 27.125
|
|
arrival time -26.322
|
|
-------------------------------------------------------------------
|
|
slack 0.803
|
|
|
|
Slack (MET) : 0.804ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.019ns (logic 8.012ns (27.609%) route 21.007ns (72.391%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.141ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2
|
|
SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O
|
|
net (fo=20, routed) 0.713 24.270 u_cpu/id_stage/fs_to_ds_bus_r_reg[45]_2
|
|
SLICE_X115Y155 f u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/I0
|
|
SLICE_X115Y155 LUT6 (Prop_lut6_I0_O) 0.332 24.602 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/O
|
|
net (fo=1, routed) 0.848 25.450 u_cpu/id_stage/ds_to_es_bus_r[181]_i_8_n_0
|
|
SLICE_X104Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/I0
|
|
SLICE_X104Y156 LUT6 (Prop_lut6_I0_O) 0.124 25.574 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O
|
|
net (fo=1, routed) 0.671 26.245 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0
|
|
SLICE_X108Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/I3
|
|
SLICE_X108Y156 LUT6 (Prop_lut6_I3_O) 0.124 26.369 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O
|
|
net (fo=1, routed) 0.000 26.369 u_cpu/exe_stage/ds_to_es_bus[131]
|
|
SLICE_X108Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.397 27.722
|
|
clock pessimism -0.514 27.209
|
|
clock uncertainty -0.113 27.095
|
|
SLICE_X108Y156 FDRE (Setup_fdre_C_D) 0.077 27.172 u_cpu/exe_stage/ds_to_es_bus_r_reg[181]
|
|
-------------------------------------------------------------------
|
|
required time 27.172
|
|
arrival time -26.369
|
|
-------------------------------------------------------------------
|
|
slack 0.804
|
|
|
|
Slack (MET) : 0.804ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.019ns (logic 8.012ns (27.609%) route 21.007ns (72.391%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.141ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2
|
|
SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O
|
|
net (fo=20, routed) 0.713 24.270 u_cpu/id_stage/fs_to_ds_bus_r_reg[45]_2
|
|
SLICE_X115Y155 f u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/I0
|
|
SLICE_X115Y155 LUT6 (Prop_lut6_I0_O) 0.332 24.602 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/O
|
|
net (fo=1, routed) 0.848 25.450 u_cpu/id_stage/ds_to_es_bus_r[181]_i_8_n_0
|
|
SLICE_X104Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/I0
|
|
SLICE_X104Y156 LUT6 (Prop_lut6_I0_O) 0.124 25.574 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O
|
|
net (fo=1, routed) 0.671 26.245 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0
|
|
SLICE_X108Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/I3
|
|
SLICE_X108Y156 LUT6 (Prop_lut6_I3_O) 0.124 26.369 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O
|
|
net (fo=1, routed) 0.000 26.369 u_cpu/exe_stage/ds_to_es_bus[131]
|
|
SLICE_X108Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.397 27.722
|
|
clock pessimism -0.514 27.209
|
|
clock uncertainty -0.113 27.095
|
|
SLICE_X108Y156 FDRE (Setup_fdre_C_D) 0.077 27.172 u_cpu/exe_stage/ds_to_es_bus_r_reg[181]
|
|
-------------------------------------------------------------------
|
|
required time 27.172
|
|
arrival time -26.369
|
|
-------------------------------------------------------------------
|
|
slack 0.804
|
|
|
|
Slack (MET) : 0.804ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.019ns (logic 8.012ns (27.609%) route 21.007ns (72.391%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.141ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2
|
|
SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O
|
|
net (fo=20, routed) 0.713 24.270 u_cpu/id_stage/fs_to_ds_bus_r_reg[45]_2
|
|
SLICE_X115Y155 f u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/I0
|
|
SLICE_X115Y155 LUT6 (Prop_lut6_I0_O) 0.332 24.602 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/O
|
|
net (fo=1, routed) 0.848 25.450 u_cpu/id_stage/ds_to_es_bus_r[181]_i_8_n_0
|
|
SLICE_X104Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/I0
|
|
SLICE_X104Y156 LUT6 (Prop_lut6_I0_O) 0.124 25.574 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O
|
|
net (fo=1, routed) 0.671 26.245 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0
|
|
SLICE_X108Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/I3
|
|
SLICE_X108Y156 LUT6 (Prop_lut6_I3_O) 0.124 26.369 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O
|
|
net (fo=1, routed) 0.000 26.369 u_cpu/exe_stage/ds_to_es_bus[131]
|
|
SLICE_X108Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.397 27.722
|
|
clock pessimism -0.514 27.209
|
|
clock uncertainty -0.113 27.095
|
|
SLICE_X108Y156 FDRE (Setup_fdre_C_D) 0.077 27.172 u_cpu/exe_stage/ds_to_es_bus_r_reg[181]
|
|
-------------------------------------------------------------------
|
|
required time 27.172
|
|
arrival time -26.369
|
|
-------------------------------------------------------------------
|
|
slack 0.804
|
|
|
|
Slack (MET) : 0.804ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.019ns (logic 8.012ns (27.609%) route 21.007ns (72.391%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.141ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2
|
|
SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O
|
|
net (fo=20, routed) 0.713 24.270 u_cpu/id_stage/fs_to_ds_bus_r_reg[45]_2
|
|
SLICE_X115Y155 f u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/I0
|
|
SLICE_X115Y155 LUT6 (Prop_lut6_I0_O) 0.332 24.602 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/O
|
|
net (fo=1, routed) 0.848 25.450 u_cpu/id_stage/ds_to_es_bus_r[181]_i_8_n_0
|
|
SLICE_X104Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/I0
|
|
SLICE_X104Y156 LUT6 (Prop_lut6_I0_O) 0.124 25.574 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O
|
|
net (fo=1, routed) 0.671 26.245 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0
|
|
SLICE_X108Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/I3
|
|
SLICE_X108Y156 LUT6 (Prop_lut6_I3_O) 0.124 26.369 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O
|
|
net (fo=1, routed) 0.000 26.369 u_cpu/exe_stage/ds_to_es_bus[131]
|
|
SLICE_X108Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.397 27.722
|
|
clock pessimism -0.514 27.209
|
|
clock uncertainty -0.113 27.095
|
|
SLICE_X108Y156 FDRE (Setup_fdre_C_D) 0.077 27.172 u_cpu/exe_stage/ds_to_es_bus_r_reg[181]
|
|
-------------------------------------------------------------------
|
|
required time 27.172
|
|
arrival time -26.369
|
|
-------------------------------------------------------------------
|
|
slack 0.804
|
|
|
|
Slack (MET) : 0.804ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.019ns (logic 8.012ns (27.609%) route 21.007ns (72.391%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.141ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2
|
|
SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O
|
|
net (fo=20, routed) 0.713 24.270 u_cpu/id_stage/fs_to_ds_bus_r_reg[45]_2
|
|
SLICE_X115Y155 f u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/I0
|
|
SLICE_X115Y155 LUT6 (Prop_lut6_I0_O) 0.332 24.602 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/O
|
|
net (fo=1, routed) 0.848 25.450 u_cpu/id_stage/ds_to_es_bus_r[181]_i_8_n_0
|
|
SLICE_X104Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/I0
|
|
SLICE_X104Y156 LUT6 (Prop_lut6_I0_O) 0.124 25.574 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O
|
|
net (fo=1, routed) 0.671 26.245 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0
|
|
SLICE_X108Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/I3
|
|
SLICE_X108Y156 LUT6 (Prop_lut6_I3_O) 0.124 26.369 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O
|
|
net (fo=1, routed) 0.000 26.369 u_cpu/exe_stage/ds_to_es_bus[131]
|
|
SLICE_X108Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.397 27.722
|
|
clock pessimism -0.514 27.209
|
|
clock uncertainty -0.113 27.095
|
|
SLICE_X108Y156 FDRE (Setup_fdre_C_D) 0.077 27.172 u_cpu/exe_stage/ds_to_es_bus_r_reg[181]
|
|
-------------------------------------------------------------------
|
|
required time 27.172
|
|
arrival time -26.369
|
|
-------------------------------------------------------------------
|
|
slack 0.804
|
|
|
|
Slack (MET) : 0.804ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.019ns (logic 8.012ns (27.609%) route 21.007ns (72.391%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.141ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2
|
|
SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O
|
|
net (fo=20, routed) 0.713 24.270 u_cpu/id_stage/fs_to_ds_bus_r_reg[45]_2
|
|
SLICE_X115Y155 f u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/I0
|
|
SLICE_X115Y155 LUT6 (Prop_lut6_I0_O) 0.332 24.602 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/O
|
|
net (fo=1, routed) 0.848 25.450 u_cpu/id_stage/ds_to_es_bus_r[181]_i_8_n_0
|
|
SLICE_X104Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/I0
|
|
SLICE_X104Y156 LUT6 (Prop_lut6_I0_O) 0.124 25.574 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O
|
|
net (fo=1, routed) 0.671 26.245 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0
|
|
SLICE_X108Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/I3
|
|
SLICE_X108Y156 LUT6 (Prop_lut6_I3_O) 0.124 26.369 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O
|
|
net (fo=1, routed) 0.000 26.369 u_cpu/exe_stage/ds_to_es_bus[131]
|
|
SLICE_X108Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.397 27.722
|
|
clock pessimism -0.514 27.209
|
|
clock uncertainty -0.113 27.095
|
|
SLICE_X108Y156 FDRE (Setup_fdre_C_D) 0.077 27.172 u_cpu/exe_stage/ds_to_es_bus_r_reg[181]
|
|
-------------------------------------------------------------------
|
|
required time 27.172
|
|
arrival time -26.369
|
|
-------------------------------------------------------------------
|
|
slack 0.804
|
|
|
|
Slack (MET) : 0.804ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.019ns (logic 8.012ns (27.609%) route 21.007ns (72.391%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.141ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2
|
|
SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O
|
|
net (fo=20, routed) 0.713 24.270 u_cpu/id_stage/fs_to_ds_bus_r_reg[45]_2
|
|
SLICE_X115Y155 f u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/I0
|
|
SLICE_X115Y155 LUT6 (Prop_lut6_I0_O) 0.332 24.602 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/O
|
|
net (fo=1, routed) 0.848 25.450 u_cpu/id_stage/ds_to_es_bus_r[181]_i_8_n_0
|
|
SLICE_X104Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/I0
|
|
SLICE_X104Y156 LUT6 (Prop_lut6_I0_O) 0.124 25.574 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O
|
|
net (fo=1, routed) 0.671 26.245 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0
|
|
SLICE_X108Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/I3
|
|
SLICE_X108Y156 LUT6 (Prop_lut6_I3_O) 0.124 26.369 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O
|
|
net (fo=1, routed) 0.000 26.369 u_cpu/exe_stage/ds_to_es_bus[131]
|
|
SLICE_X108Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.397 27.722
|
|
clock pessimism -0.514 27.209
|
|
clock uncertainty -0.113 27.095
|
|
SLICE_X108Y156 FDRE (Setup_fdre_C_D) 0.077 27.172 u_cpu/exe_stage/ds_to_es_bus_r_reg[181]
|
|
-------------------------------------------------------------------
|
|
required time 27.172
|
|
arrival time -26.369
|
|
-------------------------------------------------------------------
|
|
slack 0.804
|
|
|
|
Slack (MET) : 0.804ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.019ns (logic 8.012ns (27.609%) route 21.007ns (72.391%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.141ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2
|
|
SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O
|
|
net (fo=20, routed) 0.713 24.270 u_cpu/id_stage/fs_to_ds_bus_r_reg[45]_2
|
|
SLICE_X115Y155 f u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/I0
|
|
SLICE_X115Y155 LUT6 (Prop_lut6_I0_O) 0.332 24.602 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/O
|
|
net (fo=1, routed) 0.848 25.450 u_cpu/id_stage/ds_to_es_bus_r[181]_i_8_n_0
|
|
SLICE_X104Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/I0
|
|
SLICE_X104Y156 LUT6 (Prop_lut6_I0_O) 0.124 25.574 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O
|
|
net (fo=1, routed) 0.671 26.245 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0
|
|
SLICE_X108Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/I3
|
|
SLICE_X108Y156 LUT6 (Prop_lut6_I3_O) 0.124 26.369 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O
|
|
net (fo=1, routed) 0.000 26.369 u_cpu/exe_stage/ds_to_es_bus[131]
|
|
SLICE_X108Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.397 27.722
|
|
clock pessimism -0.514 27.209
|
|
clock uncertainty -0.113 27.095
|
|
SLICE_X108Y156 FDRE (Setup_fdre_C_D) 0.077 27.172 u_cpu/exe_stage/ds_to_es_bus_r_reg[181]
|
|
-------------------------------------------------------------------
|
|
required time 27.172
|
|
arrival time -26.369
|
|
-------------------------------------------------------------------
|
|
slack 0.804
|
|
|
|
Slack (MET) : 0.804ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.019ns (logic 8.012ns (27.609%) route 21.007ns (72.391%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.141ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2
|
|
SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O
|
|
net (fo=20, routed) 0.713 24.270 u_cpu/id_stage/fs_to_ds_bus_r_reg[45]_2
|
|
SLICE_X115Y155 f u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/I0
|
|
SLICE_X115Y155 LUT6 (Prop_lut6_I0_O) 0.332 24.602 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/O
|
|
net (fo=1, routed) 0.848 25.450 u_cpu/id_stage/ds_to_es_bus_r[181]_i_8_n_0
|
|
SLICE_X104Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/I0
|
|
SLICE_X104Y156 LUT6 (Prop_lut6_I0_O) 0.124 25.574 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O
|
|
net (fo=1, routed) 0.671 26.245 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0
|
|
SLICE_X108Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/I3
|
|
SLICE_X108Y156 LUT6 (Prop_lut6_I3_O) 0.124 26.369 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O
|
|
net (fo=1, routed) 0.000 26.369 u_cpu/exe_stage/ds_to_es_bus[131]
|
|
SLICE_X108Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.397 27.722
|
|
clock pessimism -0.514 27.209
|
|
clock uncertainty -0.113 27.095
|
|
SLICE_X108Y156 FDRE (Setup_fdre_C_D) 0.077 27.172 u_cpu/exe_stage/ds_to_es_bus_r_reg[181]
|
|
-------------------------------------------------------------------
|
|
required time 27.172
|
|
arrival time -26.369
|
|
-------------------------------------------------------------------
|
|
slack 0.804
|
|
|
|
Slack (MET) : 0.804ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 29.019ns (logic 8.012ns (27.609%) route 21.007ns (72.391%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.141ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2
|
|
SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O
|
|
net (fo=20, routed) 0.713 24.270 u_cpu/id_stage/fs_to_ds_bus_r_reg[45]_2
|
|
SLICE_X115Y155 f u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/I0
|
|
SLICE_X115Y155 LUT6 (Prop_lut6_I0_O) 0.332 24.602 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/O
|
|
net (fo=1, routed) 0.848 25.450 u_cpu/id_stage/ds_to_es_bus_r[181]_i_8_n_0
|
|
SLICE_X104Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/I0
|
|
SLICE_X104Y156 LUT6 (Prop_lut6_I0_O) 0.124 25.574 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O
|
|
net (fo=1, routed) 0.671 26.245 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0
|
|
SLICE_X108Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/I3
|
|
SLICE_X108Y156 LUT6 (Prop_lut6_I3_O) 0.124 26.369 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O
|
|
net (fo=1, routed) 0.000 26.369 u_cpu/exe_stage/ds_to_es_bus[131]
|
|
SLICE_X108Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.397 27.722
|
|
clock pessimism -0.514 27.209
|
|
clock uncertainty -0.113 27.095
|
|
SLICE_X108Y156 FDRE (Setup_fdre_C_D) 0.077 27.172 u_cpu/exe_stage/ds_to_es_bus_r_reg[181]
|
|
-------------------------------------------------------------------
|
|
required time 27.172
|
|
arrival time -26.369
|
|
-------------------------------------------------------------------
|
|
slack 0.804
|
|
|
|
Slack (MET) : 0.863ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.961ns (logic 7.809ns (26.964%) route 21.152ns (73.036%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1
|
|
SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O
|
|
net (fo=32, routed) 0.987 24.398 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0
|
|
SLICE_X117Y153 f u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/I2
|
|
SLICE_X117Y153 LUT4 (Prop_lut4_I2_O) 0.124 24.522 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/O
|
|
net (fo=1, routed) 0.718 25.239 u_cpu/id_stage/ds_to_es_bus_r[185]_i_7_n_0
|
|
SLICE_X117Y156 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/I2
|
|
SLICE_X117Y156 LUT4 (Prop_lut4_I2_O) 0.124 25.363 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/O
|
|
net (fo=1, routed) 0.823 26.187 u_cpu/id_stage/ds_to_es_bus_r[185]_i_3_n_0
|
|
SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/I2
|
|
SLICE_X112Y158 LUT6 (Prop_lut6_I2_O) 0.124 26.311 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/O
|
|
net (fo=1, routed) 0.000 26.311 u_cpu/exe_stage/ds_to_es_bus[135]
|
|
SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.077 27.173 u_cpu/exe_stage/ds_to_es_bus_r_reg[185]
|
|
-------------------------------------------------------------------
|
|
required time 27.173
|
|
arrival time -26.311
|
|
-------------------------------------------------------------------
|
|
slack 0.863
|
|
|
|
Slack (MET) : 0.863ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.961ns (logic 7.809ns (26.964%) route 21.152ns (73.036%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1
|
|
SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O
|
|
net (fo=32, routed) 0.987 24.398 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0
|
|
SLICE_X117Y153 f u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/I2
|
|
SLICE_X117Y153 LUT4 (Prop_lut4_I2_O) 0.124 24.522 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/O
|
|
net (fo=1, routed) 0.718 25.239 u_cpu/id_stage/ds_to_es_bus_r[185]_i_7_n_0
|
|
SLICE_X117Y156 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/I2
|
|
SLICE_X117Y156 LUT4 (Prop_lut4_I2_O) 0.124 25.363 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/O
|
|
net (fo=1, routed) 0.823 26.187 u_cpu/id_stage/ds_to_es_bus_r[185]_i_3_n_0
|
|
SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/I2
|
|
SLICE_X112Y158 LUT6 (Prop_lut6_I2_O) 0.124 26.311 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/O
|
|
net (fo=1, routed) 0.000 26.311 u_cpu/exe_stage/ds_to_es_bus[135]
|
|
SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.077 27.173 u_cpu/exe_stage/ds_to_es_bus_r_reg[185]
|
|
-------------------------------------------------------------------
|
|
required time 27.173
|
|
arrival time -26.311
|
|
-------------------------------------------------------------------
|
|
slack 0.863
|
|
|
|
Slack (MET) : 0.863ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.961ns (logic 7.809ns (26.964%) route 21.152ns (73.036%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1
|
|
SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O
|
|
net (fo=32, routed) 0.987 24.398 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0
|
|
SLICE_X117Y153 f u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/I2
|
|
SLICE_X117Y153 LUT4 (Prop_lut4_I2_O) 0.124 24.522 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/O
|
|
net (fo=1, routed) 0.718 25.239 u_cpu/id_stage/ds_to_es_bus_r[185]_i_7_n_0
|
|
SLICE_X117Y156 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/I2
|
|
SLICE_X117Y156 LUT4 (Prop_lut4_I2_O) 0.124 25.363 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/O
|
|
net (fo=1, routed) 0.823 26.187 u_cpu/id_stage/ds_to_es_bus_r[185]_i_3_n_0
|
|
SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/I2
|
|
SLICE_X112Y158 LUT6 (Prop_lut6_I2_O) 0.124 26.311 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/O
|
|
net (fo=1, routed) 0.000 26.311 u_cpu/exe_stage/ds_to_es_bus[135]
|
|
SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.077 27.173 u_cpu/exe_stage/ds_to_es_bus_r_reg[185]
|
|
-------------------------------------------------------------------
|
|
required time 27.173
|
|
arrival time -26.311
|
|
-------------------------------------------------------------------
|
|
slack 0.863
|
|
|
|
Slack (MET) : 0.863ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.961ns (logic 7.809ns (26.964%) route 21.152ns (73.036%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1
|
|
SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O
|
|
net (fo=32, routed) 0.987 24.398 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0
|
|
SLICE_X117Y153 f u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/I2
|
|
SLICE_X117Y153 LUT4 (Prop_lut4_I2_O) 0.124 24.522 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/O
|
|
net (fo=1, routed) 0.718 25.239 u_cpu/id_stage/ds_to_es_bus_r[185]_i_7_n_0
|
|
SLICE_X117Y156 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/I2
|
|
SLICE_X117Y156 LUT4 (Prop_lut4_I2_O) 0.124 25.363 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/O
|
|
net (fo=1, routed) 0.823 26.187 u_cpu/id_stage/ds_to_es_bus_r[185]_i_3_n_0
|
|
SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/I2
|
|
SLICE_X112Y158 LUT6 (Prop_lut6_I2_O) 0.124 26.311 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/O
|
|
net (fo=1, routed) 0.000 26.311 u_cpu/exe_stage/ds_to_es_bus[135]
|
|
SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.077 27.173 u_cpu/exe_stage/ds_to_es_bus_r_reg[185]
|
|
-------------------------------------------------------------------
|
|
required time 27.173
|
|
arrival time -26.311
|
|
-------------------------------------------------------------------
|
|
slack 0.863
|
|
|
|
Slack (MET) : 0.863ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.961ns (logic 7.809ns (26.964%) route 21.152ns (73.036%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1
|
|
SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O
|
|
net (fo=32, routed) 0.987 24.398 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0
|
|
SLICE_X117Y153 f u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/I2
|
|
SLICE_X117Y153 LUT4 (Prop_lut4_I2_O) 0.124 24.522 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/O
|
|
net (fo=1, routed) 0.718 25.239 u_cpu/id_stage/ds_to_es_bus_r[185]_i_7_n_0
|
|
SLICE_X117Y156 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/I2
|
|
SLICE_X117Y156 LUT4 (Prop_lut4_I2_O) 0.124 25.363 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/O
|
|
net (fo=1, routed) 0.823 26.187 u_cpu/id_stage/ds_to_es_bus_r[185]_i_3_n_0
|
|
SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/I2
|
|
SLICE_X112Y158 LUT6 (Prop_lut6_I2_O) 0.124 26.311 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/O
|
|
net (fo=1, routed) 0.000 26.311 u_cpu/exe_stage/ds_to_es_bus[135]
|
|
SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.077 27.173 u_cpu/exe_stage/ds_to_es_bus_r_reg[185]
|
|
-------------------------------------------------------------------
|
|
required time 27.173
|
|
arrival time -26.311
|
|
-------------------------------------------------------------------
|
|
slack 0.863
|
|
|
|
Slack (MET) : 0.863ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.961ns (logic 7.809ns (26.964%) route 21.152ns (73.036%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1
|
|
SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O
|
|
net (fo=32, routed) 0.987 24.398 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0
|
|
SLICE_X117Y153 f u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/I2
|
|
SLICE_X117Y153 LUT4 (Prop_lut4_I2_O) 0.124 24.522 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/O
|
|
net (fo=1, routed) 0.718 25.239 u_cpu/id_stage/ds_to_es_bus_r[185]_i_7_n_0
|
|
SLICE_X117Y156 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/I2
|
|
SLICE_X117Y156 LUT4 (Prop_lut4_I2_O) 0.124 25.363 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/O
|
|
net (fo=1, routed) 0.823 26.187 u_cpu/id_stage/ds_to_es_bus_r[185]_i_3_n_0
|
|
SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/I2
|
|
SLICE_X112Y158 LUT6 (Prop_lut6_I2_O) 0.124 26.311 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/O
|
|
net (fo=1, routed) 0.000 26.311 u_cpu/exe_stage/ds_to_es_bus[135]
|
|
SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.077 27.173 u_cpu/exe_stage/ds_to_es_bus_r_reg[185]
|
|
-------------------------------------------------------------------
|
|
required time 27.173
|
|
arrival time -26.311
|
|
-------------------------------------------------------------------
|
|
slack 0.863
|
|
|
|
Slack (MET) : 0.863ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.961ns (logic 7.809ns (26.964%) route 21.152ns (73.036%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1
|
|
SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O
|
|
net (fo=32, routed) 0.987 24.398 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0
|
|
SLICE_X117Y153 f u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/I2
|
|
SLICE_X117Y153 LUT4 (Prop_lut4_I2_O) 0.124 24.522 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/O
|
|
net (fo=1, routed) 0.718 25.239 u_cpu/id_stage/ds_to_es_bus_r[185]_i_7_n_0
|
|
SLICE_X117Y156 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/I2
|
|
SLICE_X117Y156 LUT4 (Prop_lut4_I2_O) 0.124 25.363 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/O
|
|
net (fo=1, routed) 0.823 26.187 u_cpu/id_stage/ds_to_es_bus_r[185]_i_3_n_0
|
|
SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/I2
|
|
SLICE_X112Y158 LUT6 (Prop_lut6_I2_O) 0.124 26.311 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/O
|
|
net (fo=1, routed) 0.000 26.311 u_cpu/exe_stage/ds_to_es_bus[135]
|
|
SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.077 27.173 u_cpu/exe_stage/ds_to_es_bus_r_reg[185]
|
|
-------------------------------------------------------------------
|
|
required time 27.173
|
|
arrival time -26.311
|
|
-------------------------------------------------------------------
|
|
slack 0.863
|
|
|
|
Slack (MET) : 0.863ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.961ns (logic 7.809ns (26.964%) route 21.152ns (73.036%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1
|
|
SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O
|
|
net (fo=32, routed) 0.987 24.398 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0
|
|
SLICE_X117Y153 f u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/I2
|
|
SLICE_X117Y153 LUT4 (Prop_lut4_I2_O) 0.124 24.522 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/O
|
|
net (fo=1, routed) 0.718 25.239 u_cpu/id_stage/ds_to_es_bus_r[185]_i_7_n_0
|
|
SLICE_X117Y156 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/I2
|
|
SLICE_X117Y156 LUT4 (Prop_lut4_I2_O) 0.124 25.363 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/O
|
|
net (fo=1, routed) 0.823 26.187 u_cpu/id_stage/ds_to_es_bus_r[185]_i_3_n_0
|
|
SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/I2
|
|
SLICE_X112Y158 LUT6 (Prop_lut6_I2_O) 0.124 26.311 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/O
|
|
net (fo=1, routed) 0.000 26.311 u_cpu/exe_stage/ds_to_es_bus[135]
|
|
SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.077 27.173 u_cpu/exe_stage/ds_to_es_bus_r_reg[185]
|
|
-------------------------------------------------------------------
|
|
required time 27.173
|
|
arrival time -26.311
|
|
-------------------------------------------------------------------
|
|
slack 0.863
|
|
|
|
Slack (MET) : 0.863ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.961ns (logic 7.809ns (26.964%) route 21.152ns (73.036%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1
|
|
SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O
|
|
net (fo=32, routed) 0.987 24.398 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0
|
|
SLICE_X117Y153 f u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/I2
|
|
SLICE_X117Y153 LUT4 (Prop_lut4_I2_O) 0.124 24.522 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/O
|
|
net (fo=1, routed) 0.718 25.239 u_cpu/id_stage/ds_to_es_bus_r[185]_i_7_n_0
|
|
SLICE_X117Y156 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/I2
|
|
SLICE_X117Y156 LUT4 (Prop_lut4_I2_O) 0.124 25.363 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/O
|
|
net (fo=1, routed) 0.823 26.187 u_cpu/id_stage/ds_to_es_bus_r[185]_i_3_n_0
|
|
SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/I2
|
|
SLICE_X112Y158 LUT6 (Prop_lut6_I2_O) 0.124 26.311 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/O
|
|
net (fo=1, routed) 0.000 26.311 u_cpu/exe_stage/ds_to_es_bus[135]
|
|
SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.077 27.173 u_cpu/exe_stage/ds_to_es_bus_r_reg[185]
|
|
-------------------------------------------------------------------
|
|
required time 27.173
|
|
arrival time -26.311
|
|
-------------------------------------------------------------------
|
|
slack 0.863
|
|
|
|
Slack (MET) : 0.863ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.961ns (logic 7.809ns (26.964%) route 21.152ns (73.036%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1
|
|
SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O
|
|
net (fo=32, routed) 0.987 24.398 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0
|
|
SLICE_X117Y153 f u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/I2
|
|
SLICE_X117Y153 LUT4 (Prop_lut4_I2_O) 0.124 24.522 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/O
|
|
net (fo=1, routed) 0.718 25.239 u_cpu/id_stage/ds_to_es_bus_r[185]_i_7_n_0
|
|
SLICE_X117Y156 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/I2
|
|
SLICE_X117Y156 LUT4 (Prop_lut4_I2_O) 0.124 25.363 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/O
|
|
net (fo=1, routed) 0.823 26.187 u_cpu/id_stage/ds_to_es_bus_r[185]_i_3_n_0
|
|
SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/I2
|
|
SLICE_X112Y158 LUT6 (Prop_lut6_I2_O) 0.124 26.311 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/O
|
|
net (fo=1, routed) 0.000 26.311 u_cpu/exe_stage/ds_to_es_bus[135]
|
|
SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.077 27.173 u_cpu/exe_stage/ds_to_es_bus_r_reg[185]
|
|
-------------------------------------------------------------------
|
|
required time 27.173
|
|
arrival time -26.311
|
|
-------------------------------------------------------------------
|
|
slack 0.863
|
|
|
|
Slack (MET) : 0.865ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.912ns (logic 8.037ns (27.799%) route 20.875ns (72.201%))
|
|
Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.141ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.492 23.006 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y154 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4
|
|
SLICE_X101Y154 LUT6 (Prop_lut6_I4_O) 0.124 23.130 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O
|
|
net (fo=32, routed) 1.058 24.188 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4
|
|
SLICE_X103Y151 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1
|
|
SLICE_X103Y151 LUT2 (Prop_lut2_I1_O) 0.150 24.338 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O
|
|
net (fo=1, routed) 1.172 25.510 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1
|
|
SLICE_X105Y151 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4
|
|
SLICE_X105Y151 LUT6 (Prop_lut6_I4_O) 0.326 25.836 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O
|
|
net (fo=1, routed) 0.301 26.137 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0
|
|
SLICE_X105Y150 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3
|
|
SLICE_X105Y150 LUT6 (Prop_lut6_I3_O) 0.124 26.261 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O
|
|
net (fo=1, routed) 0.000 26.261 u_cpu/exe_stage/ds_to_es_bus[114]
|
|
SLICE_X105Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.397 27.722
|
|
clock pessimism -0.514 27.209
|
|
clock uncertainty -0.113 27.095
|
|
SLICE_X105Y150 FDRE (Setup_fdre_C_D) 0.031 27.126 u_cpu/exe_stage/ds_to_es_bus_r_reg[164]
|
|
-------------------------------------------------------------------
|
|
required time 27.126
|
|
arrival time -26.261
|
|
-------------------------------------------------------------------
|
|
slack 0.865
|
|
|
|
Slack (MET) : 0.865ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.912ns (logic 8.037ns (27.799%) route 20.875ns (72.201%))
|
|
Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.141ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.492 23.006 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y154 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4
|
|
SLICE_X101Y154 LUT6 (Prop_lut6_I4_O) 0.124 23.130 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O
|
|
net (fo=32, routed) 1.058 24.188 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4
|
|
SLICE_X103Y151 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1
|
|
SLICE_X103Y151 LUT2 (Prop_lut2_I1_O) 0.150 24.338 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O
|
|
net (fo=1, routed) 1.172 25.510 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1
|
|
SLICE_X105Y151 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4
|
|
SLICE_X105Y151 LUT6 (Prop_lut6_I4_O) 0.326 25.836 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O
|
|
net (fo=1, routed) 0.301 26.137 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0
|
|
SLICE_X105Y150 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3
|
|
SLICE_X105Y150 LUT6 (Prop_lut6_I3_O) 0.124 26.261 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O
|
|
net (fo=1, routed) 0.000 26.261 u_cpu/exe_stage/ds_to_es_bus[114]
|
|
SLICE_X105Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.397 27.722
|
|
clock pessimism -0.514 27.209
|
|
clock uncertainty -0.113 27.095
|
|
SLICE_X105Y150 FDRE (Setup_fdre_C_D) 0.031 27.126 u_cpu/exe_stage/ds_to_es_bus_r_reg[164]
|
|
-------------------------------------------------------------------
|
|
required time 27.126
|
|
arrival time -26.261
|
|
-------------------------------------------------------------------
|
|
slack 0.865
|
|
|
|
Slack (MET) : 0.865ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.912ns (logic 8.037ns (27.799%) route 20.875ns (72.201%))
|
|
Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.141ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.492 23.006 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y154 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4
|
|
SLICE_X101Y154 LUT6 (Prop_lut6_I4_O) 0.124 23.130 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O
|
|
net (fo=32, routed) 1.058 24.188 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4
|
|
SLICE_X103Y151 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1
|
|
SLICE_X103Y151 LUT2 (Prop_lut2_I1_O) 0.150 24.338 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O
|
|
net (fo=1, routed) 1.172 25.510 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1
|
|
SLICE_X105Y151 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4
|
|
SLICE_X105Y151 LUT6 (Prop_lut6_I4_O) 0.326 25.836 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O
|
|
net (fo=1, routed) 0.301 26.137 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0
|
|
SLICE_X105Y150 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3
|
|
SLICE_X105Y150 LUT6 (Prop_lut6_I3_O) 0.124 26.261 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O
|
|
net (fo=1, routed) 0.000 26.261 u_cpu/exe_stage/ds_to_es_bus[114]
|
|
SLICE_X105Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.397 27.722
|
|
clock pessimism -0.514 27.209
|
|
clock uncertainty -0.113 27.095
|
|
SLICE_X105Y150 FDRE (Setup_fdre_C_D) 0.031 27.126 u_cpu/exe_stage/ds_to_es_bus_r_reg[164]
|
|
-------------------------------------------------------------------
|
|
required time 27.126
|
|
arrival time -26.261
|
|
-------------------------------------------------------------------
|
|
slack 0.865
|
|
|
|
Slack (MET) : 0.865ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.912ns (logic 8.037ns (27.799%) route 20.875ns (72.201%))
|
|
Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.141ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.492 23.006 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y154 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4
|
|
SLICE_X101Y154 LUT6 (Prop_lut6_I4_O) 0.124 23.130 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O
|
|
net (fo=32, routed) 1.058 24.188 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4
|
|
SLICE_X103Y151 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1
|
|
SLICE_X103Y151 LUT2 (Prop_lut2_I1_O) 0.150 24.338 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O
|
|
net (fo=1, routed) 1.172 25.510 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1
|
|
SLICE_X105Y151 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4
|
|
SLICE_X105Y151 LUT6 (Prop_lut6_I4_O) 0.326 25.836 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O
|
|
net (fo=1, routed) 0.301 26.137 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0
|
|
SLICE_X105Y150 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3
|
|
SLICE_X105Y150 LUT6 (Prop_lut6_I3_O) 0.124 26.261 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O
|
|
net (fo=1, routed) 0.000 26.261 u_cpu/exe_stage/ds_to_es_bus[114]
|
|
SLICE_X105Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.397 27.722
|
|
clock pessimism -0.514 27.209
|
|
clock uncertainty -0.113 27.095
|
|
SLICE_X105Y150 FDRE (Setup_fdre_C_D) 0.031 27.126 u_cpu/exe_stage/ds_to_es_bus_r_reg[164]
|
|
-------------------------------------------------------------------
|
|
required time 27.126
|
|
arrival time -26.261
|
|
-------------------------------------------------------------------
|
|
slack 0.865
|
|
|
|
Slack (MET) : 0.865ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.912ns (logic 8.037ns (27.799%) route 20.875ns (72.201%))
|
|
Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.141ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.492 23.006 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y154 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4
|
|
SLICE_X101Y154 LUT6 (Prop_lut6_I4_O) 0.124 23.130 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O
|
|
net (fo=32, routed) 1.058 24.188 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4
|
|
SLICE_X103Y151 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1
|
|
SLICE_X103Y151 LUT2 (Prop_lut2_I1_O) 0.150 24.338 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O
|
|
net (fo=1, routed) 1.172 25.510 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1
|
|
SLICE_X105Y151 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4
|
|
SLICE_X105Y151 LUT6 (Prop_lut6_I4_O) 0.326 25.836 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O
|
|
net (fo=1, routed) 0.301 26.137 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0
|
|
SLICE_X105Y150 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3
|
|
SLICE_X105Y150 LUT6 (Prop_lut6_I3_O) 0.124 26.261 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O
|
|
net (fo=1, routed) 0.000 26.261 u_cpu/exe_stage/ds_to_es_bus[114]
|
|
SLICE_X105Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.397 27.722
|
|
clock pessimism -0.514 27.209
|
|
clock uncertainty -0.113 27.095
|
|
SLICE_X105Y150 FDRE (Setup_fdre_C_D) 0.031 27.126 u_cpu/exe_stage/ds_to_es_bus_r_reg[164]
|
|
-------------------------------------------------------------------
|
|
required time 27.126
|
|
arrival time -26.261
|
|
-------------------------------------------------------------------
|
|
slack 0.865
|
|
|
|
Slack (MET) : 0.865ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.912ns (logic 8.037ns (27.799%) route 20.875ns (72.201%))
|
|
Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.141ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.492 23.006 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y154 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4
|
|
SLICE_X101Y154 LUT6 (Prop_lut6_I4_O) 0.124 23.130 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O
|
|
net (fo=32, routed) 1.058 24.188 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4
|
|
SLICE_X103Y151 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1
|
|
SLICE_X103Y151 LUT2 (Prop_lut2_I1_O) 0.150 24.338 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O
|
|
net (fo=1, routed) 1.172 25.510 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1
|
|
SLICE_X105Y151 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4
|
|
SLICE_X105Y151 LUT6 (Prop_lut6_I4_O) 0.326 25.836 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O
|
|
net (fo=1, routed) 0.301 26.137 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0
|
|
SLICE_X105Y150 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3
|
|
SLICE_X105Y150 LUT6 (Prop_lut6_I3_O) 0.124 26.261 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O
|
|
net (fo=1, routed) 0.000 26.261 u_cpu/exe_stage/ds_to_es_bus[114]
|
|
SLICE_X105Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.397 27.722
|
|
clock pessimism -0.514 27.209
|
|
clock uncertainty -0.113 27.095
|
|
SLICE_X105Y150 FDRE (Setup_fdre_C_D) 0.031 27.126 u_cpu/exe_stage/ds_to_es_bus_r_reg[164]
|
|
-------------------------------------------------------------------
|
|
required time 27.126
|
|
arrival time -26.261
|
|
-------------------------------------------------------------------
|
|
slack 0.865
|
|
|
|
Slack (MET) : 0.865ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.912ns (logic 8.037ns (27.799%) route 20.875ns (72.201%))
|
|
Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.141ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.492 23.006 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y154 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4
|
|
SLICE_X101Y154 LUT6 (Prop_lut6_I4_O) 0.124 23.130 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O
|
|
net (fo=32, routed) 1.058 24.188 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4
|
|
SLICE_X103Y151 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1
|
|
SLICE_X103Y151 LUT2 (Prop_lut2_I1_O) 0.150 24.338 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O
|
|
net (fo=1, routed) 1.172 25.510 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1
|
|
SLICE_X105Y151 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4
|
|
SLICE_X105Y151 LUT6 (Prop_lut6_I4_O) 0.326 25.836 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O
|
|
net (fo=1, routed) 0.301 26.137 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0
|
|
SLICE_X105Y150 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3
|
|
SLICE_X105Y150 LUT6 (Prop_lut6_I3_O) 0.124 26.261 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O
|
|
net (fo=1, routed) 0.000 26.261 u_cpu/exe_stage/ds_to_es_bus[114]
|
|
SLICE_X105Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.397 27.722
|
|
clock pessimism -0.514 27.209
|
|
clock uncertainty -0.113 27.095
|
|
SLICE_X105Y150 FDRE (Setup_fdre_C_D) 0.031 27.126 u_cpu/exe_stage/ds_to_es_bus_r_reg[164]
|
|
-------------------------------------------------------------------
|
|
required time 27.126
|
|
arrival time -26.261
|
|
-------------------------------------------------------------------
|
|
slack 0.865
|
|
|
|
Slack (MET) : 0.865ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.912ns (logic 8.037ns (27.799%) route 20.875ns (72.201%))
|
|
Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.141ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.492 23.006 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y154 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4
|
|
SLICE_X101Y154 LUT6 (Prop_lut6_I4_O) 0.124 23.130 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O
|
|
net (fo=32, routed) 1.058 24.188 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4
|
|
SLICE_X103Y151 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1
|
|
SLICE_X103Y151 LUT2 (Prop_lut2_I1_O) 0.150 24.338 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O
|
|
net (fo=1, routed) 1.172 25.510 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1
|
|
SLICE_X105Y151 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4
|
|
SLICE_X105Y151 LUT6 (Prop_lut6_I4_O) 0.326 25.836 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O
|
|
net (fo=1, routed) 0.301 26.137 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0
|
|
SLICE_X105Y150 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3
|
|
SLICE_X105Y150 LUT6 (Prop_lut6_I3_O) 0.124 26.261 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O
|
|
net (fo=1, routed) 0.000 26.261 u_cpu/exe_stage/ds_to_es_bus[114]
|
|
SLICE_X105Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.397 27.722
|
|
clock pessimism -0.514 27.209
|
|
clock uncertainty -0.113 27.095
|
|
SLICE_X105Y150 FDRE (Setup_fdre_C_D) 0.031 27.126 u_cpu/exe_stage/ds_to_es_bus_r_reg[164]
|
|
-------------------------------------------------------------------
|
|
required time 27.126
|
|
arrival time -26.261
|
|
-------------------------------------------------------------------
|
|
slack 0.865
|
|
|
|
Slack (MET) : 0.865ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.912ns (logic 8.037ns (27.799%) route 20.875ns (72.201%))
|
|
Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.141ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.492 23.006 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y154 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4
|
|
SLICE_X101Y154 LUT6 (Prop_lut6_I4_O) 0.124 23.130 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O
|
|
net (fo=32, routed) 1.058 24.188 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4
|
|
SLICE_X103Y151 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1
|
|
SLICE_X103Y151 LUT2 (Prop_lut2_I1_O) 0.150 24.338 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O
|
|
net (fo=1, routed) 1.172 25.510 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1
|
|
SLICE_X105Y151 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4
|
|
SLICE_X105Y151 LUT6 (Prop_lut6_I4_O) 0.326 25.836 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O
|
|
net (fo=1, routed) 0.301 26.137 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0
|
|
SLICE_X105Y150 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3
|
|
SLICE_X105Y150 LUT6 (Prop_lut6_I3_O) 0.124 26.261 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O
|
|
net (fo=1, routed) 0.000 26.261 u_cpu/exe_stage/ds_to_es_bus[114]
|
|
SLICE_X105Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.397 27.722
|
|
clock pessimism -0.514 27.209
|
|
clock uncertainty -0.113 27.095
|
|
SLICE_X105Y150 FDRE (Setup_fdre_C_D) 0.031 27.126 u_cpu/exe_stage/ds_to_es_bus_r_reg[164]
|
|
-------------------------------------------------------------------
|
|
required time 27.126
|
|
arrival time -26.261
|
|
-------------------------------------------------------------------
|
|
slack 0.865
|
|
|
|
Slack (MET) : 0.865ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.912ns (logic 8.037ns (27.799%) route 20.875ns (72.201%))
|
|
Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.141ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.492 23.006 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y154 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4
|
|
SLICE_X101Y154 LUT6 (Prop_lut6_I4_O) 0.124 23.130 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O
|
|
net (fo=32, routed) 1.058 24.188 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4
|
|
SLICE_X103Y151 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1
|
|
SLICE_X103Y151 LUT2 (Prop_lut2_I1_O) 0.150 24.338 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O
|
|
net (fo=1, routed) 1.172 25.510 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1
|
|
SLICE_X105Y151 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4
|
|
SLICE_X105Y151 LUT6 (Prop_lut6_I4_O) 0.326 25.836 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O
|
|
net (fo=1, routed) 0.301 26.137 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0
|
|
SLICE_X105Y150 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3
|
|
SLICE_X105Y150 LUT6 (Prop_lut6_I3_O) 0.124 26.261 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O
|
|
net (fo=1, routed) 0.000 26.261 u_cpu/exe_stage/ds_to_es_bus[114]
|
|
SLICE_X105Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.397 27.722
|
|
clock pessimism -0.514 27.209
|
|
clock uncertainty -0.113 27.095
|
|
SLICE_X105Y150 FDRE (Setup_fdre_C_D) 0.031 27.126 u_cpu/exe_stage/ds_to_es_bus_r_reg[164]
|
|
-------------------------------------------------------------------
|
|
required time 27.126
|
|
arrival time -26.261
|
|
-------------------------------------------------------------------
|
|
slack 0.865
|
|
|
|
Slack (MET) : 0.867ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.906ns (logic 7.809ns (27.015%) route 21.097ns (72.985%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.143ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 1.026 24.185 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X115Y152 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/I0
|
|
SLICE_X115Y152 LUT6 (Prop_lut6_I0_O) 0.124 24.309 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O
|
|
net (fo=15, routed) 0.796 25.105 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0
|
|
SLICE_X116Y153 f u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/I5
|
|
SLICE_X116Y153 LUT6 (Prop_lut6_I5_O) 0.124 25.229 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O
|
|
net (fo=1, routed) 0.902 26.131 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0
|
|
SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/I1
|
|
SLICE_X110Y160 LUT5 (Prop_lut5_I1_O) 0.124 26.255 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O
|
|
net (fo=1, routed) 0.000 26.255 u_cpu/exe_stage/ds_to_es_bus[140]
|
|
SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.395 27.720
|
|
clock pessimism -0.514 27.207
|
|
clock uncertainty -0.113 27.093
|
|
SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.029 27.122 u_cpu/exe_stage/ds_to_es_bus_r_reg[190]
|
|
-------------------------------------------------------------------
|
|
required time 27.122
|
|
arrival time -26.255
|
|
-------------------------------------------------------------------
|
|
slack 0.867
|
|
|
|
Slack (MET) : 0.867ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.906ns (logic 7.809ns (27.015%) route 21.097ns (72.985%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.143ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 1.026 24.185 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X115Y152 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/I0
|
|
SLICE_X115Y152 LUT6 (Prop_lut6_I0_O) 0.124 24.309 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O
|
|
net (fo=15, routed) 0.796 25.105 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0
|
|
SLICE_X116Y153 f u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/I5
|
|
SLICE_X116Y153 LUT6 (Prop_lut6_I5_O) 0.124 25.229 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O
|
|
net (fo=1, routed) 0.902 26.131 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0
|
|
SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/I1
|
|
SLICE_X110Y160 LUT5 (Prop_lut5_I1_O) 0.124 26.255 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O
|
|
net (fo=1, routed) 0.000 26.255 u_cpu/exe_stage/ds_to_es_bus[140]
|
|
SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.395 27.720
|
|
clock pessimism -0.514 27.207
|
|
clock uncertainty -0.113 27.093
|
|
SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.029 27.122 u_cpu/exe_stage/ds_to_es_bus_r_reg[190]
|
|
-------------------------------------------------------------------
|
|
required time 27.122
|
|
arrival time -26.255
|
|
-------------------------------------------------------------------
|
|
slack 0.867
|
|
|
|
Slack (MET) : 0.867ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.906ns (logic 7.809ns (27.015%) route 21.097ns (72.985%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.143ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 1.026 24.185 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X115Y152 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/I0
|
|
SLICE_X115Y152 LUT6 (Prop_lut6_I0_O) 0.124 24.309 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O
|
|
net (fo=15, routed) 0.796 25.105 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0
|
|
SLICE_X116Y153 f u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/I5
|
|
SLICE_X116Y153 LUT6 (Prop_lut6_I5_O) 0.124 25.229 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O
|
|
net (fo=1, routed) 0.902 26.131 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0
|
|
SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/I1
|
|
SLICE_X110Y160 LUT5 (Prop_lut5_I1_O) 0.124 26.255 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O
|
|
net (fo=1, routed) 0.000 26.255 u_cpu/exe_stage/ds_to_es_bus[140]
|
|
SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.395 27.720
|
|
clock pessimism -0.514 27.207
|
|
clock uncertainty -0.113 27.093
|
|
SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.029 27.122 u_cpu/exe_stage/ds_to_es_bus_r_reg[190]
|
|
-------------------------------------------------------------------
|
|
required time 27.122
|
|
arrival time -26.255
|
|
-------------------------------------------------------------------
|
|
slack 0.867
|
|
|
|
Slack (MET) : 0.867ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.906ns (logic 7.809ns (27.015%) route 21.097ns (72.985%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.143ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 1.026 24.185 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X115Y152 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/I0
|
|
SLICE_X115Y152 LUT6 (Prop_lut6_I0_O) 0.124 24.309 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O
|
|
net (fo=15, routed) 0.796 25.105 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0
|
|
SLICE_X116Y153 f u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/I5
|
|
SLICE_X116Y153 LUT6 (Prop_lut6_I5_O) 0.124 25.229 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O
|
|
net (fo=1, routed) 0.902 26.131 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0
|
|
SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/I1
|
|
SLICE_X110Y160 LUT5 (Prop_lut5_I1_O) 0.124 26.255 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O
|
|
net (fo=1, routed) 0.000 26.255 u_cpu/exe_stage/ds_to_es_bus[140]
|
|
SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.395 27.720
|
|
clock pessimism -0.514 27.207
|
|
clock uncertainty -0.113 27.093
|
|
SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.029 27.122 u_cpu/exe_stage/ds_to_es_bus_r_reg[190]
|
|
-------------------------------------------------------------------
|
|
required time 27.122
|
|
arrival time -26.255
|
|
-------------------------------------------------------------------
|
|
slack 0.867
|
|
|
|
Slack (MET) : 0.867ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.906ns (logic 7.809ns (27.015%) route 21.097ns (72.985%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.143ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 1.026 24.185 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X115Y152 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/I0
|
|
SLICE_X115Y152 LUT6 (Prop_lut6_I0_O) 0.124 24.309 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O
|
|
net (fo=15, routed) 0.796 25.105 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0
|
|
SLICE_X116Y153 f u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/I5
|
|
SLICE_X116Y153 LUT6 (Prop_lut6_I5_O) 0.124 25.229 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O
|
|
net (fo=1, routed) 0.902 26.131 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0
|
|
SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/I1
|
|
SLICE_X110Y160 LUT5 (Prop_lut5_I1_O) 0.124 26.255 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O
|
|
net (fo=1, routed) 0.000 26.255 u_cpu/exe_stage/ds_to_es_bus[140]
|
|
SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.395 27.720
|
|
clock pessimism -0.514 27.207
|
|
clock uncertainty -0.113 27.093
|
|
SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.029 27.122 u_cpu/exe_stage/ds_to_es_bus_r_reg[190]
|
|
-------------------------------------------------------------------
|
|
required time 27.122
|
|
arrival time -26.255
|
|
-------------------------------------------------------------------
|
|
slack 0.867
|
|
|
|
Slack (MET) : 0.867ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.906ns (logic 7.809ns (27.015%) route 21.097ns (72.985%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.143ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 1.026 24.185 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X115Y152 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/I0
|
|
SLICE_X115Y152 LUT6 (Prop_lut6_I0_O) 0.124 24.309 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O
|
|
net (fo=15, routed) 0.796 25.105 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0
|
|
SLICE_X116Y153 f u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/I5
|
|
SLICE_X116Y153 LUT6 (Prop_lut6_I5_O) 0.124 25.229 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O
|
|
net (fo=1, routed) 0.902 26.131 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0
|
|
SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/I1
|
|
SLICE_X110Y160 LUT5 (Prop_lut5_I1_O) 0.124 26.255 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O
|
|
net (fo=1, routed) 0.000 26.255 u_cpu/exe_stage/ds_to_es_bus[140]
|
|
SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.395 27.720
|
|
clock pessimism -0.514 27.207
|
|
clock uncertainty -0.113 27.093
|
|
SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.029 27.122 u_cpu/exe_stage/ds_to_es_bus_r_reg[190]
|
|
-------------------------------------------------------------------
|
|
required time 27.122
|
|
arrival time -26.255
|
|
-------------------------------------------------------------------
|
|
slack 0.867
|
|
|
|
Slack (MET) : 0.867ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.906ns (logic 7.809ns (27.015%) route 21.097ns (72.985%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.143ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 1.026 24.185 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X115Y152 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/I0
|
|
SLICE_X115Y152 LUT6 (Prop_lut6_I0_O) 0.124 24.309 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O
|
|
net (fo=15, routed) 0.796 25.105 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0
|
|
SLICE_X116Y153 f u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/I5
|
|
SLICE_X116Y153 LUT6 (Prop_lut6_I5_O) 0.124 25.229 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O
|
|
net (fo=1, routed) 0.902 26.131 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0
|
|
SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/I1
|
|
SLICE_X110Y160 LUT5 (Prop_lut5_I1_O) 0.124 26.255 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O
|
|
net (fo=1, routed) 0.000 26.255 u_cpu/exe_stage/ds_to_es_bus[140]
|
|
SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.395 27.720
|
|
clock pessimism -0.514 27.207
|
|
clock uncertainty -0.113 27.093
|
|
SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.029 27.122 u_cpu/exe_stage/ds_to_es_bus_r_reg[190]
|
|
-------------------------------------------------------------------
|
|
required time 27.122
|
|
arrival time -26.255
|
|
-------------------------------------------------------------------
|
|
slack 0.867
|
|
|
|
Slack (MET) : 0.867ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.906ns (logic 7.809ns (27.015%) route 21.097ns (72.985%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.143ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 1.026 24.185 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X115Y152 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/I0
|
|
SLICE_X115Y152 LUT6 (Prop_lut6_I0_O) 0.124 24.309 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O
|
|
net (fo=15, routed) 0.796 25.105 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0
|
|
SLICE_X116Y153 f u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/I5
|
|
SLICE_X116Y153 LUT6 (Prop_lut6_I5_O) 0.124 25.229 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O
|
|
net (fo=1, routed) 0.902 26.131 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0
|
|
SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/I1
|
|
SLICE_X110Y160 LUT5 (Prop_lut5_I1_O) 0.124 26.255 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O
|
|
net (fo=1, routed) 0.000 26.255 u_cpu/exe_stage/ds_to_es_bus[140]
|
|
SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.395 27.720
|
|
clock pessimism -0.514 27.207
|
|
clock uncertainty -0.113 27.093
|
|
SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.029 27.122 u_cpu/exe_stage/ds_to_es_bus_r_reg[190]
|
|
-------------------------------------------------------------------
|
|
required time 27.122
|
|
arrival time -26.255
|
|
-------------------------------------------------------------------
|
|
slack 0.867
|
|
|
|
Slack (MET) : 0.867ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.906ns (logic 7.809ns (27.015%) route 21.097ns (72.985%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.143ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 1.026 24.185 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X115Y152 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/I0
|
|
SLICE_X115Y152 LUT6 (Prop_lut6_I0_O) 0.124 24.309 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O
|
|
net (fo=15, routed) 0.796 25.105 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0
|
|
SLICE_X116Y153 f u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/I5
|
|
SLICE_X116Y153 LUT6 (Prop_lut6_I5_O) 0.124 25.229 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O
|
|
net (fo=1, routed) 0.902 26.131 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0
|
|
SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/I1
|
|
SLICE_X110Y160 LUT5 (Prop_lut5_I1_O) 0.124 26.255 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O
|
|
net (fo=1, routed) 0.000 26.255 u_cpu/exe_stage/ds_to_es_bus[140]
|
|
SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.395 27.720
|
|
clock pessimism -0.514 27.207
|
|
clock uncertainty -0.113 27.093
|
|
SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.029 27.122 u_cpu/exe_stage/ds_to_es_bus_r_reg[190]
|
|
-------------------------------------------------------------------
|
|
required time 27.122
|
|
arrival time -26.255
|
|
-------------------------------------------------------------------
|
|
slack 0.867
|
|
|
|
Slack (MET) : 0.867ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.906ns (logic 7.809ns (27.015%) route 21.097ns (72.985%))
|
|
Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.143ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 1.026 24.185 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X115Y152 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/I0
|
|
SLICE_X115Y152 LUT6 (Prop_lut6_I0_O) 0.124 24.309 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O
|
|
net (fo=15, routed) 0.796 25.105 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0
|
|
SLICE_X116Y153 f u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/I5
|
|
SLICE_X116Y153 LUT6 (Prop_lut6_I5_O) 0.124 25.229 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O
|
|
net (fo=1, routed) 0.902 26.131 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0
|
|
SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/I1
|
|
SLICE_X110Y160 LUT5 (Prop_lut5_I1_O) 0.124 26.255 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O
|
|
net (fo=1, routed) 0.000 26.255 u_cpu/exe_stage/ds_to_es_bus[140]
|
|
SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.395 27.720
|
|
clock pessimism -0.514 27.207
|
|
clock uncertainty -0.113 27.093
|
|
SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.029 27.122 u_cpu/exe_stage/ds_to_es_bus_r_reg[190]
|
|
-------------------------------------------------------------------
|
|
required time 27.122
|
|
arrival time -26.255
|
|
-------------------------------------------------------------------
|
|
slack 0.867
|
|
|
|
Slack (MET) : 0.894ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.883ns (logic 8.039ns (27.833%) route 20.844ns (72.167%))
|
|
Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0
|
|
SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O
|
|
net (fo=27, routed) 0.878 25.101 u_cpu/u_csr/ds_to_es_bus_r_reg[162]_0
|
|
SLICE_X109Y152 f u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/I1
|
|
SLICE_X109Y152 LUT2 (Prop_lut2_I1_O) 0.152 25.253 r u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/O
|
|
net (fo=1, routed) 0.654 25.907 u_cpu/id_stage/ds_to_es_bus_r_reg[171]
|
|
SLICE_X109Y151 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/I2
|
|
SLICE_X109Y151 LUT6 (Prop_lut6_I2_O) 0.326 26.233 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/O
|
|
net (fo=1, routed) 0.000 26.233 u_cpu/exe_stage/ds_to_es_bus[121]
|
|
SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X109Y151 FDRE (Setup_fdre_C_D) 0.031 27.127 u_cpu/exe_stage/ds_to_es_bus_r_reg[171]
|
|
-------------------------------------------------------------------
|
|
required time 27.127
|
|
arrival time -26.233
|
|
-------------------------------------------------------------------
|
|
slack 0.894
|
|
|
|
Slack (MET) : 0.894ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.883ns (logic 8.039ns (27.833%) route 20.844ns (72.167%))
|
|
Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0
|
|
SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O
|
|
net (fo=27, routed) 0.878 25.101 u_cpu/u_csr/ds_to_es_bus_r_reg[162]_0
|
|
SLICE_X109Y152 f u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/I1
|
|
SLICE_X109Y152 LUT2 (Prop_lut2_I1_O) 0.152 25.253 r u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/O
|
|
net (fo=1, routed) 0.654 25.907 u_cpu/id_stage/ds_to_es_bus_r_reg[171]
|
|
SLICE_X109Y151 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/I2
|
|
SLICE_X109Y151 LUT6 (Prop_lut6_I2_O) 0.326 26.233 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/O
|
|
net (fo=1, routed) 0.000 26.233 u_cpu/exe_stage/ds_to_es_bus[121]
|
|
SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X109Y151 FDRE (Setup_fdre_C_D) 0.031 27.127 u_cpu/exe_stage/ds_to_es_bus_r_reg[171]
|
|
-------------------------------------------------------------------
|
|
required time 27.127
|
|
arrival time -26.233
|
|
-------------------------------------------------------------------
|
|
slack 0.894
|
|
|
|
Slack (MET) : 0.894ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.883ns (logic 8.039ns (27.833%) route 20.844ns (72.167%))
|
|
Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0
|
|
SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O
|
|
net (fo=27, routed) 0.878 25.101 u_cpu/u_csr/ds_to_es_bus_r_reg[162]_0
|
|
SLICE_X109Y152 f u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/I1
|
|
SLICE_X109Y152 LUT2 (Prop_lut2_I1_O) 0.152 25.253 r u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/O
|
|
net (fo=1, routed) 0.654 25.907 u_cpu/id_stage/ds_to_es_bus_r_reg[171]
|
|
SLICE_X109Y151 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/I2
|
|
SLICE_X109Y151 LUT6 (Prop_lut6_I2_O) 0.326 26.233 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/O
|
|
net (fo=1, routed) 0.000 26.233 u_cpu/exe_stage/ds_to_es_bus[121]
|
|
SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X109Y151 FDRE (Setup_fdre_C_D) 0.031 27.127 u_cpu/exe_stage/ds_to_es_bus_r_reg[171]
|
|
-------------------------------------------------------------------
|
|
required time 27.127
|
|
arrival time -26.233
|
|
-------------------------------------------------------------------
|
|
slack 0.894
|
|
|
|
Slack (MET) : 0.894ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.883ns (logic 8.039ns (27.833%) route 20.844ns (72.167%))
|
|
Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0
|
|
SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O
|
|
net (fo=27, routed) 0.878 25.101 u_cpu/u_csr/ds_to_es_bus_r_reg[162]_0
|
|
SLICE_X109Y152 f u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/I1
|
|
SLICE_X109Y152 LUT2 (Prop_lut2_I1_O) 0.152 25.253 r u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/O
|
|
net (fo=1, routed) 0.654 25.907 u_cpu/id_stage/ds_to_es_bus_r_reg[171]
|
|
SLICE_X109Y151 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/I2
|
|
SLICE_X109Y151 LUT6 (Prop_lut6_I2_O) 0.326 26.233 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/O
|
|
net (fo=1, routed) 0.000 26.233 u_cpu/exe_stage/ds_to_es_bus[121]
|
|
SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X109Y151 FDRE (Setup_fdre_C_D) 0.031 27.127 u_cpu/exe_stage/ds_to_es_bus_r_reg[171]
|
|
-------------------------------------------------------------------
|
|
required time 27.127
|
|
arrival time -26.233
|
|
-------------------------------------------------------------------
|
|
slack 0.894
|
|
|
|
Slack (MET) : 0.894ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.883ns (logic 8.039ns (27.833%) route 20.844ns (72.167%))
|
|
Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0
|
|
SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O
|
|
net (fo=27, routed) 0.878 25.101 u_cpu/u_csr/ds_to_es_bus_r_reg[162]_0
|
|
SLICE_X109Y152 f u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/I1
|
|
SLICE_X109Y152 LUT2 (Prop_lut2_I1_O) 0.152 25.253 r u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/O
|
|
net (fo=1, routed) 0.654 25.907 u_cpu/id_stage/ds_to_es_bus_r_reg[171]
|
|
SLICE_X109Y151 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/I2
|
|
SLICE_X109Y151 LUT6 (Prop_lut6_I2_O) 0.326 26.233 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/O
|
|
net (fo=1, routed) 0.000 26.233 u_cpu/exe_stage/ds_to_es_bus[121]
|
|
SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X109Y151 FDRE (Setup_fdre_C_D) 0.031 27.127 u_cpu/exe_stage/ds_to_es_bus_r_reg[171]
|
|
-------------------------------------------------------------------
|
|
required time 27.127
|
|
arrival time -26.233
|
|
-------------------------------------------------------------------
|
|
slack 0.894
|
|
|
|
Slack (MET) : 0.894ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.883ns (logic 8.039ns (27.833%) route 20.844ns (72.167%))
|
|
Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0
|
|
SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O
|
|
net (fo=27, routed) 0.878 25.101 u_cpu/u_csr/ds_to_es_bus_r_reg[162]_0
|
|
SLICE_X109Y152 f u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/I1
|
|
SLICE_X109Y152 LUT2 (Prop_lut2_I1_O) 0.152 25.253 r u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/O
|
|
net (fo=1, routed) 0.654 25.907 u_cpu/id_stage/ds_to_es_bus_r_reg[171]
|
|
SLICE_X109Y151 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/I2
|
|
SLICE_X109Y151 LUT6 (Prop_lut6_I2_O) 0.326 26.233 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/O
|
|
net (fo=1, routed) 0.000 26.233 u_cpu/exe_stage/ds_to_es_bus[121]
|
|
SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X109Y151 FDRE (Setup_fdre_C_D) 0.031 27.127 u_cpu/exe_stage/ds_to_es_bus_r_reg[171]
|
|
-------------------------------------------------------------------
|
|
required time 27.127
|
|
arrival time -26.233
|
|
-------------------------------------------------------------------
|
|
slack 0.894
|
|
|
|
Slack (MET) : 0.894ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.883ns (logic 8.039ns (27.833%) route 20.844ns (72.167%))
|
|
Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0
|
|
SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O
|
|
net (fo=27, routed) 0.878 25.101 u_cpu/u_csr/ds_to_es_bus_r_reg[162]_0
|
|
SLICE_X109Y152 f u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/I1
|
|
SLICE_X109Y152 LUT2 (Prop_lut2_I1_O) 0.152 25.253 r u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/O
|
|
net (fo=1, routed) 0.654 25.907 u_cpu/id_stage/ds_to_es_bus_r_reg[171]
|
|
SLICE_X109Y151 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/I2
|
|
SLICE_X109Y151 LUT6 (Prop_lut6_I2_O) 0.326 26.233 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/O
|
|
net (fo=1, routed) 0.000 26.233 u_cpu/exe_stage/ds_to_es_bus[121]
|
|
SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X109Y151 FDRE (Setup_fdre_C_D) 0.031 27.127 u_cpu/exe_stage/ds_to_es_bus_r_reg[171]
|
|
-------------------------------------------------------------------
|
|
required time 27.127
|
|
arrival time -26.233
|
|
-------------------------------------------------------------------
|
|
slack 0.894
|
|
|
|
Slack (MET) : 0.894ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.883ns (logic 8.039ns (27.833%) route 20.844ns (72.167%))
|
|
Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0
|
|
SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O
|
|
net (fo=27, routed) 0.878 25.101 u_cpu/u_csr/ds_to_es_bus_r_reg[162]_0
|
|
SLICE_X109Y152 f u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/I1
|
|
SLICE_X109Y152 LUT2 (Prop_lut2_I1_O) 0.152 25.253 r u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/O
|
|
net (fo=1, routed) 0.654 25.907 u_cpu/id_stage/ds_to_es_bus_r_reg[171]
|
|
SLICE_X109Y151 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/I2
|
|
SLICE_X109Y151 LUT6 (Prop_lut6_I2_O) 0.326 26.233 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/O
|
|
net (fo=1, routed) 0.000 26.233 u_cpu/exe_stage/ds_to_es_bus[121]
|
|
SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X109Y151 FDRE (Setup_fdre_C_D) 0.031 27.127 u_cpu/exe_stage/ds_to_es_bus_r_reg[171]
|
|
-------------------------------------------------------------------
|
|
required time 27.127
|
|
arrival time -26.233
|
|
-------------------------------------------------------------------
|
|
slack 0.894
|
|
|
|
Slack (MET) : 0.894ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.883ns (logic 8.039ns (27.833%) route 20.844ns (72.167%))
|
|
Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0
|
|
SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O
|
|
net (fo=27, routed) 0.878 25.101 u_cpu/u_csr/ds_to_es_bus_r_reg[162]_0
|
|
SLICE_X109Y152 f u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/I1
|
|
SLICE_X109Y152 LUT2 (Prop_lut2_I1_O) 0.152 25.253 r u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/O
|
|
net (fo=1, routed) 0.654 25.907 u_cpu/id_stage/ds_to_es_bus_r_reg[171]
|
|
SLICE_X109Y151 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/I2
|
|
SLICE_X109Y151 LUT6 (Prop_lut6_I2_O) 0.326 26.233 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/O
|
|
net (fo=1, routed) 0.000 26.233 u_cpu/exe_stage/ds_to_es_bus[121]
|
|
SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X109Y151 FDRE (Setup_fdre_C_D) 0.031 27.127 u_cpu/exe_stage/ds_to_es_bus_r_reg[171]
|
|
-------------------------------------------------------------------
|
|
required time 27.127
|
|
arrival time -26.233
|
|
-------------------------------------------------------------------
|
|
slack 0.894
|
|
|
|
Slack (MET) : 0.894ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.883ns (logic 8.039ns (27.833%) route 20.844ns (72.167%))
|
|
Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0
|
|
SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O
|
|
net (fo=27, routed) 0.878 25.101 u_cpu/u_csr/ds_to_es_bus_r_reg[162]_0
|
|
SLICE_X109Y152 f u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/I1
|
|
SLICE_X109Y152 LUT2 (Prop_lut2_I1_O) 0.152 25.253 r u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/O
|
|
net (fo=1, routed) 0.654 25.907 u_cpu/id_stage/ds_to_es_bus_r_reg[171]
|
|
SLICE_X109Y151 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/I2
|
|
SLICE_X109Y151 LUT6 (Prop_lut6_I2_O) 0.326 26.233 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/O
|
|
net (fo=1, routed) 0.000 26.233 u_cpu/exe_stage/ds_to_es_bus[121]
|
|
SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.398 27.723
|
|
clock pessimism -0.514 27.210
|
|
clock uncertainty -0.113 27.096
|
|
SLICE_X109Y151 FDRE (Setup_fdre_C_D) 0.031 27.127 u_cpu/exe_stage/ds_to_es_bus_r_reg[171]
|
|
-------------------------------------------------------------------
|
|
required time 27.127
|
|
arrival time -26.233
|
|
-------------------------------------------------------------------
|
|
slack 0.894
|
|
|
|
Slack (MET) : 0.921ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.855ns (logic 8.026ns (27.815%) route 20.829ns (72.185%))
|
|
Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.142ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 0.661 23.820 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X111Y153 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/I0
|
|
SLICE_X111Y153 LUT6 (Prop_lut6_I0_O) 0.124 23.944 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/O
|
|
net (fo=22, routed) 0.870 24.814 u_cpu/u_csr/ds_to_es_bus_r_reg[172]
|
|
SLICE_X112Y150 f u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/I1
|
|
SLICE_X112Y150 LUT2 (Prop_lut2_I1_O) 0.117 24.931 r u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/O
|
|
net (fo=1, routed) 0.925 25.856 u_cpu/id_stage/ds_to_es_bus_r_reg[172]
|
|
SLICE_X105Y154 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/I2
|
|
SLICE_X105Y154 LUT6 (Prop_lut6_I2_O) 0.348 26.204 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/O
|
|
net (fo=1, routed) 0.000 26.204 u_cpu/exe_stage/ds_to_es_bus[122]
|
|
SLICE_X105Y154 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.396 27.721
|
|
clock pessimism -0.514 27.208
|
|
clock uncertainty -0.113 27.094
|
|
SLICE_X105Y154 FDRE (Setup_fdre_C_D) 0.031 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[172]
|
|
-------------------------------------------------------------------
|
|
required time 27.125
|
|
arrival time -26.204
|
|
-------------------------------------------------------------------
|
|
slack 0.921
|
|
|
|
Slack (MET) : 0.921ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.855ns (logic 8.026ns (27.815%) route 20.829ns (72.185%))
|
|
Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.142ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 0.661 23.820 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X111Y153 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/I0
|
|
SLICE_X111Y153 LUT6 (Prop_lut6_I0_O) 0.124 23.944 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/O
|
|
net (fo=22, routed) 0.870 24.814 u_cpu/u_csr/ds_to_es_bus_r_reg[172]
|
|
SLICE_X112Y150 f u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/I1
|
|
SLICE_X112Y150 LUT2 (Prop_lut2_I1_O) 0.117 24.931 r u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/O
|
|
net (fo=1, routed) 0.925 25.856 u_cpu/id_stage/ds_to_es_bus_r_reg[172]
|
|
SLICE_X105Y154 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/I2
|
|
SLICE_X105Y154 LUT6 (Prop_lut6_I2_O) 0.348 26.204 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/O
|
|
net (fo=1, routed) 0.000 26.204 u_cpu/exe_stage/ds_to_es_bus[122]
|
|
SLICE_X105Y154 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.396 27.721
|
|
clock pessimism -0.514 27.208
|
|
clock uncertainty -0.113 27.094
|
|
SLICE_X105Y154 FDRE (Setup_fdre_C_D) 0.031 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[172]
|
|
-------------------------------------------------------------------
|
|
required time 27.125
|
|
arrival time -26.204
|
|
-------------------------------------------------------------------
|
|
slack 0.921
|
|
|
|
Slack (MET) : 0.921ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.855ns (logic 8.026ns (27.815%) route 20.829ns (72.185%))
|
|
Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.142ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 0.661 23.820 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X111Y153 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/I0
|
|
SLICE_X111Y153 LUT6 (Prop_lut6_I0_O) 0.124 23.944 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/O
|
|
net (fo=22, routed) 0.870 24.814 u_cpu/u_csr/ds_to_es_bus_r_reg[172]
|
|
SLICE_X112Y150 f u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/I1
|
|
SLICE_X112Y150 LUT2 (Prop_lut2_I1_O) 0.117 24.931 r u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/O
|
|
net (fo=1, routed) 0.925 25.856 u_cpu/id_stage/ds_to_es_bus_r_reg[172]
|
|
SLICE_X105Y154 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/I2
|
|
SLICE_X105Y154 LUT6 (Prop_lut6_I2_O) 0.348 26.204 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/O
|
|
net (fo=1, routed) 0.000 26.204 u_cpu/exe_stage/ds_to_es_bus[122]
|
|
SLICE_X105Y154 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.396 27.721
|
|
clock pessimism -0.514 27.208
|
|
clock uncertainty -0.113 27.094
|
|
SLICE_X105Y154 FDRE (Setup_fdre_C_D) 0.031 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[172]
|
|
-------------------------------------------------------------------
|
|
required time 27.125
|
|
arrival time -26.204
|
|
-------------------------------------------------------------------
|
|
slack 0.921
|
|
|
|
Slack (MET) : 0.921ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.855ns (logic 8.026ns (27.815%) route 20.829ns (72.185%))
|
|
Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.142ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 0.661 23.820 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X111Y153 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/I0
|
|
SLICE_X111Y153 LUT6 (Prop_lut6_I0_O) 0.124 23.944 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/O
|
|
net (fo=22, routed) 0.870 24.814 u_cpu/u_csr/ds_to_es_bus_r_reg[172]
|
|
SLICE_X112Y150 f u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/I1
|
|
SLICE_X112Y150 LUT2 (Prop_lut2_I1_O) 0.117 24.931 r u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/O
|
|
net (fo=1, routed) 0.925 25.856 u_cpu/id_stage/ds_to_es_bus_r_reg[172]
|
|
SLICE_X105Y154 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/I2
|
|
SLICE_X105Y154 LUT6 (Prop_lut6_I2_O) 0.348 26.204 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/O
|
|
net (fo=1, routed) 0.000 26.204 u_cpu/exe_stage/ds_to_es_bus[122]
|
|
SLICE_X105Y154 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.396 27.721
|
|
clock pessimism -0.514 27.208
|
|
clock uncertainty -0.113 27.094
|
|
SLICE_X105Y154 FDRE (Setup_fdre_C_D) 0.031 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[172]
|
|
-------------------------------------------------------------------
|
|
required time 27.125
|
|
arrival time -26.204
|
|
-------------------------------------------------------------------
|
|
slack 0.921
|
|
|
|
Slack (MET) : 0.921ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.855ns (logic 8.026ns (27.815%) route 20.829ns (72.185%))
|
|
Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.142ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 0.661 23.820 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X111Y153 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/I0
|
|
SLICE_X111Y153 LUT6 (Prop_lut6_I0_O) 0.124 23.944 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/O
|
|
net (fo=22, routed) 0.870 24.814 u_cpu/u_csr/ds_to_es_bus_r_reg[172]
|
|
SLICE_X112Y150 f u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/I1
|
|
SLICE_X112Y150 LUT2 (Prop_lut2_I1_O) 0.117 24.931 r u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/O
|
|
net (fo=1, routed) 0.925 25.856 u_cpu/id_stage/ds_to_es_bus_r_reg[172]
|
|
SLICE_X105Y154 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/I2
|
|
SLICE_X105Y154 LUT6 (Prop_lut6_I2_O) 0.348 26.204 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/O
|
|
net (fo=1, routed) 0.000 26.204 u_cpu/exe_stage/ds_to_es_bus[122]
|
|
SLICE_X105Y154 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.396 27.721
|
|
clock pessimism -0.514 27.208
|
|
clock uncertainty -0.113 27.094
|
|
SLICE_X105Y154 FDRE (Setup_fdre_C_D) 0.031 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[172]
|
|
-------------------------------------------------------------------
|
|
required time 27.125
|
|
arrival time -26.204
|
|
-------------------------------------------------------------------
|
|
slack 0.921
|
|
|
|
Slack (MET) : 0.921ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.855ns (logic 8.026ns (27.815%) route 20.829ns (72.185%))
|
|
Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.142ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 0.661 23.820 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X111Y153 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/I0
|
|
SLICE_X111Y153 LUT6 (Prop_lut6_I0_O) 0.124 23.944 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/O
|
|
net (fo=22, routed) 0.870 24.814 u_cpu/u_csr/ds_to_es_bus_r_reg[172]
|
|
SLICE_X112Y150 f u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/I1
|
|
SLICE_X112Y150 LUT2 (Prop_lut2_I1_O) 0.117 24.931 r u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/O
|
|
net (fo=1, routed) 0.925 25.856 u_cpu/id_stage/ds_to_es_bus_r_reg[172]
|
|
SLICE_X105Y154 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/I2
|
|
SLICE_X105Y154 LUT6 (Prop_lut6_I2_O) 0.348 26.204 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/O
|
|
net (fo=1, routed) 0.000 26.204 u_cpu/exe_stage/ds_to_es_bus[122]
|
|
SLICE_X105Y154 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.396 27.721
|
|
clock pessimism -0.514 27.208
|
|
clock uncertainty -0.113 27.094
|
|
SLICE_X105Y154 FDRE (Setup_fdre_C_D) 0.031 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[172]
|
|
-------------------------------------------------------------------
|
|
required time 27.125
|
|
arrival time -26.204
|
|
-------------------------------------------------------------------
|
|
slack 0.921
|
|
|
|
Slack (MET) : 0.921ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.855ns (logic 8.026ns (27.815%) route 20.829ns (72.185%))
|
|
Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.142ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 0.661 23.820 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X111Y153 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/I0
|
|
SLICE_X111Y153 LUT6 (Prop_lut6_I0_O) 0.124 23.944 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/O
|
|
net (fo=22, routed) 0.870 24.814 u_cpu/u_csr/ds_to_es_bus_r_reg[172]
|
|
SLICE_X112Y150 f u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/I1
|
|
SLICE_X112Y150 LUT2 (Prop_lut2_I1_O) 0.117 24.931 r u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/O
|
|
net (fo=1, routed) 0.925 25.856 u_cpu/id_stage/ds_to_es_bus_r_reg[172]
|
|
SLICE_X105Y154 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/I2
|
|
SLICE_X105Y154 LUT6 (Prop_lut6_I2_O) 0.348 26.204 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/O
|
|
net (fo=1, routed) 0.000 26.204 u_cpu/exe_stage/ds_to_es_bus[122]
|
|
SLICE_X105Y154 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.396 27.721
|
|
clock pessimism -0.514 27.208
|
|
clock uncertainty -0.113 27.094
|
|
SLICE_X105Y154 FDRE (Setup_fdre_C_D) 0.031 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[172]
|
|
-------------------------------------------------------------------
|
|
required time 27.125
|
|
arrival time -26.204
|
|
-------------------------------------------------------------------
|
|
slack 0.921
|
|
|
|
Slack (MET) : 0.921ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.855ns (logic 8.026ns (27.815%) route 20.829ns (72.185%))
|
|
Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.142ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 0.661 23.820 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X111Y153 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/I0
|
|
SLICE_X111Y153 LUT6 (Prop_lut6_I0_O) 0.124 23.944 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/O
|
|
net (fo=22, routed) 0.870 24.814 u_cpu/u_csr/ds_to_es_bus_r_reg[172]
|
|
SLICE_X112Y150 f u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/I1
|
|
SLICE_X112Y150 LUT2 (Prop_lut2_I1_O) 0.117 24.931 r u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/O
|
|
net (fo=1, routed) 0.925 25.856 u_cpu/id_stage/ds_to_es_bus_r_reg[172]
|
|
SLICE_X105Y154 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/I2
|
|
SLICE_X105Y154 LUT6 (Prop_lut6_I2_O) 0.348 26.204 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/O
|
|
net (fo=1, routed) 0.000 26.204 u_cpu/exe_stage/ds_to_es_bus[122]
|
|
SLICE_X105Y154 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.396 27.721
|
|
clock pessimism -0.514 27.208
|
|
clock uncertainty -0.113 27.094
|
|
SLICE_X105Y154 FDRE (Setup_fdre_C_D) 0.031 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[172]
|
|
-------------------------------------------------------------------
|
|
required time 27.125
|
|
arrival time -26.204
|
|
-------------------------------------------------------------------
|
|
slack 0.921
|
|
|
|
Slack (MET) : 0.921ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.855ns (logic 8.026ns (27.815%) route 20.829ns (72.185%))
|
|
Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.142ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 0.661 23.820 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X111Y153 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/I0
|
|
SLICE_X111Y153 LUT6 (Prop_lut6_I0_O) 0.124 23.944 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/O
|
|
net (fo=22, routed) 0.870 24.814 u_cpu/u_csr/ds_to_es_bus_r_reg[172]
|
|
SLICE_X112Y150 f u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/I1
|
|
SLICE_X112Y150 LUT2 (Prop_lut2_I1_O) 0.117 24.931 r u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/O
|
|
net (fo=1, routed) 0.925 25.856 u_cpu/id_stage/ds_to_es_bus_r_reg[172]
|
|
SLICE_X105Y154 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/I2
|
|
SLICE_X105Y154 LUT6 (Prop_lut6_I2_O) 0.348 26.204 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/O
|
|
net (fo=1, routed) 0.000 26.204 u_cpu/exe_stage/ds_to_es_bus[122]
|
|
SLICE_X105Y154 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.396 27.721
|
|
clock pessimism -0.514 27.208
|
|
clock uncertainty -0.113 27.094
|
|
SLICE_X105Y154 FDRE (Setup_fdre_C_D) 0.031 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[172]
|
|
-------------------------------------------------------------------
|
|
required time 27.125
|
|
arrival time -26.204
|
|
-------------------------------------------------------------------
|
|
slack 0.921
|
|
|
|
Slack (MET) : 0.921ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.855ns (logic 8.026ns (27.815%) route 20.829ns (72.185%))
|
|
Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.142ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 )
|
|
Source Clock Delay (SCD): -2.651ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.216ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.625 -2.651
|
|
SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C
|
|
SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q
|
|
net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0]
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1
|
|
SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O
|
|
net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0
|
|
SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0]
|
|
SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3]
|
|
net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0
|
|
SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3
|
|
SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S
|
|
SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O
|
|
net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0
|
|
SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0
|
|
SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O
|
|
net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0
|
|
SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0
|
|
SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O
|
|
net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0
|
|
SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5
|
|
SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O
|
|
net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0
|
|
SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5
|
|
SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O
|
|
net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0
|
|
SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3
|
|
SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O
|
|
net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14]
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2
|
|
SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
|
net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
|
SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1]
|
|
SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
|
net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
|
SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI
|
|
SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
|
net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
|
SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0
|
|
SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
|
net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
|
SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5
|
|
SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O
|
|
net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11]
|
|
SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1
|
|
SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O
|
|
net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0
|
|
SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0
|
|
SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O
|
|
net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36]
|
|
SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4
|
|
SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O
|
|
net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0
|
|
SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5
|
|
SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O
|
|
net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4]
|
|
SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2
|
|
SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O
|
|
net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0
|
|
SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1]
|
|
SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0
|
|
SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI
|
|
SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2
|
|
SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O
|
|
net (fo=20, routed) 0.661 23.820 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0
|
|
SLICE_X111Y153 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/I0
|
|
SLICE_X111Y153 LUT6 (Prop_lut6_I0_O) 0.124 23.944 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/O
|
|
net (fo=22, routed) 0.870 24.814 u_cpu/u_csr/ds_to_es_bus_r_reg[172]
|
|
SLICE_X112Y150 f u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/I1
|
|
SLICE_X112Y150 LUT2 (Prop_lut2_I1_O) 0.117 24.931 r u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/O
|
|
net (fo=1, routed) 0.925 25.856 u_cpu/id_stage/ds_to_es_bus_r_reg[172]
|
|
SLICE_X105Y154 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/I2
|
|
SLICE_X105Y154 LUT6 (Prop_lut6_I2_O) 0.348 26.204 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/O
|
|
net (fo=1, routed) 0.000 26.204 u_cpu/exe_stage/ds_to_es_bus[122]
|
|
SLICE_X105Y154 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.000 30.000 r
|
|
clock source latency -5.674 24.326
|
|
propagated clock network latency
|
|
3.396 27.721
|
|
clock pessimism -0.514 27.208
|
|
clock uncertainty -0.113 27.094
|
|
SLICE_X105Y154 FDRE (Setup_fdre_C_D) 0.031 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[172]
|
|
-------------------------------------------------------------------
|
|
required time 27.125
|
|
arrival time -26.204
|
|
-------------------------------------------------------------------
|
|
slack 0.921
|
|
|
|
Slack (MET) : 3.826ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][22]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.817ns (logic 0.642ns (7.282%) route 8.175ns (92.718%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.055ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 10.892 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.745 6.147 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X96Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][22]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.566 10.892
|
|
clock pessimism -0.507 10.385
|
|
clock uncertainty -0.093 10.292
|
|
SLICE_X96Y99 FDCE (Recov_fdce_C_CLR) -0.319 9.973 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][22]
|
|
-------------------------------------------------------------------
|
|
required time 9.973
|
|
arrival time -6.147
|
|
-------------------------------------------------------------------
|
|
slack 3.826
|
|
|
|
Slack (MET) : 3.860ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][5]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.747ns (logic 0.642ns (7.340%) route 8.105ns (92.660%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.061ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.102ns = ( 10.898 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.675 6.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X104Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][5]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.572 10.898
|
|
clock pessimism -0.507 10.391
|
|
clock uncertainty -0.093 10.298
|
|
SLICE_X104Y85 FDCE (Recov_fdce_C_CLR) -0.361 9.937 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][5]
|
|
-------------------------------------------------------------------
|
|
required time 9.937
|
|
arrival time -6.077
|
|
-------------------------------------------------------------------
|
|
slack 3.860
|
|
|
|
Slack (MET) : 3.902ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][26]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.747ns (logic 0.642ns (7.340%) route 8.105ns (92.660%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.061ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.102ns = ( 10.898 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.675 6.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X104Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][26]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.572 10.898
|
|
clock pessimism -0.507 10.391
|
|
clock uncertainty -0.093 10.298
|
|
SLICE_X104Y85 FDCE (Recov_fdce_C_CLR) -0.319 9.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][26]
|
|
-------------------------------------------------------------------
|
|
required time 9.979
|
|
arrival time -6.077
|
|
-------------------------------------------------------------------
|
|
slack 3.902
|
|
|
|
Slack (MET) : 4.068ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][22]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.485ns (logic 0.642ns (7.567%) route 7.843ns (92.433%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.051ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.413 5.815 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X95Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][22]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.562 10.888
|
|
clock pessimism -0.507 10.381
|
|
clock uncertainty -0.093 10.288
|
|
SLICE_X95Y99 FDCE (Recov_fdce_C_CLR) -0.405 9.883 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][22]
|
|
-------------------------------------------------------------------
|
|
required time 9.883
|
|
arrival time -5.815
|
|
-------------------------------------------------------------------
|
|
slack 4.068
|
|
|
|
Slack (MET) : 4.068ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][8]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.485ns (logic 0.642ns (7.567%) route 7.843ns (92.433%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.051ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.413 5.815 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X95Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][8]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.562 10.888
|
|
clock pessimism -0.507 10.381
|
|
clock uncertainty -0.093 10.288
|
|
SLICE_X95Y99 FDCE (Recov_fdce_C_CLR) -0.405 9.883 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][8]
|
|
-------------------------------------------------------------------
|
|
required time 9.883
|
|
arrival time -5.815
|
|
-------------------------------------------------------------------
|
|
slack 4.068
|
|
|
|
Slack (MET) : 4.068ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][9]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.485ns (logic 0.642ns (7.567%) route 7.843ns (92.433%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.051ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.413 5.815 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X95Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][9]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.562 10.888
|
|
clock pessimism -0.507 10.381
|
|
clock uncertainty -0.093 10.288
|
|
SLICE_X95Y99 FDCE (Recov_fdce_C_CLR) -0.405 9.883 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][9]
|
|
-------------------------------------------------------------------
|
|
required time 9.883
|
|
arrival time -5.815
|
|
-------------------------------------------------------------------
|
|
slack 4.068
|
|
|
|
Slack (MET) : 4.115ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][12]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.052ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X101Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][12]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.563 10.889
|
|
clock pessimism -0.507 10.382
|
|
clock uncertainty -0.093 10.289
|
|
SLICE_X101Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][12]
|
|
-------------------------------------------------------------------
|
|
required time 9.884
|
|
arrival time -5.769
|
|
-------------------------------------------------------------------
|
|
slack 4.115
|
|
|
|
Slack (MET) : 4.115ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][31]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.052ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X101Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][31]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.563 10.889
|
|
clock pessimism -0.507 10.382
|
|
clock uncertainty -0.093 10.289
|
|
SLICE_X101Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][31]
|
|
-------------------------------------------------------------------
|
|
required time 9.884
|
|
arrival time -5.769
|
|
-------------------------------------------------------------------
|
|
slack 4.115
|
|
|
|
Slack (MET) : 4.115ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][3]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.052ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X101Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.563 10.889
|
|
clock pessimism -0.507 10.382
|
|
clock uncertainty -0.093 10.289
|
|
SLICE_X101Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][3]
|
|
-------------------------------------------------------------------
|
|
required time 9.884
|
|
arrival time -5.769
|
|
-------------------------------------------------------------------
|
|
slack 4.115
|
|
|
|
Slack (MET) : 4.115ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][4]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.052ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X101Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.563 10.889
|
|
clock pessimism -0.507 10.382
|
|
clock uncertainty -0.093 10.289
|
|
SLICE_X101Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][4]
|
|
-------------------------------------------------------------------
|
|
required time 9.884
|
|
arrival time -5.769
|
|
-------------------------------------------------------------------
|
|
slack 4.115
|
|
|
|
Slack (MET) : 4.115ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][5]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.052ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X101Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][5]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.563 10.889
|
|
clock pessimism -0.507 10.382
|
|
clock uncertainty -0.093 10.289
|
|
SLICE_X101Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][5]
|
|
-------------------------------------------------------------------
|
|
required time 9.884
|
|
arrival time -5.769
|
|
-------------------------------------------------------------------
|
|
slack 4.115
|
|
|
|
Slack (MET) : 4.115ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][6]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.052ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X101Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][6]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.563 10.889
|
|
clock pessimism -0.507 10.382
|
|
clock uncertainty -0.093 10.289
|
|
SLICE_X101Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][6]
|
|
-------------------------------------------------------------------
|
|
required time 9.884
|
|
arrival time -5.769
|
|
-------------------------------------------------------------------
|
|
slack 4.115
|
|
|
|
Slack (MET) : 4.154ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][6]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.485ns (logic 0.642ns (7.567%) route 7.843ns (92.433%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.051ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.413 5.815 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X94Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][6]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.562 10.888
|
|
clock pessimism -0.507 10.381
|
|
clock uncertainty -0.093 10.288
|
|
SLICE_X94Y99 FDCE (Recov_fdce_C_CLR) -0.319 9.969 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][6]
|
|
-------------------------------------------------------------------
|
|
required time 9.969
|
|
arrival time -5.815
|
|
-------------------------------------------------------------------
|
|
slack 4.154
|
|
|
|
Slack (MET) : 4.154ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][8]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.485ns (logic 0.642ns (7.567%) route 7.843ns (92.433%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.051ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.413 5.815 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X94Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][8]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.562 10.888
|
|
clock pessimism -0.507 10.381
|
|
clock uncertainty -0.093 10.288
|
|
SLICE_X94Y99 FDCE (Recov_fdce_C_CLR) -0.319 9.969 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][8]
|
|
-------------------------------------------------------------------
|
|
required time 9.969
|
|
arrival time -5.815
|
|
-------------------------------------------------------------------
|
|
slack 4.154
|
|
|
|
Slack (MET) : 4.159ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][26]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.052ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X100Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][26]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.563 10.889
|
|
clock pessimism -0.507 10.382
|
|
clock uncertainty -0.093 10.289
|
|
SLICE_X100Y86 FDCE (Recov_fdce_C_CLR) -0.361 9.928 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][26]
|
|
-------------------------------------------------------------------
|
|
required time 9.928
|
|
arrival time -5.769
|
|
-------------------------------------------------------------------
|
|
slack 4.159
|
|
|
|
Slack (MET) : 4.201ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][25]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.052ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X100Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][25]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.563 10.889
|
|
clock pessimism -0.507 10.382
|
|
clock uncertainty -0.093 10.289
|
|
SLICE_X100Y86 FDCE (Recov_fdce_C_CLR) -0.319 9.970 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][25]
|
|
-------------------------------------------------------------------
|
|
required time 9.970
|
|
arrival time -5.769
|
|
-------------------------------------------------------------------
|
|
slack 4.201
|
|
|
|
Slack (MET) : 4.223ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][24]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.054ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X103Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][24]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.565 10.891
|
|
clock pessimism -0.507 10.384
|
|
clock uncertainty -0.093 10.291
|
|
SLICE_X103Y85 FDCE (Recov_fdce_C_CLR) -0.405 9.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][24]
|
|
-------------------------------------------------------------------
|
|
required time 9.886
|
|
arrival time -5.662
|
|
-------------------------------------------------------------------
|
|
slack 4.223
|
|
|
|
Slack (MET) : 4.223ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][27]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.054ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X103Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][27]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.565 10.891
|
|
clock pessimism -0.507 10.384
|
|
clock uncertainty -0.093 10.291
|
|
SLICE_X103Y85 FDCE (Recov_fdce_C_CLR) -0.405 9.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][27]
|
|
-------------------------------------------------------------------
|
|
required time 9.886
|
|
arrival time -5.662
|
|
-------------------------------------------------------------------
|
|
slack 4.223
|
|
|
|
Slack (MET) : 4.223ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][4]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.054ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X103Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.565 10.891
|
|
clock pessimism -0.507 10.384
|
|
clock uncertainty -0.093 10.291
|
|
SLICE_X103Y85 FDCE (Recov_fdce_C_CLR) -0.405 9.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][4]
|
|
-------------------------------------------------------------------
|
|
required time 9.886
|
|
arrival time -5.662
|
|
-------------------------------------------------------------------
|
|
slack 4.223
|
|
|
|
Slack (MET) : 4.223ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][7]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.054ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X103Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][7]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.565 10.891
|
|
clock pessimism -0.507 10.384
|
|
clock uncertainty -0.093 10.291
|
|
SLICE_X103Y85 FDCE (Recov_fdce_C_CLR) -0.405 9.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][7]
|
|
-------------------------------------------------------------------
|
|
required time 9.886
|
|
arrival time -5.662
|
|
-------------------------------------------------------------------
|
|
slack 4.223
|
|
|
|
Slack (MET) : 4.224ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][22]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.329ns (logic 0.642ns (7.708%) route 7.687ns (92.292%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.051ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.257 5.659 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X95Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][22]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.562 10.888
|
|
clock pessimism -0.507 10.381
|
|
clock uncertainty -0.093 10.288
|
|
SLICE_X95Y98 FDCE (Recov_fdce_C_CLR) -0.405 9.883 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][22]
|
|
-------------------------------------------------------------------
|
|
required time 9.883
|
|
arrival time -5.659
|
|
-------------------------------------------------------------------
|
|
slack 4.224
|
|
|
|
Slack (MET) : 4.224ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][6]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.329ns (logic 0.642ns (7.708%) route 7.687ns (92.292%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.051ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.257 5.659 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X95Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][6]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.562 10.888
|
|
clock pessimism -0.507 10.381
|
|
clock uncertainty -0.093 10.288
|
|
SLICE_X95Y98 FDCE (Recov_fdce_C_CLR) -0.405 9.883 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][6]
|
|
-------------------------------------------------------------------
|
|
required time 9.883
|
|
arrival time -5.659
|
|
-------------------------------------------------------------------
|
|
slack 4.224
|
|
|
|
Slack (MET) : 4.224ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][8]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.329ns (logic 0.642ns (7.708%) route 7.687ns (92.292%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.051ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.257 5.659 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X95Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][8]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.562 10.888
|
|
clock pessimism -0.507 10.381
|
|
clock uncertainty -0.093 10.288
|
|
SLICE_X95Y98 FDCE (Recov_fdce_C_CLR) -0.405 9.883 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][8]
|
|
-------------------------------------------------------------------
|
|
required time 9.883
|
|
arrival time -5.659
|
|
-------------------------------------------------------------------
|
|
slack 4.224
|
|
|
|
Slack (MET) : 4.275ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][13]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.277ns (logic 0.642ns (7.757%) route 7.635ns (92.243%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.050ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.113ns = ( 10.887 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.205 5.607 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X99Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][13]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.561 10.887
|
|
clock pessimism -0.507 10.380
|
|
clock uncertainty -0.093 10.287
|
|
SLICE_X99Y87 FDCE (Recov_fdce_C_CLR) -0.405 9.882 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][13]
|
|
-------------------------------------------------------------------
|
|
required time 9.882
|
|
arrival time -5.607
|
|
-------------------------------------------------------------------
|
|
slack 4.275
|
|
|
|
Slack (MET) : 4.275ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][2]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.277ns (logic 0.642ns (7.757%) route 7.635ns (92.243%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.050ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.113ns = ( 10.887 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.205 5.607 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X99Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.561 10.887
|
|
clock pessimism -0.507 10.380
|
|
clock uncertainty -0.093 10.287
|
|
SLICE_X99Y87 FDCE (Recov_fdce_C_CLR) -0.405 9.882 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][2]
|
|
-------------------------------------------------------------------
|
|
required time 9.882
|
|
arrival time -5.607
|
|
-------------------------------------------------------------------
|
|
slack 4.275
|
|
|
|
Slack (MET) : 4.275ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][3]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.277ns (logic 0.642ns (7.757%) route 7.635ns (92.243%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.050ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.113ns = ( 10.887 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.205 5.607 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X99Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.561 10.887
|
|
clock pessimism -0.507 10.380
|
|
clock uncertainty -0.093 10.287
|
|
SLICE_X99Y87 FDCE (Recov_fdce_C_CLR) -0.405 9.882 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][3]
|
|
-------------------------------------------------------------------
|
|
required time 9.882
|
|
arrival time -5.607
|
|
-------------------------------------------------------------------
|
|
slack 4.275
|
|
|
|
Slack (MET) : 4.305ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_sync_reg[2]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.172ns (logic 0.642ns (7.856%) route 7.530ns (92.144%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.025ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.277ns = ( 10.723 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.101 5.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X95Y101 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_sync_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.398 10.723
|
|
clock pessimism -0.418 10.305
|
|
clock uncertainty -0.093 10.212
|
|
SLICE_X95Y101 FDCE (Recov_fdce_C_CLR) -0.405 9.807 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_sync_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 9.807
|
|
arrival time -5.503
|
|
-------------------------------------------------------------------
|
|
slack 4.305
|
|
|
|
Slack (MET) : 4.309ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][24]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.054ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X102Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][24]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.565 10.891
|
|
clock pessimism -0.507 10.384
|
|
clock uncertainty -0.093 10.291
|
|
SLICE_X102Y85 FDCE (Recov_fdce_C_CLR) -0.319 9.972 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][24]
|
|
-------------------------------------------------------------------
|
|
required time 9.972
|
|
arrival time -5.662
|
|
-------------------------------------------------------------------
|
|
slack 4.309
|
|
|
|
Slack (MET) : 4.309ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][26]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.054ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X102Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][26]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.565 10.891
|
|
clock pessimism -0.507 10.384
|
|
clock uncertainty -0.093 10.291
|
|
SLICE_X102Y85 FDCE (Recov_fdce_C_CLR) -0.319 9.972 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][26]
|
|
-------------------------------------------------------------------
|
|
required time 9.972
|
|
arrival time -5.662
|
|
-------------------------------------------------------------------
|
|
slack 4.309
|
|
|
|
Slack (MET) : 4.309ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][5]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.054ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X102Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][5]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.565 10.891
|
|
clock pessimism -0.507 10.384
|
|
clock uncertainty -0.093 10.291
|
|
SLICE_X102Y85 FDCE (Recov_fdce_C_CLR) -0.319 9.972 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][5]
|
|
-------------------------------------------------------------------
|
|
required time 9.972
|
|
arrival time -5.662
|
|
-------------------------------------------------------------------
|
|
slack 4.309
|
|
|
|
Slack (MET) : 4.309ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][7]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.054ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X102Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][7]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.565 10.891
|
|
clock pessimism -0.507 10.384
|
|
clock uncertainty -0.093 10.291
|
|
SLICE_X102Y85 FDCE (Recov_fdce_C_CLR) -0.319 9.972 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][7]
|
|
-------------------------------------------------------------------
|
|
required time 9.972
|
|
arrival time -5.662
|
|
-------------------------------------------------------------------
|
|
slack 4.309
|
|
|
|
Slack (MET) : 4.310ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][6]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.329ns (logic 0.642ns (7.708%) route 7.687ns (92.292%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.051ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.257 5.659 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X94Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][6]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.562 10.888
|
|
clock pessimism -0.507 10.381
|
|
clock uncertainty -0.093 10.288
|
|
SLICE_X94Y98 FDCE (Recov_fdce_C_CLR) -0.319 9.969 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][6]
|
|
-------------------------------------------------------------------
|
|
required time 9.969
|
|
arrival time -5.659
|
|
-------------------------------------------------------------------
|
|
slack 4.310
|
|
|
|
Slack (MET) : 4.319ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][19]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.277ns (logic 0.642ns (7.757%) route 7.635ns (92.243%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.050ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.113ns = ( 10.887 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.205 5.607 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X98Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][19]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.561 10.887
|
|
clock pessimism -0.507 10.380
|
|
clock uncertainty -0.093 10.287
|
|
SLICE_X98Y87 FDCE (Recov_fdce_C_CLR) -0.361 9.926 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][19]
|
|
-------------------------------------------------------------------
|
|
required time 9.926
|
|
arrival time -5.607
|
|
-------------------------------------------------------------------
|
|
slack 4.319
|
|
|
|
Slack (MET) : 4.319ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][2]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.277ns (logic 0.642ns (7.757%) route 7.635ns (92.243%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.050ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.113ns = ( 10.887 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.205 5.607 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X98Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.561 10.887
|
|
clock pessimism -0.507 10.380
|
|
clock uncertainty -0.093 10.287
|
|
SLICE_X98Y87 FDCE (Recov_fdce_C_CLR) -0.361 9.926 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][2]
|
|
-------------------------------------------------------------------
|
|
required time 9.926
|
|
arrival time -5.607
|
|
-------------------------------------------------------------------
|
|
slack 4.319
|
|
|
|
Slack (MET) : 4.361ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][12]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.277ns (logic 0.642ns (7.757%) route 7.635ns (92.243%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.050ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.113ns = ( 10.887 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.205 5.607 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X98Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][12]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.561 10.887
|
|
clock pessimism -0.507 10.380
|
|
clock uncertainty -0.093 10.287
|
|
SLICE_X98Y87 FDCE (Recov_fdce_C_CLR) -0.319 9.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][12]
|
|
-------------------------------------------------------------------
|
|
required time 9.968
|
|
arrival time -5.607
|
|
-------------------------------------------------------------------
|
|
slack 4.361
|
|
|
|
Slack (MET) : 4.361ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][29]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.277ns (logic 0.642ns (7.757%) route 7.635ns (92.243%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.050ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.113ns = ( 10.887 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.205 5.607 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X98Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][29]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.561 10.887
|
|
clock pessimism -0.507 10.380
|
|
clock uncertainty -0.093 10.287
|
|
SLICE_X98Y87 FDCE (Recov_fdce_C_CLR) -0.319 9.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][29]
|
|
-------------------------------------------------------------------
|
|
required time 9.968
|
|
arrival time -5.607
|
|
-------------------------------------------------------------------
|
|
slack 4.361
|
|
|
|
Slack (MET) : 4.382ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][25]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.173ns (logic 0.642ns (7.855%) route 7.531ns (92.145%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.053ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.110ns = ( 10.890 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.101 5.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X103Y84 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][25]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.564 10.890
|
|
clock pessimism -0.507 10.383
|
|
clock uncertainty -0.093 10.290
|
|
SLICE_X103Y84 FDCE (Recov_fdce_C_CLR) -0.405 9.885 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][25]
|
|
-------------------------------------------------------------------
|
|
required time 9.885
|
|
arrival time -5.503
|
|
-------------------------------------------------------------------
|
|
slack 4.382
|
|
|
|
Slack (MET) : 4.382ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][6]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.173ns (logic 0.642ns (7.855%) route 7.531ns (92.145%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.053ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.110ns = ( 10.890 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.101 5.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X103Y84 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][6]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.564 10.890
|
|
clock pessimism -0.507 10.383
|
|
clock uncertainty -0.093 10.290
|
|
SLICE_X103Y84 FDCE (Recov_fdce_C_CLR) -0.405 9.885 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][6]
|
|
-------------------------------------------------------------------
|
|
required time 9.885
|
|
arrival time -5.503
|
|
-------------------------------------------------------------------
|
|
slack 4.382
|
|
|
|
Slack (MET) : 4.406ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][25]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.145ns (logic 0.642ns (7.883%) route 7.503ns (92.117%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.049ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.073 5.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X99Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][25]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.560 10.886
|
|
clock pessimism -0.507 10.379
|
|
clock uncertainty -0.093 10.286
|
|
SLICE_X99Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][25]
|
|
-------------------------------------------------------------------
|
|
required time 9.881
|
|
arrival time -5.475
|
|
-------------------------------------------------------------------
|
|
slack 4.406
|
|
|
|
Slack (MET) : 4.406ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][28]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.145ns (logic 0.642ns (7.883%) route 7.503ns (92.117%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.049ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.073 5.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X99Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][28]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.560 10.886
|
|
clock pessimism -0.507 10.379
|
|
clock uncertainty -0.093 10.286
|
|
SLICE_X99Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][28]
|
|
-------------------------------------------------------------------
|
|
required time 9.881
|
|
arrival time -5.475
|
|
-------------------------------------------------------------------
|
|
slack 4.406
|
|
|
|
Slack (MET) : 4.406ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][2]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.145ns (logic 0.642ns (7.883%) route 7.503ns (92.117%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.049ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.073 5.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X99Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.560 10.886
|
|
clock pessimism -0.507 10.379
|
|
clock uncertainty -0.093 10.286
|
|
SLICE_X99Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][2]
|
|
-------------------------------------------------------------------
|
|
required time 9.881
|
|
arrival time -5.475
|
|
-------------------------------------------------------------------
|
|
slack 4.406
|
|
|
|
Slack (MET) : 4.406ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][3]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.145ns (logic 0.642ns (7.883%) route 7.503ns (92.117%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.049ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.073 5.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X99Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.560 10.886
|
|
clock pessimism -0.507 10.379
|
|
clock uncertainty -0.093 10.286
|
|
SLICE_X99Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][3]
|
|
-------------------------------------------------------------------
|
|
required time 9.881
|
|
arrival time -5.475
|
|
-------------------------------------------------------------------
|
|
slack 4.406
|
|
|
|
Slack (MET) : 4.420ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][12]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.134ns (logic 0.642ns (7.893%) route 7.492ns (92.107%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.053ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.110ns = ( 10.890 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.062 5.465 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X101Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][12]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.564 10.890
|
|
clock pessimism -0.507 10.383
|
|
clock uncertainty -0.093 10.290
|
|
SLICE_X101Y87 FDCE (Recov_fdce_C_CLR) -0.405 9.885 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][12]
|
|
-------------------------------------------------------------------
|
|
required time 9.885
|
|
arrival time -5.465
|
|
-------------------------------------------------------------------
|
|
slack 4.420
|
|
|
|
Slack (MET) : 4.420ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][20]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.134ns (logic 0.642ns (7.893%) route 7.492ns (92.107%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.053ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.110ns = ( 10.890 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.062 5.465 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X101Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][20]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.564 10.890
|
|
clock pessimism -0.507 10.383
|
|
clock uncertainty -0.093 10.290
|
|
SLICE_X101Y87 FDCE (Recov_fdce_C_CLR) -0.405 9.885 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][20]
|
|
-------------------------------------------------------------------
|
|
required time 9.885
|
|
arrival time -5.465
|
|
-------------------------------------------------------------------
|
|
slack 4.420
|
|
|
|
Slack (MET) : 4.420ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][3]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.134ns (logic 0.642ns (7.893%) route 7.492ns (92.107%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.053ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.110ns = ( 10.890 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.062 5.465 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X101Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.564 10.890
|
|
clock pessimism -0.507 10.383
|
|
clock uncertainty -0.093 10.290
|
|
SLICE_X101Y87 FDCE (Recov_fdce_C_CLR) -0.405 9.885 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][3]
|
|
-------------------------------------------------------------------
|
|
required time 9.885
|
|
arrival time -5.465
|
|
-------------------------------------------------------------------
|
|
slack 4.420
|
|
|
|
Slack (MET) : 4.430ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][2]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.120ns (logic 0.642ns (7.906%) route 7.478ns (92.094%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.049ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.048 5.450 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X97Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.560 10.886
|
|
clock pessimism -0.507 10.379
|
|
clock uncertainty -0.093 10.286
|
|
SLICE_X97Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][2]
|
|
-------------------------------------------------------------------
|
|
required time 9.881
|
|
arrival time -5.450
|
|
-------------------------------------------------------------------
|
|
slack 4.430
|
|
|
|
Slack (MET) : 4.430ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][31]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.120ns (logic 0.642ns (7.906%) route 7.478ns (92.094%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.049ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.048 5.450 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X97Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][31]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.560 10.886
|
|
clock pessimism -0.507 10.379
|
|
clock uncertainty -0.093 10.286
|
|
SLICE_X97Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][31]
|
|
-------------------------------------------------------------------
|
|
required time 9.881
|
|
arrival time -5.450
|
|
-------------------------------------------------------------------
|
|
slack 4.430
|
|
|
|
Slack (MET) : 4.430ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][7]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.120ns (logic 0.642ns (7.906%) route 7.478ns (92.094%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.049ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.048 5.450 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X97Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][7]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.560 10.886
|
|
clock pessimism -0.507 10.379
|
|
clock uncertainty -0.093 10.286
|
|
SLICE_X97Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][7]
|
|
-------------------------------------------------------------------
|
|
required time 9.881
|
|
arrival time -5.450
|
|
-------------------------------------------------------------------
|
|
slack 4.430
|
|
|
|
Slack (MET) : 4.430ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][8]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.120ns (logic 0.642ns (7.906%) route 7.478ns (92.094%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.049ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.048 5.450 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X97Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][8]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.560 10.886
|
|
clock pessimism -0.507 10.379
|
|
clock uncertainty -0.093 10.286
|
|
SLICE_X97Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][8]
|
|
-------------------------------------------------------------------
|
|
required time 9.881
|
|
arrival time -5.450
|
|
-------------------------------------------------------------------
|
|
slack 4.430
|
|
|
|
Slack (MET) : 4.450ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][3]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.145ns (logic 0.642ns (7.883%) route 7.503ns (92.117%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.049ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.073 5.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X98Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.560 10.886
|
|
clock pessimism -0.507 10.379
|
|
clock uncertainty -0.093 10.286
|
|
SLICE_X98Y86 FDCE (Recov_fdce_C_CLR) -0.361 9.925 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][3]
|
|
-------------------------------------------------------------------
|
|
required time 9.925
|
|
arrival time -5.475
|
|
-------------------------------------------------------------------
|
|
slack 4.450
|
|
|
|
Slack (MET) : 4.450ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][4]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.145ns (logic 0.642ns (7.883%) route 7.503ns (92.117%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.049ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.073 5.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X98Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.560 10.886
|
|
clock pessimism -0.507 10.379
|
|
clock uncertainty -0.093 10.286
|
|
SLICE_X98Y86 FDCE (Recov_fdce_C_CLR) -0.361 9.925 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][4]
|
|
-------------------------------------------------------------------
|
|
required time 9.925
|
|
arrival time -5.475
|
|
-------------------------------------------------------------------
|
|
slack 4.450
|
|
|
|
Slack (MET) : 4.474ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][9]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.120ns (logic 0.642ns (7.906%) route 7.478ns (92.094%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.049ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.048 5.450 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X96Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][9]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.560 10.886
|
|
clock pessimism -0.507 10.379
|
|
clock uncertainty -0.093 10.286
|
|
SLICE_X96Y86 FDCE (Recov_fdce_C_CLR) -0.361 9.925 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][9]
|
|
-------------------------------------------------------------------
|
|
required time 9.925
|
|
arrival time -5.450
|
|
-------------------------------------------------------------------
|
|
slack 4.474
|
|
|
|
Slack (MET) : 4.479ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][10]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.066ns (logic 0.642ns (7.959%) route 7.424ns (92.041%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.044ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.119ns = ( 10.881 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.995 5.397 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X89Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][10]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.555 10.881
|
|
clock pessimism -0.507 10.374
|
|
clock uncertainty -0.093 10.281
|
|
SLICE_X89Y99 FDCE (Recov_fdce_C_CLR) -0.405 9.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][10]
|
|
-------------------------------------------------------------------
|
|
required time 9.876
|
|
arrival time -5.397
|
|
-------------------------------------------------------------------
|
|
slack 4.479
|
|
|
|
Slack (MET) : 4.479ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][13]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.066ns (logic 0.642ns (7.959%) route 7.424ns (92.041%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.044ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.119ns = ( 10.881 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.995 5.397 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X89Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][13]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.555 10.881
|
|
clock pessimism -0.507 10.374
|
|
clock uncertainty -0.093 10.281
|
|
SLICE_X89Y99 FDCE (Recov_fdce_C_CLR) -0.405 9.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][13]
|
|
-------------------------------------------------------------------
|
|
required time 9.876
|
|
arrival time -5.397
|
|
-------------------------------------------------------------------
|
|
slack 4.479
|
|
|
|
Slack (MET) : 4.479ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][5]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.066ns (logic 0.642ns (7.959%) route 7.424ns (92.041%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.044ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.119ns = ( 10.881 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.995 5.397 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X89Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][5]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.555 10.881
|
|
clock pessimism -0.507 10.374
|
|
clock uncertainty -0.093 10.281
|
|
SLICE_X89Y99 FDCE (Recov_fdce_C_CLR) -0.405 9.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][5]
|
|
-------------------------------------------------------------------
|
|
required time 9.876
|
|
arrival time -5.397
|
|
-------------------------------------------------------------------
|
|
slack 4.479
|
|
|
|
Slack (MET) : 4.492ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][27]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.145ns (logic 0.642ns (7.883%) route 7.503ns (92.117%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.049ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.073 5.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X98Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][27]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.560 10.886
|
|
clock pessimism -0.507 10.379
|
|
clock uncertainty -0.093 10.286
|
|
SLICE_X98Y86 FDCE (Recov_fdce_C_CLR) -0.319 9.967 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][27]
|
|
-------------------------------------------------------------------
|
|
required time 9.967
|
|
arrival time -5.475
|
|
-------------------------------------------------------------------
|
|
slack 4.492
|
|
|
|
Slack (MET) : 4.492ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][28]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.145ns (logic 0.642ns (7.883%) route 7.503ns (92.117%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.049ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.073 5.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X98Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][28]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.560 10.886
|
|
clock pessimism -0.507 10.379
|
|
clock uncertainty -0.093 10.286
|
|
SLICE_X98Y86 FDCE (Recov_fdce_C_CLR) -0.319 9.967 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][28]
|
|
-------------------------------------------------------------------
|
|
required time 9.967
|
|
arrival time -5.475
|
|
-------------------------------------------------------------------
|
|
slack 4.492
|
|
|
|
Slack (MET) : 4.506ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][12]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.134ns (logic 0.642ns (7.893%) route 7.492ns (92.107%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.053ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.110ns = ( 10.890 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.062 5.465 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X100Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][12]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.564 10.890
|
|
clock pessimism -0.507 10.383
|
|
clock uncertainty -0.093 10.290
|
|
SLICE_X100Y87 FDCE (Recov_fdce_C_CLR) -0.319 9.971 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][12]
|
|
-------------------------------------------------------------------
|
|
required time 9.971
|
|
arrival time -5.465
|
|
-------------------------------------------------------------------
|
|
slack 4.506
|
|
|
|
Slack (MET) : 4.506ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][4]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.134ns (logic 0.642ns (7.893%) route 7.492ns (92.107%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.053ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.110ns = ( 10.890 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.062 5.465 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X100Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.564 10.890
|
|
clock pessimism -0.507 10.383
|
|
clock uncertainty -0.093 10.290
|
|
SLICE_X100Y87 FDCE (Recov_fdce_C_CLR) -0.319 9.971 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][4]
|
|
-------------------------------------------------------------------
|
|
required time 9.971
|
|
arrival time -5.465
|
|
-------------------------------------------------------------------
|
|
slack 4.506
|
|
|
|
Slack (MET) : 4.508ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][12]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.044ns (logic 0.642ns (7.981%) route 7.402ns (92.019%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.051ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.973 5.375 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X95Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][12]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.562 10.888
|
|
clock pessimism -0.507 10.381
|
|
clock uncertainty -0.093 10.288
|
|
SLICE_X95Y97 FDCE (Recov_fdce_C_CLR) -0.405 9.883 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][12]
|
|
-------------------------------------------------------------------
|
|
required time 9.883
|
|
arrival time -5.375
|
|
-------------------------------------------------------------------
|
|
slack 4.508
|
|
|
|
Slack (MET) : 4.508ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][4]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.044ns (logic 0.642ns (7.981%) route 7.402ns (92.019%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.051ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.973 5.375 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X95Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.562 10.888
|
|
clock pessimism -0.507 10.381
|
|
clock uncertainty -0.093 10.288
|
|
SLICE_X95Y97 FDCE (Recov_fdce_C_CLR) -0.405 9.883 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][4]
|
|
-------------------------------------------------------------------
|
|
required time 9.883
|
|
arrival time -5.375
|
|
-------------------------------------------------------------------
|
|
slack 4.508
|
|
|
|
Slack (MET) : 4.512ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][31]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.127ns (logic 0.642ns (7.900%) route 7.485ns (92.100%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.051ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.055 5.457 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X100Y84 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][31]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.562 10.888
|
|
clock pessimism -0.507 10.381
|
|
clock uncertainty -0.093 10.288
|
|
SLICE_X100Y84 FDCE (Recov_fdce_C_CLR) -0.319 9.969 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][31]
|
|
-------------------------------------------------------------------
|
|
required time 9.969
|
|
arrival time -5.457
|
|
-------------------------------------------------------------------
|
|
slack 4.512
|
|
|
|
Slack (MET) : 4.512ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][4]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.127ns (logic 0.642ns (7.900%) route 7.485ns (92.100%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.051ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.055 5.457 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X100Y84 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.562 10.888
|
|
clock pessimism -0.507 10.381
|
|
clock uncertainty -0.093 10.288
|
|
SLICE_X100Y84 FDCE (Recov_fdce_C_CLR) -0.319 9.969 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][4]
|
|
-------------------------------------------------------------------
|
|
required time 9.969
|
|
arrival time -5.457
|
|
-------------------------------------------------------------------
|
|
slack 4.512
|
|
|
|
Slack (MET) : 4.512ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][6]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.127ns (logic 0.642ns (7.900%) route 7.485ns (92.100%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.051ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.055 5.457 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X100Y84 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][6]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.562 10.888
|
|
clock pessimism -0.507 10.381
|
|
clock uncertainty -0.093 10.288
|
|
SLICE_X100Y84 FDCE (Recov_fdce_C_CLR) -0.319 9.969 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][6]
|
|
-------------------------------------------------------------------
|
|
required time 9.969
|
|
arrival time -5.457
|
|
-------------------------------------------------------------------
|
|
slack 4.512
|
|
|
|
Slack (MET) : 4.516ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][18]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.120ns (logic 0.642ns (7.906%) route 7.478ns (92.094%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.049ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 5.048 5.450 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X96Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][18]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.560 10.886
|
|
clock pessimism -0.507 10.379
|
|
clock uncertainty -0.093 10.286
|
|
SLICE_X96Y86 FDCE (Recov_fdce_C_CLR) -0.319 9.967 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][18]
|
|
-------------------------------------------------------------------
|
|
required time 9.967
|
|
arrival time -5.450
|
|
-------------------------------------------------------------------
|
|
slack 4.516
|
|
|
|
Slack (MET) : 4.545ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][18]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.003ns (logic 0.642ns (8.022%) route 7.361ns (91.978%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.046ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.117ns = ( 10.883 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.931 5.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X95Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][18]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.557 10.883
|
|
clock pessimism -0.507 10.376
|
|
clock uncertainty -0.093 10.283
|
|
SLICE_X95Y87 FDCE (Recov_fdce_C_CLR) -0.405 9.878 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][18]
|
|
-------------------------------------------------------------------
|
|
required time 9.878
|
|
arrival time -5.333
|
|
-------------------------------------------------------------------
|
|
slack 4.545
|
|
|
|
Slack (MET) : 4.545ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][19]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.003ns (logic 0.642ns (8.022%) route 7.361ns (91.978%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.046ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.117ns = ( 10.883 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.931 5.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X95Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][19]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.557 10.883
|
|
clock pessimism -0.507 10.376
|
|
clock uncertainty -0.093 10.283
|
|
SLICE_X95Y87 FDCE (Recov_fdce_C_CLR) -0.405 9.878 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][19]
|
|
-------------------------------------------------------------------
|
|
required time 9.878
|
|
arrival time -5.333
|
|
-------------------------------------------------------------------
|
|
slack 4.545
|
|
|
|
Slack (MET) : 4.551ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][10]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 7.994ns (logic 0.642ns (8.031%) route 7.352ns (91.969%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.044ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.119ns = ( 10.881 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.922 5.325 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X89Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][10]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.555 10.881
|
|
clock pessimism -0.507 10.374
|
|
clock uncertainty -0.093 10.281
|
|
SLICE_X89Y97 FDCE (Recov_fdce_C_CLR) -0.405 9.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][10]
|
|
-------------------------------------------------------------------
|
|
required time 9.876
|
|
arrival time -5.325
|
|
-------------------------------------------------------------------
|
|
slack 4.551
|
|
|
|
Slack (MET) : 4.551ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][5]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 7.994ns (logic 0.642ns (8.031%) route 7.352ns (91.969%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.044ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.119ns = ( 10.881 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.922 5.325 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X89Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][5]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.555 10.881
|
|
clock pessimism -0.507 10.374
|
|
clock uncertainty -0.093 10.281
|
|
SLICE_X89Y97 FDCE (Recov_fdce_C_CLR) -0.405 9.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][5]
|
|
-------------------------------------------------------------------
|
|
required time 9.876
|
|
arrival time -5.325
|
|
-------------------------------------------------------------------
|
|
slack 4.551
|
|
|
|
Slack (MET) : 4.565ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][14]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.066ns (logic 0.642ns (7.959%) route 7.424ns (92.041%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.044ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.119ns = ( 10.881 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.995 5.397 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X88Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][14]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.555 10.881
|
|
clock pessimism -0.507 10.374
|
|
clock uncertainty -0.093 10.281
|
|
SLICE_X88Y99 FDCE (Recov_fdce_C_CLR) -0.319 9.962 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][14]
|
|
-------------------------------------------------------------------
|
|
required time 9.962
|
|
arrival time -5.397
|
|
-------------------------------------------------------------------
|
|
slack 4.565
|
|
|
|
Slack (MET) : 4.565ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][2]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.066ns (logic 0.642ns (7.959%) route 7.424ns (92.041%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.044ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.119ns = ( 10.881 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.995 5.397 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X88Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.555 10.881
|
|
clock pessimism -0.507 10.374
|
|
clock uncertainty -0.093 10.281
|
|
SLICE_X88Y99 FDCE (Recov_fdce_C_CLR) -0.319 9.962 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][2]
|
|
-------------------------------------------------------------------
|
|
required time 9.962
|
|
arrival time -5.397
|
|
-------------------------------------------------------------------
|
|
slack 4.565
|
|
|
|
Slack (MET) : 4.566ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][31]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.027ns (logic 0.642ns (7.998%) route 7.385ns (92.002%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.048ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.115ns = ( 10.885 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.955 5.358 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X98Y84 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][31]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.559 10.885
|
|
clock pessimism -0.507 10.378
|
|
clock uncertainty -0.093 10.285
|
|
SLICE_X98Y84 FDCE (Recov_fdce_C_CLR) -0.361 9.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][31]
|
|
-------------------------------------------------------------------
|
|
required time 9.924
|
|
arrival time -5.358
|
|
-------------------------------------------------------------------
|
|
slack 4.566
|
|
|
|
Slack (MET) : 4.566ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][3]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.027ns (logic 0.642ns (7.998%) route 7.385ns (92.002%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.048ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.115ns = ( 10.885 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.955 5.358 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X98Y84 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.559 10.885
|
|
clock pessimism -0.507 10.378
|
|
clock uncertainty -0.093 10.285
|
|
SLICE_X98Y84 FDCE (Recov_fdce_C_CLR) -0.361 9.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][3]
|
|
-------------------------------------------------------------------
|
|
required time 9.924
|
|
arrival time -5.358
|
|
-------------------------------------------------------------------
|
|
slack 4.566
|
|
|
|
Slack (MET) : 4.566ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][6]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.027ns (logic 0.642ns (7.998%) route 7.385ns (92.002%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.048ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.115ns = ( 10.885 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.955 5.358 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X98Y84 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][6]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.559 10.885
|
|
clock pessimism -0.507 10.378
|
|
clock uncertainty -0.093 10.285
|
|
SLICE_X98Y84 FDCE (Recov_fdce_C_CLR) -0.361 9.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][6]
|
|
-------------------------------------------------------------------
|
|
required time 9.924
|
|
arrival time -5.358
|
|
-------------------------------------------------------------------
|
|
slack 4.566
|
|
|
|
Slack (MET) : 4.594ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][20]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 7.954ns (logic 0.642ns (8.071%) route 7.312ns (91.929%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.047ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.116ns = ( 10.884 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.883 5.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X91Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][20]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.558 10.884
|
|
clock pessimism -0.507 10.377
|
|
clock uncertainty -0.093 10.284
|
|
SLICE_X91Y94 FDCE (Recov_fdce_C_CLR) -0.405 9.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][20]
|
|
-------------------------------------------------------------------
|
|
required time 9.879
|
|
arrival time -5.285
|
|
-------------------------------------------------------------------
|
|
slack 4.594
|
|
|
|
Slack (MET) : 4.594ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][21]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 7.954ns (logic 0.642ns (8.071%) route 7.312ns (91.929%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.047ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.116ns = ( 10.884 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.883 5.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X91Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][21]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.558 10.884
|
|
clock pessimism -0.507 10.377
|
|
clock uncertainty -0.093 10.284
|
|
SLICE_X91Y94 FDCE (Recov_fdce_C_CLR) -0.405 9.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][21]
|
|
-------------------------------------------------------------------
|
|
required time 9.879
|
|
arrival time -5.285
|
|
-------------------------------------------------------------------
|
|
slack 4.594
|
|
|
|
Slack (MET) : 4.594ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][23]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 7.954ns (logic 0.642ns (8.071%) route 7.312ns (91.929%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.047ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.116ns = ( 10.884 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.883 5.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X91Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][23]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.558 10.884
|
|
clock pessimism -0.507 10.377
|
|
clock uncertainty -0.093 10.284
|
|
SLICE_X91Y94 FDCE (Recov_fdce_C_CLR) -0.405 9.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][23]
|
|
-------------------------------------------------------------------
|
|
required time 9.879
|
|
arrival time -5.285
|
|
-------------------------------------------------------------------
|
|
slack 4.594
|
|
|
|
Slack (MET) : 4.594ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][7]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 7.954ns (logic 0.642ns (8.071%) route 7.312ns (91.929%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.047ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.116ns = ( 10.884 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.883 5.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X91Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][7]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.558 10.884
|
|
clock pessimism -0.507 10.377
|
|
clock uncertainty -0.093 10.284
|
|
SLICE_X91Y94 FDCE (Recov_fdce_C_CLR) -0.405 9.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][7]
|
|
-------------------------------------------------------------------
|
|
required time 9.879
|
|
arrival time -5.285
|
|
-------------------------------------------------------------------
|
|
slack 4.594
|
|
|
|
Slack (MET) : 4.594ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][12]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.044ns (logic 0.642ns (7.981%) route 7.402ns (92.019%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.051ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.973 5.375 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X94Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][12]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.562 10.888
|
|
clock pessimism -0.507 10.381
|
|
clock uncertainty -0.093 10.288
|
|
SLICE_X94Y97 FDCE (Recov_fdce_C_CLR) -0.319 9.969 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][12]
|
|
-------------------------------------------------------------------
|
|
required time 9.969
|
|
arrival time -5.375
|
|
-------------------------------------------------------------------
|
|
slack 4.594
|
|
|
|
Slack (MET) : 4.594ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][15]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.044ns (logic 0.642ns (7.981%) route 7.402ns (92.019%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.051ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.973 5.375 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X94Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][15]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.562 10.888
|
|
clock pessimism -0.507 10.381
|
|
clock uncertainty -0.093 10.288
|
|
SLICE_X94Y97 FDCE (Recov_fdce_C_CLR) -0.319 9.969 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][15]
|
|
-------------------------------------------------------------------
|
|
required time 9.969
|
|
arrival time -5.375
|
|
-------------------------------------------------------------------
|
|
slack 4.594
|
|
|
|
Slack (MET) : 4.594ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][22]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.044ns (logic 0.642ns (7.981%) route 7.402ns (92.019%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.051ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.973 5.375 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X94Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][22]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.562 10.888
|
|
clock pessimism -0.507 10.381
|
|
clock uncertainty -0.093 10.288
|
|
SLICE_X94Y97 FDCE (Recov_fdce_C_CLR) -0.319 9.969 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][22]
|
|
-------------------------------------------------------------------
|
|
required time 9.969
|
|
arrival time -5.375
|
|
-------------------------------------------------------------------
|
|
slack 4.594
|
|
|
|
Slack (MET) : 4.594ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][6]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.044ns (logic 0.642ns (7.981%) route 7.402ns (92.019%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.051ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.973 5.375 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X94Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][6]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.562 10.888
|
|
clock pessimism -0.507 10.381
|
|
clock uncertainty -0.093 10.288
|
|
SLICE_X94Y97 FDCE (Recov_fdce_C_CLR) -0.319 9.969 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][6]
|
|
-------------------------------------------------------------------
|
|
required time 9.969
|
|
arrival time -5.375
|
|
-------------------------------------------------------------------
|
|
slack 4.594
|
|
|
|
Slack (MET) : 4.608ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][25]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.027ns (logic 0.642ns (7.998%) route 7.385ns (92.002%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.048ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.115ns = ( 10.885 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.955 5.358 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X98Y84 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][25]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.559 10.885
|
|
clock pessimism -0.507 10.378
|
|
clock uncertainty -0.093 10.285
|
|
SLICE_X98Y84 FDCE (Recov_fdce_C_CLR) -0.319 9.966 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][25]
|
|
-------------------------------------------------------------------
|
|
required time 9.966
|
|
arrival time -5.358
|
|
-------------------------------------------------------------------
|
|
slack 4.608
|
|
|
|
Slack (MET) : 4.608ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][28]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.027ns (logic 0.642ns (7.998%) route 7.385ns (92.002%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.048ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.115ns = ( 10.885 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.955 5.358 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X98Y84 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][28]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.559 10.885
|
|
clock pessimism -0.507 10.378
|
|
clock uncertainty -0.093 10.285
|
|
SLICE_X98Y84 FDCE (Recov_fdce_C_CLR) -0.319 9.966 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][28]
|
|
-------------------------------------------------------------------
|
|
required time 9.966
|
|
arrival time -5.358
|
|
-------------------------------------------------------------------
|
|
slack 4.608
|
|
|
|
Slack (MET) : 4.608ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][2]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 8.027ns (logic 0.642ns (7.998%) route 7.385ns (92.002%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.048ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.115ns = ( 10.885 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.955 5.358 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X98Y84 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.559 10.885
|
|
clock pessimism -0.507 10.378
|
|
clock uncertainty -0.093 10.285
|
|
SLICE_X98Y84 FDCE (Recov_fdce_C_CLR) -0.319 9.966 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][2]
|
|
-------------------------------------------------------------------
|
|
required time 9.966
|
|
arrival time -5.358
|
|
-------------------------------------------------------------------
|
|
slack 4.608
|
|
|
|
Slack (MET) : 4.637ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][10]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 7.994ns (logic 0.642ns (8.031%) route 7.352ns (91.969%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.044ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.119ns = ( 10.881 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.922 5.325 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X88Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][10]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.555 10.881
|
|
clock pessimism -0.507 10.374
|
|
clock uncertainty -0.093 10.281
|
|
SLICE_X88Y97 FDCE (Recov_fdce_C_CLR) -0.319 9.962 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][10]
|
|
-------------------------------------------------------------------
|
|
required time 9.962
|
|
arrival time -5.325
|
|
-------------------------------------------------------------------
|
|
slack 4.637
|
|
|
|
Slack (MET) : 4.637ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][5]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 7.994ns (logic 0.642ns (8.031%) route 7.352ns (91.969%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.044ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.119ns = ( 10.881 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.922 5.325 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X88Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][5]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.555 10.881
|
|
clock pessimism -0.507 10.374
|
|
clock uncertainty -0.093 10.281
|
|
SLICE_X88Y97 FDCE (Recov_fdce_C_CLR) -0.319 9.962 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][5]
|
|
-------------------------------------------------------------------
|
|
required time 9.962
|
|
arrival time -5.325
|
|
-------------------------------------------------------------------
|
|
slack 4.637
|
|
|
|
Slack (MET) : 4.651ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][27]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 7.890ns (logic 0.642ns (8.137%) route 7.248ns (91.863%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.039ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.124ns = ( 10.876 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.818 5.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X89Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][27]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.550 10.876
|
|
clock pessimism -0.507 10.369
|
|
clock uncertainty -0.093 10.276
|
|
SLICE_X89Y87 FDCE (Recov_fdce_C_CLR) -0.405 9.871 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][27]
|
|
-------------------------------------------------------------------
|
|
required time 9.871
|
|
arrival time -5.220
|
|
-------------------------------------------------------------------
|
|
slack 4.651
|
|
|
|
Slack (MET) : 4.651ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][28]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 7.890ns (logic 0.642ns (8.137%) route 7.248ns (91.863%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.039ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.124ns = ( 10.876 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.818 5.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X89Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][28]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.550 10.876
|
|
clock pessimism -0.507 10.369
|
|
clock uncertainty -0.093 10.276
|
|
SLICE_X89Y87 FDCE (Recov_fdce_C_CLR) -0.405 9.871 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][28]
|
|
-------------------------------------------------------------------
|
|
required time 9.871
|
|
arrival time -5.220
|
|
-------------------------------------------------------------------
|
|
slack 4.651
|
|
|
|
Slack (MET) : 4.663ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][18]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 7.883ns (logic 0.642ns (8.144%) route 7.241ns (91.856%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.045ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.118ns = ( 10.882 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.812 5.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X95Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][18]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.556 10.882
|
|
clock pessimism -0.507 10.375
|
|
clock uncertainty -0.093 10.282
|
|
SLICE_X95Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.877 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][18]
|
|
-------------------------------------------------------------------
|
|
required time 9.877
|
|
arrival time -5.214
|
|
-------------------------------------------------------------------
|
|
slack 4.663
|
|
|
|
Slack (MET) : 4.672ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][18]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 7.878ns (logic 0.642ns (8.149%) route 7.236ns (91.851%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.049ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.806 5.209 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X97Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][18]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.560 10.886
|
|
clock pessimism -0.507 10.379
|
|
clock uncertainty -0.093 10.286
|
|
SLICE_X97Y85 FDCE (Recov_fdce_C_CLR) -0.405 9.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][18]
|
|
-------------------------------------------------------------------
|
|
required time 9.881
|
|
arrival time -5.209
|
|
-------------------------------------------------------------------
|
|
slack 4.672
|
|
|
|
Slack (MET) : 4.672ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][9]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 7.878ns (logic 0.642ns (8.149%) route 7.236ns (91.851%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.049ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.806 5.209 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X97Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][9]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.560 10.886
|
|
clock pessimism -0.507 10.379
|
|
clock uncertainty -0.093 10.286
|
|
SLICE_X97Y85 FDCE (Recov_fdce_C_CLR) -0.405 9.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][9]
|
|
-------------------------------------------------------------------
|
|
required time 9.881
|
|
arrival time -5.209
|
|
-------------------------------------------------------------------
|
|
slack 4.672
|
|
|
|
Slack (MET) : 4.673ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][12]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 7.884ns (logic 0.642ns (8.143%) route 7.242ns (91.857%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.055ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 10.892 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.812 5.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X101Y89 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][12]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.566 10.892
|
|
clock pessimism -0.507 10.385
|
|
clock uncertainty -0.093 10.292
|
|
SLICE_X101Y89 FDCE (Recov_fdce_C_CLR) -0.405 9.887 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][12]
|
|
-------------------------------------------------------------------
|
|
required time 9.887
|
|
arrival time -5.214
|
|
-------------------------------------------------------------------
|
|
slack 4.673
|
|
|
|
Slack (MET) : 4.673ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][13]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 7.884ns (logic 0.642ns (8.143%) route 7.242ns (91.857%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.055ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 10.892 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.812 5.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X101Y89 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][13]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.566 10.892
|
|
clock pessimism -0.507 10.385
|
|
clock uncertainty -0.093 10.292
|
|
SLICE_X101Y89 FDCE (Recov_fdce_C_CLR) -0.405 9.887 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][13]
|
|
-------------------------------------------------------------------
|
|
required time 9.887
|
|
arrival time -5.214
|
|
-------------------------------------------------------------------
|
|
slack 4.673
|
|
|
|
Slack (MET) : 4.673ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][19]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 7.884ns (logic 0.642ns (8.143%) route 7.242ns (91.857%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.055ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 10.892 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.812 5.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X101Y89 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][19]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.566 10.892
|
|
clock pessimism -0.507 10.385
|
|
clock uncertainty -0.093 10.292
|
|
SLICE_X101Y89 FDCE (Recov_fdce_C_CLR) -0.405 9.887 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][19]
|
|
-------------------------------------------------------------------
|
|
required time 9.887
|
|
arrival time -5.214
|
|
-------------------------------------------------------------------
|
|
slack 4.673
|
|
|
|
Slack (MET) : 4.673ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][20]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 7.884ns (logic 0.642ns (8.143%) route 7.242ns (91.857%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.055ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 10.892 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.812 5.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X101Y89 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][20]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.566 10.892
|
|
clock pessimism -0.507 10.385
|
|
clock uncertainty -0.093 10.292
|
|
SLICE_X101Y89 FDCE (Recov_fdce_C_CLR) -0.405 9.887 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][20]
|
|
-------------------------------------------------------------------
|
|
required time 9.887
|
|
arrival time -5.214
|
|
-------------------------------------------------------------------
|
|
slack 4.673
|
|
|
|
Slack (MET) : 4.680ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][20]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 7.954ns (logic 0.642ns (8.071%) route 7.312ns (91.929%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.047ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.116ns = ( 10.884 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.883 5.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X90Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][20]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.558 10.884
|
|
clock pessimism -0.507 10.377
|
|
clock uncertainty -0.093 10.284
|
|
SLICE_X90Y94 FDCE (Recov_fdce_C_CLR) -0.319 9.965 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][20]
|
|
-------------------------------------------------------------------
|
|
required time 9.965
|
|
arrival time -5.285
|
|
-------------------------------------------------------------------
|
|
slack 4.680
|
|
|
|
Slack (MET) : 4.680ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][21]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 7.954ns (logic 0.642ns (8.071%) route 7.312ns (91.929%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.047ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.116ns = ( 10.884 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.883 5.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X90Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][21]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.558 10.884
|
|
clock pessimism -0.507 10.377
|
|
clock uncertainty -0.093 10.284
|
|
SLICE_X90Y94 FDCE (Recov_fdce_C_CLR) -0.319 9.965 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][21]
|
|
-------------------------------------------------------------------
|
|
required time 9.965
|
|
arrival time -5.285
|
|
-------------------------------------------------------------------
|
|
slack 4.680
|
|
|
|
Slack (MET) : 4.680ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][24]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 7.954ns (logic 0.642ns (8.071%) route 7.312ns (91.929%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.047ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.116ns = ( 10.884 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.883 5.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X90Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][24]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.558 10.884
|
|
clock pessimism -0.507 10.377
|
|
clock uncertainty -0.093 10.284
|
|
SLICE_X90Y94 FDCE (Recov_fdce_C_CLR) -0.319 9.965 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][24]
|
|
-------------------------------------------------------------------
|
|
required time 9.965
|
|
arrival time -5.285
|
|
-------------------------------------------------------------------
|
|
slack 4.680
|
|
|
|
Slack (MET) : 4.680ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][14]/CLR
|
|
(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns)
|
|
Data Path Delay: 7.852ns (logic 0.642ns (8.176%) route 7.210ns (91.824%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.031ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.132ns = ( 10.868 - 13.000 )
|
|
Source Clock Delay (SCD): -2.670ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.172ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.606 -2.670
|
|
SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
|
|
SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
|
|
net (fo=1066, routed) 4.781 5.183 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0
|
|
SLICE_X86Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][14]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
13.000 13.000 r
|
|
clock source latency -5.674 7.326
|
|
propagated clock network latency
|
|
3.542 10.868
|
|
clock pessimism -0.507 10.361
|
|
clock uncertainty -0.093 10.268
|
|
SLICE_X86Y99 FDCE (Recov_fdce_C_CLR) -0.405 9.863 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][14]
|
|
-------------------------------------------------------------------
|
|
required time 9.863
|
|
arrival time -5.183
|
|
-------------------------------------------------------------------
|
|
slack 4.680
|
|
|
|
|
|
|
|
|