100 lines
3.2 KiB
Tcl
100 lines
3.2 KiB
Tcl
# Runs the currently built sdk/axi_ram.mif with the generic SoC testbench.
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# The caller is responsible for building the desired software example first.
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set script_dir [file dirname [file normalize [info script]]]
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set repo_root [file normalize [file join $script_dir ../../../..]]
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set xpr [file join $repo_root fpga project Loongson_Soc.xpr]
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set save_vcd 0
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if {[info exists ::env(SAVE_VCD)]} {
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set value [string tolower [string trim $::env(SAVE_VCD)]]
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set save_vcd [expr {$value ni {"" "0" "false" "no" "off"}}]
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}
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set sim_run_time "all"
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if {[info exists ::env(SIM_RUN_TIME)] && $::env(SIM_RUN_TIME) ne ""} {
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set sim_run_time $::env(SIM_RUN_TIME)
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}
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# xelab inherits this when compiling generated C files with the host gcc.
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set ::env(CCACHE_DISABLE) 1
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# Vivado 2019.2's bundled clang needs the matching 64-bit ncurses/tinfo pair.
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# On hosts that also carry /lib/libtinfo.so.5, the loader may otherwise mix it
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# with /lib64/libncurses.so.5 and fail with an unresolved _nc_tiparm symbol.
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if {[info exists ::env(LD_LIBRARY_PATH)] && $::env(LD_LIBRARY_PATH) ne ""} {
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append ::env(LD_LIBRARY_PATH) ":/lib64"
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} else {
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set ::env(LD_LIBRARY_PATH) "/lib64"
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}
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if {![file exists $xpr]} {
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puts stderr "ERROR: project not found: $xpr"
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exit 2
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}
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if {![file exists [file join $repo_root sdk axi_ram.mif]]} {
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puts stderr "ERROR: sdk/axi_ram.mif not found; build a software example first"
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exit 3
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}
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open_project $xpr
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set simset [get_filesets sim_1]
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set_property top tb_top $simset
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set_property incremental false $simset
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set_property xsim.elaborate.mt_level off $simset
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set_property xsim.elaborate.debug_level [expr {$save_vcd ? "typical" : "off"}] $simset
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set_property xsim.simulate.log_all_signals false $simset
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if {$save_vcd} {
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# launch_simulation normally runs 1000 ns before returning. Start at 0 ns
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# so the VCD includes power-on reset and reset release.
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set_property xsim.simulate.runtime 0ns $simset
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}
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update_compile_order -fileset sim_1
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launch_simulation
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if {$save_vcd} {
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if {![info exists ::env(SOC_VCD_PATH)] || $::env(SOC_VCD_PATH) eq ""} {
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puts stderr "ERROR: SAVE_VCD requires SOC_VCD_PATH"
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close_sim
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close_project
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exit 4
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}
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set vcd_path [file normalize $::env(SOC_VCD_PATH)]
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set vcd_patterns [list \
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/tb_top/clk \
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/tb_top/reset \
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/tb_top/UART_TX \
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/tb_top/uart_wen \
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/tb_top/uart_data \
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/tb_top/debug_wb_pc]
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if {[info exists ::env(VCD_SCOPE)] && $::env(VCD_SCOPE) ne ""} {
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set vcd_patterns [list $::env(VCD_SCOPE)]
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set vcd_objects [get_objects -quiet -r {*}$vcd_patterns]
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} else {
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# Keep the default trace small. Recursive collection is only enabled
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# when the caller explicitly supplies VCD_SCOPE.
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set vcd_objects [get_objects -quiet {*}$vcd_patterns]
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}
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if {[llength $vcd_objects] == 0} {
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puts stderr "ERROR: VCD scope matched no simulation objects: $vcd_patterns"
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close_sim
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close_project
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exit 5
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}
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file mkdir [file dirname $vcd_path]
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puts "Recording VCD: $vcd_path (scope: $vcd_patterns)"
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open_vcd $vcd_path
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log_vcd $vcd_objects
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}
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puts "Running simulation for: $sim_run_time"
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run $sim_run_time
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if {$save_vcd} {
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close_vcd
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}
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close_sim
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close_project
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exit 0
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