34 lines
1.2 KiB
VHDL
34 lines
1.2 KiB
VHDL
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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-- --------------------------------------------------------------------------------
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-- Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
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-- Date : Tue Jul 7 23:25:51 2026
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-- Host : fedora running 64-bit unknown
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-- Command : write_vhdl -force -mode synth_stub
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-- /home/fallensigh/Dev/ciciec2026_loongson_regional/rtl/ip/PLL_2019_2/clk_pll_stub.vhdl
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-- Design : clk_pll
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-- Purpose : Stub declaration of top-level module interface
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-- Device : xc7a200tfbg676-1
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-- --------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity clk_pll is
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Port (
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cpu_clk : out STD_LOGIC;
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sys_clk : out STD_LOGIC;
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mlkem_clk : out STD_LOGIC;
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resetn : in STD_LOGIC;
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locked : out STD_LOGIC;
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clk_in1 : in STD_LOGIC
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);
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end clk_pll;
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architecture stub of clk_pll is
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attribute syn_black_box : boolean;
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attribute black_box_pad_pin : string;
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attribute syn_black_box of stub : architecture is true;
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attribute black_box_pad_pin of stub : architecture is "cpu_clk,sys_clk,mlkem_clk,resetn,locked,clk_in1";
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begin
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end;
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