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FallenSigh c37f493bcb Compute matmul CRC before result store

2026-07-04 19:45:22 +08:00

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common_func.h

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

confreg_time.h

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

core_time.h

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

dma.h

Compute matmul CRC before result store

2026-07-04 19:45:22 +08:00

dvi.h

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

fft.h

Use uncached ExtRAM access (0xBC400000) to bypass CPU data cache

2026-06-24 02:04:40 +08:00

handler.h

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

led.h

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

regdef.h

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

seg7.h

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

uart_print.h

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00